bbracker
8338b3bd34
expanded GPIO testing and caught small GPIO bug
2021-06-03 10:03:09 -04:00
Ross Thompson
db2a38c300
Fixed a few lint errors,
...
clock gater was wrong,
missing signal definitions in branch predictor.
2021-06-02 09:33:24 -05:00
bbracker
4f03ecb6ec
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-06-02 10:03:23 -04:00
bbracker
28abd28b1f
fixed InstrValid signals and implemented less costly MEPC loading
2021-06-02 10:03:19 -04:00
Kip Macsai-Goren
f7deda0514
implemented Sv48.
2021-06-01 17:50:37 -04:00
James E. Stine
7f5e5287b0
delete div.bak
2021-06-01 17:39:54 -04:00
Ross Thompson
2093e7cce3
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-06-01 15:20:37 -05:00
Ross Thompson
7afbd8d877
The clock gater was not implemented correctly. Now it is level sensitive to a low clock.
2021-06-01 15:05:22 -05:00
James E. Stine
2c140679e3
Minor cosmetic update to fpu.sv
2021-06-01 15:45:32 -04:00
James E. Stine
bccdd2c137
Updates to muldiv.sv for 32-bit div/rem
2021-06-01 15:31:07 -04:00
Ross Thompson
8e330367ac
added clock gater to floating point divider to speed up simulation time.
2021-06-01 13:46:21 -05:00
Ross Thompson
605ceb7ddb
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-06-01 12:42:21 -05:00
Ross Thompson
f5aa5d7c67
Forgot to include the new gshare predictor file.
2021-06-01 12:42:03 -05:00
Kip Macsai-Goren
8f7e69715d
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-06-01 13:20:39 -04:00
Ross Thompson
8f9680556f
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-06-01 11:33:12 -05:00
Ross Thompson
5bc2a8b346
Now have global history working correctly.
2021-06-01 10:57:43 -05:00
James E. Stine
927aec34a2
Modify muldiv.sv to handle W instructions for 64-bits
2021-05-31 23:27:42 -04:00
Ross Thompson
1db8d0e59c
may have fixed the global branch history predictor.
...
The solution required a completed rewrite and understanding of how the GHR needs to be speculatively updated and repaired.
2021-05-31 16:11:12 -05:00
Kip Macsai-Goren
42af5f9818
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-05-31 11:01:15 -04:00
James E. Stine
a71b97e878
Cosmetic changes on integer divider
2021-05-31 09:16:30 -04:00
James E. Stine
2f365a9e07
Add enhancements to integer divider including:
...
- better comments
- optimize FSM to end earlier
- passes for 32-bit or 64-bit depending on parameter to intdiv
Left div.bak in just in case have to revert back to original for now.
2021-05-31 09:12:21 -04:00
James E. Stine
889b935630
Modify elements of generics for LZD and shifter wrote for integer
...
divider.
2021-05-31 08:36:19 -04:00
bbracker
a45b61ede9
turns out I should not have tried renaming FStallD to FPUStallD because that name was already used! All the same it does feel weird to have two such signals floating around \(ah pun!\)
2021-05-28 23:11:37 -04:00
Kip Macsai-Goren
529226ac8d
made priority encoder parameterizable
2021-05-28 18:09:28 -04:00
Ross Thompson
40bdcda32d
It's a bit sloppy, but the global history predictor is working correctly now.
...
There were two major bugs with the predictor.
First the update mechanism was completely wrong. The PHT is updated with the GHR that was used to lookup the prediction. PHT[GHR] = Sat2(PHT[GHR], branch outcome).
Second the GHR needs to be updated speculatively as the branch is predicted. This is important so that back to back branches' GHRs are not the same. The must be different to avoid aliasing. Speculation of the GHR update allows them to be different. On mis prediction the GHR must be reverted.
This implementation is a bit sloppy with names and now the GHR recovery is performed. Updates to follow.
2021-05-27 23:06:28 -05:00
Katherine Parry
0646e08609
classify unit created and passes imperas tests
2021-05-27 18:53:55 -04:00
Katherine Parry
65eca433b6
All compare instructions pass imperas tests
2021-05-27 15:23:28 -04:00
Katherine Parry
bd05de0dbb
FADD and FSUB imperas tests pass
2021-05-26 12:33:33 -04:00
James E. Stine
e3b3321f91
delete old file for FPregfile
2021-05-26 09:13:09 -05:00
James E. Stine
cc2a7ced7f
Add regression test for fpadd
2021-05-26 09:12:37 -05:00
Katherine Parry
3869a73a9c
renamed top level FPU wires
2021-05-25 20:04:34 -04:00
Ross Thompson
735e511073
fixed bug with icache miss spill fsm branch.
2021-05-25 14:26:22 -05:00
James E. Stine
e32e812f6a
Update FPregfile to use more compact code and better structure for ease in reading
2021-05-25 13:21:59 -05:00
Ross Thompson
aa9a81b760
Merge remote-tracking branch 'refs/remotes/origin/main' into main
2021-05-24 23:25:36 -05:00
Ross Thompson
13034c7406
Fixed bug in the two bit sat counter branch predictor. The SRAM needs to be read enabled by StallF.
2021-05-24 23:24:54 -05:00
James E. Stine
bbc1dfb309
Minor cosmetic elements on div.sv
2021-05-24 19:30:28 -05:00
James E. Stine
1704fdc877
Mod for DIV/REM instruction and update to div.sv unit
2021-05-24 19:29:13 -05:00
Ross Thompson
3c5e87d6c2
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-05-24 14:28:41 -05:00
Katherine Parry
03aea055fa
FMV.X.D imperas test passes
2021-05-24 14:44:30 -04:00
Ross Thompson
dd26b754eb
Fixed minor bug in instruction class decoding.
2021-05-24 13:41:14 -05:00
Ross Thompson
b06fda88ff
Fixed bug with instruction classification. The class decoder was incorretly labeling jalr acting as both jalr and jr (no link).
2021-05-24 12:37:16 -05:00
James E. Stine
194c32defa
Update header for FPadd
2021-05-24 08:28:16 -05:00
Katherine Parry
55f22979ca
FSD and FLD imperas tests pass
2021-05-23 18:33:14 -04:00
Katherine Parry
71e4a10efb
FMV.D.X imperas test passes
2021-05-20 22:17:59 -04:00
bbracker
8554f2f3cd
plic implementation optimizations
2021-05-19 18:10:48 +00:00
Katherine Parry
409438bc95
floating point infinite loop removed from imperas tests
2021-05-18 10:42:51 -04:00
James E. Stine
49cc330bd9
Forgot initialization config for div - apologies
2021-05-17 17:12:27 -05:00
James E. Stine
96eca3287f
Add 32/64-bit shifter for update to shifter block
2021-05-17 17:02:13 -05:00
James E. Stine
97cbdae674
Updates on Divide - pushed in working version of DIV64U for Divide and REmainder. Will do 32-bit version tomorrow as well as Signed version
2021-05-17 16:48:51 -05:00
Thomas Fleming
fda439b51e
Fix comment
2021-05-14 08:06:07 -04:00
Thomas Fleming
1fc607b399
Remove busy-mmu and fix missing signal
2021-05-14 07:14:20 -04:00
Thomas Fleming
980c00fa64
Clean up MMU code
2021-05-14 07:12:32 -04:00
Thomas Fleming
1e0a5ef807
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-05-04 15:22:21 -04:00
bbracker
535046e494
small synthesis fixes
2021-05-04 15:21:01 -04:00
Thomas Fleming
37bba95500
Fix compiler warning in PMP checker
2021-05-04 15:18:08 -04:00
Ross Thompson
2aa4db470b
Fixed synthesis bug with icache valid bit.
2021-05-04 13:03:08 -05:00
Ross Thompson
87d3869a6e
Fixed icache pcmux control for handling miss spill miss.
2021-05-04 11:05:01 -05:00
Thomas Fleming
dac07e34cf
Fix bug in PMP checker
...
Now we only enforce PMP regions if at least one is non-null
2021-05-04 03:14:07 -04:00
Thomas Fleming
d7fa0903bc
Disable PMP checker to fix test loops
...
There is a bug in the PMP checker where S or U mode attempts to make a
memory access while no PMP registers are set. We currently treat this as
a failure, when this should instead be allowed.
2021-05-04 01:56:05 -04:00
Thomas Fleming
d53afc8510
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-05-03 23:15:39 -04:00
Domenico Ottolia
a7e89f43c1
Fix bug with IllegalInstrFaultM not getting correct value
2021-05-03 22:48:03 -04:00
Thomas Fleming
f78f2b3b5d
Adjust attributes in PMA checker
2021-05-03 21:58:32 -04:00
David Harris
96e90402c5
Rolled back fflush on uart. Use -syncio in Modelsim command line instead.
2021-05-03 20:04:44 -04:00
David Harris
062120f944
Flush uart print statements on \n
2021-05-03 19:51:51 -04:00
David Harris
743011194b
Flush uart print statements on \n
2021-05-03 19:41:37 -04:00
David Harris
8758b6efa1
Flush uart print statements on \n
2021-05-03 19:37:45 -04:00
David Harris
2f5649832a
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-05-03 19:29:01 -04:00
David Harris
1f2da4c457
Flush uart print statements on \n
2021-05-03 19:25:28 -04:00
Ross Thompson
6a01ea9f2d
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-05-03 16:57:36 -05:00
Ross Thompson
ed4f2ecb24
fixed subtle typo in icache fsm. Was messing up hit spill hit.
...
I believe the mibench qsort benchmark runs after this icache fix.
2021-05-03 16:55:36 -05:00
Domenico Ottolia
ab68933466
Fix bug that caused stvec to get the wrong value
2021-05-03 17:54:57 -04:00
Thomas Fleming
3f7061d557
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-05-03 17:38:13 -04:00
Thomas Fleming
86a93d77b4
Implement PMP checker and revise PMA checker
2021-05-03 17:37:42 -04:00
Thomas Fleming
00c3b5a033
Remove remnants of InstrReadC
2021-05-03 17:36:25 -04:00
Ross Thompson
0a44d4dd4e
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-05-03 14:53:54 -05:00
Ross Thompson
e09ac73eaf
Removed combinational loops between icache and PMA checker.
2021-05-03 14:51:25 -05:00
Ross Thompson
7185905f7b
Reduced icache to 1 port memory.
2021-05-03 14:47:49 -05:00
Katherine Parry
3f05e31954
fpu warnings fixed/commented
2021-05-03 19:17:09 +00:00
Thomas Fleming
94d734cca9
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
...
Conflicts:
wally-pipelined/src/ebu/ahblite.sv
2021-05-03 14:02:19 -04:00
Ross Thompson
12b978fec2
Eliminated extra register and fixed ports to icache.
...
Still need to support physical tag check and write in icache memory.
Still need to reduce to 1 port SRAM in icache.
I would like to refactor the icache code.
2021-05-03 12:04:54 -05:00
bbracker
8ec0d18444
merge conflict resolved -- Ross and I made the same fix
2021-05-03 10:10:42 -04:00
Ross Thompson
b57c187208
Fixed typo in ifu for bypassing branch predictor.
...
Fixed missing signal name in local history predictor.
2021-05-03 08:56:45 -05:00
David Harris
c9806fb472
Fixed lint error in div
2021-05-03 09:26:12 -04:00
bbracker
fb0910d9c0
ifu lint fixes
2021-05-03 09:25:22 -04:00
bbracker
acd99be7f8
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-05-03 09:23:52 -04:00
Katherine Parry
9252d08b41
fpu imperas tests run
2021-05-01 02:18:01 +00:00
bbracker
0d62440f60
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-04-30 06:26:35 -04:00
bbracker
9c08ce5359
rv32 plic test and lint fixes
2021-04-30 06:26:31 -04:00
Domenico Ottolia
830787e3e1
Make vectored interrupt trap handling work, and add tests for mtvec with vectored interrupts
2021-04-29 20:42:14 -04:00
Thomas Fleming
10c7260980
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-04-29 16:30:00 -04:00
ushakya22
de23edcfb9
fix to pcm bug
2021-04-29 15:21:08 -04:00
Jarred Allen
000f48cd75
Fix compile error in branch predictor
2021-04-29 14:36:56 -04:00
Shreya Sanghai
b554dc8e72
fixed bug in gshare, global and local history BP
2021-04-29 06:14:32 -04:00
Thomas Fleming
e091f430e0
Clean up PMA checker and begin PMP checker
2021-04-29 02:20:39 -04:00
Ross Thompson
14a69c1d06
Added the ability to exclude branch predictor.
2021-04-26 14:27:42 -05:00
Ross Thompson
a7e4d39ea1
Fixed issue with not saving the first cache block read on a miss spill.
2021-04-26 12:57:34 -05:00
Ross Thompson
44d28dbd1c
Icache integrated!
...
Merge branch 'icache-almost-working' into main
2021-04-26 11:48:58 -05:00
bbracker
f921886451
merge cleanup; mem init is broken
2021-04-26 08:00:17 -04:00
bbracker
7947858481
it says I need to merge in order to pull
2021-04-26 07:46:24 -04:00
bbracker
8d77012995
progress on bus and lrsc
2021-04-26 07:43:16 -04:00
