David Harris
8795a9db7a
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2023-12-31 20:26:47 -08:00
David Harris
536539237c
Fixed exclusion tags in pmachecker
2023-12-31 20:20:31 -08:00
David Harris
430d495ce5
Updated to latest riscv-arch-test
2023-12-31 10:04:20 -08:00
David Harris
52b6d1d163
restored tlbNAPOT coverage tests
2023-12-31 09:55:58 -08:00
David Harris
17cbdb53df
Progress on Verilator simulation. Full adder compiles and runs. Wally builds.
2023-12-31 09:53:13 -08:00
David Harris
cd985a44d9
Merge pull request #544 from ross144/main
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Update structural hazards, cbo.zero works for uncache memory.
2023-12-29 15:00:44 -08:00
Rose Thompson
626b89320c
More cleanup.
2023-12-29 16:51:39 -06:00
Rose Thompson
730efefc41
Cleanup.
2023-12-29 16:18:30 -06:00
Rose Thompson
6a787981c2
Restored cache store delay hazard.
2023-12-29 16:10:27 -06:00
Rose Thompson
0264a17f77
Reverted dtim to use store delay stall, but only (load after store).
2023-12-29 16:06:30 -06:00
Rose Thompson
fbab9f6c6d
Updated comments about AMO and CMO stalls.
2023-12-29 15:31:11 -06:00
Rose Thompson
f59fa5089d
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-12-29 15:13:18 -06:00
Rose Thompson
69ffc67cd2
Merge pull request #542 from davidharrishmc/dev
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Merged forward/stall detection logic into controller, renamed CMOp to CMOpM
2023-12-29 13:11:53 -08:00
Rose Thompson
bd0672f074
Merge branch 'main' into dev
2023-12-29 13:11:43 -08:00
Rose Thompson
8030b7d100
Added partial code for uncached amo operations.
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Minor fix for Makefile so coverage tests build.
2023-12-29 15:07:20 -06:00
Rose Thompson
7afeee9807
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-12-29 14:49:36 -06:00
David Harris
eb55a24d27
Merge pull request #543 from jordancarlin/main
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fixed coverage exclusions in lsu and ifu
2023-12-29 11:24:27 -08:00
Jordan Carlin
2fa243c46e
fixed coverage exclusions in lsu and ifu
2023-12-29 11:18:23 -08:00
Rose Thompson
52dad4f130
cbo.zero works for uncached memory now!
2023-12-29 11:11:06 -06:00
Rose Thompson
d1456b2471
Progress on fixing cbo.zero for uncached memory regions.
2023-12-29 11:03:38 -06:00
Rose Thompson
482529394a
Fixed some of the uncached ifu bugs.
2023-12-29 09:53:22 -06:00
David Harris
2c2f692f3a
Moved forwarding logic into controller
2023-12-26 21:17:01 -08:00
David Harris
8196ab20be
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2023-12-25 06:26:00 -08:00
David Harris
7f31a031bc
Temporarily removed zicboz and zcb tests from regression until they work
2023-12-25 06:02:28 -08:00
David Harris
86279ca68d
Removed old comment from wally-tool-chain-install
2023-12-25 05:58:55 -08:00
David Harris
e8df856fdb
Renamed CMOp to CMOpM in mmu and cache
2023-12-25 05:57:41 -08:00
Rose Thompson
b701cbf823
Merge pull request #540 from davidharrishmc/dev
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Fix Timer Interrupt Issue #530 and coverage/tlbNAPOT tests #457
2023-12-21 12:30:06 -08:00
David Harris
6395cd0284
Reversed numbering of adrdecs to make it easier to add new peripherals without renumbering the old ones; update figure to match
2023-12-21 12:29:37 -08:00
David Harris
b3ff1035c4
Propagated MIP-based tracer interrupts to testbench-linux-imperas
2023-12-21 11:47:49 -08:00
David Harris
45b5658d06
Updated Imperas testbench to use MIP bits to communicate pending interrupts
2023-12-21 11:05:26 -08:00
David Harris
c1ad6602a3
Added commented out B extension MISA to imperas.ic; not yet working
2023-12-21 11:04:41 -08:00
David Harris
dc3284049c
Rolled back B extension in rv32/64gc MISA because imperasDV isn't matching
2023-12-21 11:03:50 -08:00
David Harris
b025cd8a0d
Updated tlbNAPOT to test instructions as well
2023-12-20 23:01:35 -08:00
David Harris
9ced88c55c
Fixed tlbNAPOT test to run and makefile to gather coverage stats
2023-12-20 21:45:14 -08:00
Rose Thompson
c743f27cf2
Merge pull request #539 from davidharrishmc/dev
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PC logic moved from privileged unit to IFU. Adopting more of Zicboz, Zcb, E tests from riscv-arch-test
2023-12-20 21:33:12 -08:00
David Harris
06ddccd983
Fixed typo in IFU
2023-12-20 20:22:17 -08:00
David Harris
09ea6e6485
Set B in MISA for rv32gc and rv64gc
2023-12-20 16:29:31 -08:00
David Harris
d130a78616
Updated to current version of toolchain and prepare to be able to compile Zcb and Zicboz when supported
2023-12-20 16:29:03 -08:00
David Harris
8eace30f49
Moved UnalignedPCNextF mux into IFU
2023-12-20 16:18:31 -08:00
David Harris
0ff049db86
Removed unused tests from wally-riscv-arch-test
2023-12-20 13:34:12 -08:00
David Harris
8552369687
Merged PR538, delete unused tests
2023-12-20 13:30:31 -08:00
David Harris
2236e2c93c
Merge pull request #538 from ross144/main
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Got Verilator compiling! and Questa still simulates
2023-12-20 13:18:08 -08:00
Rose Thompson
70d0169019
All regression tests which matter are running!
2023-12-20 14:57:52 -06:00
Rose Thompson
1b59182d59
Updated tests with ending label.
2023-12-20 14:55:37 -06:00
Rose Thompson
b68dd74f89
Reverted logic to bit change.
2023-12-20 13:16:32 -06:00
Rose Thompson
f52ad13a65
Merge branch 'fix'
2023-12-20 13:10:30 -06:00
Rose Thompson
18a96740d5
Revert RAM logic to bit change.
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Added logic to hptw to prevent x propagation.
2023-12-20 13:10:20 -06:00
Rose Thompson
a8ab3c8342
Ok that is a stange bug.
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The testbench used logic for the shadow ram, but the memory used bit. This caused questa to allocate huge amounts of memory and crash. Changing shadow ram to bit fixed the issue.
2023-12-20 12:25:34 -06:00
Rose Thompson
9de434a61b
"Resolved" ram preload issues by replacing the RAM's types with bit from logic. Tested fpga synthesis.
2023-12-20 12:05:25 -06:00
Rose Thompson
9ee1ffe8fe
Almost working with modelsim and verilator.
2023-12-20 11:29:31 -06:00
