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Merge pull request #539 from davidharrishmc/dev

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PC logic moved from privileged unit to IFU.  Adopting more of Zicboz, Zcb, E tests from riscv-arch-test
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Rose Thompson 2023-12-20 21:33:12 -08:00 committed by GitHub
commit c743f27cf2
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171 changed files with 210 additions and 207264 deletions
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13
bin/wally-tool-chain-install.sh
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@ -69,9 +69,9 @@ cd $RISCV
git clone https://github.com/riscv/riscv-gnu-toolchain
cd riscv-gnu-toolchain
# Temporarily use the following commands until gcc-13 is part of riscv-gnu-toolchain (issue #1249)
git clone https://github.com/gcc-mirror/gcc -b releases/gcc-13 gcc-13
./configure --prefix=/opt/riscv --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" --with-gcc-src=`pwd`/gcc-13
#./configure --prefix=${RISCV} --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;"
#git clone https://github.com/gcc-mirror/gcc -b releases/gcc-13 gcc-13
#./configure --prefix=/opt/riscv --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" --with-gcc-src=`pwd`/gcc-13
./configure --prefix=${RISCV} --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;"
make -j ${NUM_THREADS}
# elf2hex (https://github.com/sifive/elf2hex)
@ -151,20 +151,21 @@ sudo make install
cd $RISCV
opam init -y --disable-sandboxing
opam switch create ocaml-base-compiler.4.08.0
opam switch create 5.1.0
opam install sail -y
eval $(opam config env)
git clone https://github.com/riscv/sail-riscv.git
cd sail-riscv
# For now, use checkout that is stable for Wally
git checkout 72b2516d10d472ac77482fd959a9401ce3487f60
#git checkout 72b2516d10d472ac77482fd959a9401ce3487f60 # not new enough for Zicboz?
make -j ${NUM_THREADS}
ARCH=RV32 make -j ${NUM_THREADS}
sudo ln -sf $RISCV/sail-riscv/c_emulator/riscv_sim_RV64 /usr/bin/riscv_sim_RV64
sudo ln -sf $RISCV/sail-riscv/c_emulator/riscv_sim_RV32 /usr/bin/riscv_sim_RV32
sudo pip3 install testresources
# riscof
sudo pip3 install -U testresources riscv_config
pip3 install git+https://github.com/riscv/riscof.git
# Download OSU Skywater 130 cell library

2
config/rv32gc/config.vh
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@ -35,7 +35,7 @@ localparam XLEN = 32'd32;
// IEEE 754 compliance
localparam IEEE754 = 0;
localparam MISA = (32'h00000104 | 1 << 20 | 1 << 18 | 1 << 12 | 1 << 0 | 1 <<3 | 1 << 5);
localparam MISA = (32'h00000104 | 1 << 1 | 1 << 20 | 1 << 18 | 1 << 12 | 1 << 0 | 1 <<3 | 1 << 5);
localparam ZICSR_SUPPORTED = 1;
localparam ZIFENCEI_SUPPORTED = 1;
localparam COUNTERS = 12'd32;

2
config/rv64gc/config.vh
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@ -34,7 +34,7 @@ localparam XLEN = 32'd64;
localparam IEEE754 = 0;
// MISA RISC-V configuration per specification
localparam MISA = (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0);
localparam MISA = (32'h00000104 | 1 << 1 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0);
localparam ZICSR_SUPPORTED = 1;
localparam ZIFENCEI_SUPPORTED = 1;
localparam COUNTERS = 12'd32;

2
sim/imperas.ic
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@ -79,7 +79,7 @@
#
# SVxx Memory 0x0000000000 0x7FFFFFFFFF
#
--callcommand refRoot/cpu/setPMA -lo 0x0000000000 -hi 0x7FFFFFFFFF -attributes " ------ ---- " # INITIAL
--callcommand refRoot/cpu/setPMA -lo 0x0000000000 -hi 0x7FFFFFFFFF -attributes " ---a-- ---- " # INITIAL
--callcommand refRoot/cpu/setPMA -lo 0x0000001000 -hi 0x0000001FFF -attributes " r-x-A- 1248 " # BOOTROM
--callcommand refRoot/cpu/setPMA -lo 0x0000012100 -hi 0x000001211F -attributes " rw-aA- --48 " # SDC
--callcommand refRoot/cpu/setPMA -lo 0x0002000000 -hi 0x000200FFFF -attributes " rw-aA- 1248 " # CLINT

2
sim/regression-wally
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@ -107,7 +107,7 @@ for test in tests32i:
configs.append(tc)
tests32e = ["wally32e"]
tests32e = ["arch32e"]
for test in tests32e:
tc = TestCase(
name=test,

3
src/ieu/alu.sv
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@ -69,7 +69,7 @@ module alu import cvw::*; #(parameter cvw_t P, parameter WIDTH) (
assign LTU = ~Carry;
// Select appropriate ALU Result
always_comb begin
always_comb
case (ALUSelect)
3'b000: FullResult = Sum; // add or sub (including address generation)
3'b001: FullResult = Shift; // sll, sra, or srl
@ -80,7 +80,6 @@ module alu import cvw::*; #(parameter cvw_t P, parameter WIDTH) (
3'b110: FullResult = A | CondMaskInvB; // or, orn, bset
3'b111: FullResult = A & CondMaskInvB; // and, bclr
endcase
end
// Support RV64I W-type addw/subw/addiw/shifts that discard upper 32 bits and sign-extend 32-bit result to 64 bits
if (WIDTH == 64) assign PreALUResult = W64 ? {{32{FullResult[31]}}, FullResult[31:0]} : FullResult;

28
src/ifu/ifu.sv
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@ -56,8 +56,9 @@ module ifu import cvw::*; #(parameter cvw_t P) (
output logic BPWrongM, // Prediction is wrong
// Mem
output logic CommittedF, // I$ or bus memory operation started, delay interrupts
input logic [P.XLEN-1:0] UnalignedPCNextF, // The next PCF, but not aligned to 2 bytes.
output logic [P.XLEN-1:0] PC2NextF, // Selected PC between branch prediction and next valid PC if CSRWriteFence
input logic [P.XLEN-1:0] EPCM, // Exception Program counter from privileged unit
input logic [P.XLEN-1:0] TrapVectorM, // Trap vector, from privileged unit
input logic RetM, TrapM, // return instruction, or trap
output logic [31:0] InstrD, // The decoded instruction in Decode stage
output logic [31:0] InstrM, // The decoded instruction in Memory stage
output logic [31:0] InstrOrigM, // Original compressed or uncompressed instruction in Memory stage for Illegal Instruction MTVAL
@ -100,6 +101,9 @@ module ifu import cvw::*; #(parameter cvw_t P) (
localparam [31:0] nop = 32'h00000013; // instruction for NOP
logic [P.XLEN-1:0] PCNextF; // Next PCF, selected from Branch predictor, Privilege, or PC+2/4
logic [P.XLEN-1:0] PC1NextF; // Branch predictor next PCF
logic [P.XLEN-1:0] PC2NextF; // Selected PC between branch prediction and next valid PC if CSRWriteFence
logic [P.XLEN-1:0] UnalignedPCNextF; // The next PCF, but not aligned to 2 bytes.
logic BranchMisalignedFaultE; // Branch target not aligned to 4 bytes if no compressed allowed (2 bytes if allowed)
logic [P.XLEN-1:0] PCPlus2or4F; // PCF + 2 (CompressedF) or PCF + 4 (Non-compressed)
logic [P.XLEN-1:0] PCSpillNextF; // Next PCF after possible + 2 to handle spill
@ -128,7 +132,6 @@ module ifu import cvw::*; #(parameter cvw_t P) (
logic IFUCacheBusStallF; // EIther I$ or bus busy with multicycle operation
logic GatedStallD; // StallD gated by selected next spill
// branch predictor signal
logic [P.XLEN-1:0] PC1NextF; // Branch predictor next PCF
logic BusCommittedF; // Bus memory operation in flight, delay interrupts
logic CacheCommittedF; // I$ memory operation started, delay interrupts
logic SelIROM; // PMA indicates instruction address is in the IROM
@ -300,20 +303,25 @@ module ifu import cvw::*; #(parameter cvw_t P) (
mux2 #(P.XLEN) pcmux2(.d0(PC1NextF), .d1(NextValidPCE), .s(CSRWriteFenceM),.y(PC2NextF));
else assign PC2NextF = PC1NextF;
mux3 #(P.XLEN) pcmux3(PC2NextF, EPCM, TrapVectorM, {TrapM, RetM}, UnalignedPCNextF);
mux2 #(P.XLEN) pcresetmux({UnalignedPCNextF[P.XLEN-1:1], 1'b0}, P.RESET_VECTOR[P.XLEN-1:0], reset, PCNextF);
flopen #(P.XLEN) pcreg(clk, ~StallF | reset, PCNextF, PCF);
// pcadder
// add 2 or 4 to the PC, based on whether the instruction is 16 bits or 32
assign PCPlus4F = PCF[P.XLEN-1:2] + 1; // add 4 to PC
// choose PC+2 or PC+4 based on CompressedF, which arrives later.
// Speeds up critical path as compared to selecting adder input based on CompressedF
always_comb
if (CompressedF) // add 2
if (PCF[1]) PCPlus2or4F = {PCPlus4F, 2'b00};
else PCPlus2or4F = {PCF[P.XLEN-1:2], 2'b10};
else PCPlus2or4F = {PCPlus4F, PCF[1:0]}; // add 4
if (P.COMPRESSED_SUPPORTED) begin: pcadd
// choose PC+2 or PC+4 based on CompressedF, which arrives later.
// Speeds up critical path as compared to selecting adder input based on CompressedF
always_comb
if (CompressedF) // add 2
if (PCF[1]) PCPlus2or4F = {PCPlus4F, 2'b00};
else PCPlus2or4F = {PCF[P.XLEN-1:2], 2'b10};
else PCPlus2or4F = {PCPlus4F, PCF[1:0]}; // add 4
end else begin: pcadd
assign PCPlus2or4F = {PCPlus4F, PCF[1:0]}; // always add 4 if compressed instructions are not supported
end
////////////////////////////////////////////////////////////////////////////////////////////////
// Branch and Jump Predictor

14
src/privileged/csr.sv
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@ -34,7 +34,7 @@ module csr import cvw::*; #(parameter cvw_t P) (
input logic StallE, StallM, StallW,
input logic [31:0] InstrM, // current instruction
input logic [31:0] InstrOrigM, // Original compressed or uncompressed instruction in Memory stage for Illegal Instruction MTVAL
input logic [P.XLEN-1:0] PCM, PC2NextF, // program counter, next PC going to trap/return logic
input logic [P.XLEN-1:0] PCM, // program counter, next PC going to trap/return logic
input logic [P.XLEN-1:0] SrcAM, IEUAdrM, // SrcA and memory address from IEU
input logic CSRReadM, CSRWriteM, // read or write CSR
input logic TrapM, // trap is occurring
@ -86,9 +86,11 @@ module csr import cvw::*; #(parameter cvw_t P) (
output logic [3:0] ENVCFG_CBE,
output logic ENVCFG_PBMTE, // Page-based memory type enable
output logic ENVCFG_ADUE, // HPTW A/D Update enable
// PC logic output from privileged unit to IFU
output logic [P.XLEN-1:0] EPCM, // Exception Program counter to IFU PC logic
output logic [P.XLEN-1:0] TrapVectorM, // Trap vector, to IFU PC logic
//
output logic [P.XLEN-1:0] CSRReadValW, // value read from CSR
output logic [P.XLEN-1:0] UnalignedPCNextF, // Next PC, accounting for traps and returns
output logic IllegalCSRAccessM, // Illegal CSR access: CSR doesn't exist or is inaccessible at this privilege level
output logic BigEndianM // memory access is big-endian based on privilege mode and STATUS register endian fields
);
@ -117,10 +119,8 @@ module csr import cvw::*; #(parameter cvw_t P) (
logic IllegalCSRMWriteReadonlyM;
logic [P.XLEN-1:0] CSRReadVal2M;
logic [11:0] MIP_REGW_writeable;
logic [P.XLEN-1:0] TVecM, TrapVectorM, NextFaultMtvalM;
logic [P.XLEN-1:0] TVecM,NextFaultMtvalM;
logic MTrapM, STrapM;
logic [P.XLEN-1:0] EPC;
logic RetM;
logic SelMtvecM;
logic [P.XLEN-1:0] TVecAlignedM;
logic InstrValidNotFlushedM;
@ -168,9 +168,7 @@ module csr import cvw::*; #(parameter cvw_t P) (
// Trap Returns
// A trap sets the PC to TrapVector
// A return sets the PC to MEPC or SEPC
assign RetM = mretM | sretM;
mux2 #(P.XLEN) epcmux(SEPC_REGW, MEPC_REGW, mretM, EPC);
mux3 #(P.XLEN) pcmux3(PC2NextF, EPC, TrapVectorM, {TrapM, RetM}, UnalignedPCNextF);
mux2 #(P.XLEN) epcmux(SEPC_REGW, MEPC_REGW, mretM, EPCM);
///////////////////////////////////////////
// CSRWriteValM

3
src/privileged/privdec.sv
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@ -38,7 +38,7 @@ module privdec import cvw::*; #(parameter cvw_t P) (
input logic STATUS_TSR, STATUS_TVM, STATUS_TW, // status bits
output logic IllegalInstrFaultM, // Illegal instruction
output logic EcallFaultM, BreakpointFaultM, // Ecall or breakpoint; must retire, so don't flush it when the trap occurs
output logic sretM, mretM, // return instructions
output logic sretM, mretM, RetM, // return instructions
output logic wfiM, wfiW, sfencevmaM // wfi / sfence.vma / sinval.vma instructions
);
@ -66,6 +66,7 @@ module privdec import cvw::*; #(parameter cvw_t P) (
assign sretM = PrivilegedM & (InstrM[31:20] == 12'b000100000010) & rs1zeroM & P.S_SUPPORTED &
(PrivilegeModeW == P.M_MODE | PrivilegeModeW == P.S_MODE & ~STATUS_TSR);
assign mretM = PrivilegedM & (InstrM[31:20] == 12'b001100000010) & rs1zeroM & (PrivilegeModeW == P.M_MODE);
assign RetM = sretM | mretM;
assign ecallM = PrivilegedM & (InstrM[31:20] == 12'b000000000000) & rs1zeroM;
assign ebreakM = PrivilegedM & (InstrM[31:20] == 12'b000000000001) & rs1zeroM;
assign wfiM = PrivilegedM & (InstrM[31:20] == 12'b000100000101) & rs1zeroM;

19
src/privileged/privileged.sv
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@ -37,7 +37,7 @@ module privileged import cvw::*; #(parameter cvw_t P) (
input logic [31:0] InstrM, // Instruction
input logic [31:0] InstrOrigM, // Original compressed or uncompressed instruction in Memory stage for Illegal Instruction MTVAL
input logic [P.XLEN-1:0] IEUAdrM, // address from IEU
input logic [P.XLEN-1:0] PCM, PC2NextF, // program counter, next PC going to trap/return PC logic
input logic [P.XLEN-1:0] PCM, // program counter
// control signals
input logic InstrValidM, // Current instruction is valid (not flushed)
input logic CommittedM, CommittedF, // current instruction is using bus; don't interrupt
@ -85,8 +85,9 @@ module privileged import cvw::*; #(parameter cvw_t P) (
output logic [3:0] ENVCFG_CBE, // Cache block operation enables
output logic ENVCFG_PBMTE, // Page-based memory type enable
output logic ENVCFG_ADUE, // HPTW A/D Update enable
// PC logic output in privileged unit
output logic [P.XLEN-1:0] UnalignedPCNextF, // Next PC from trap/return PC logic
// PC logic output from privileged unit to IFU
output logic [P.XLEN-1:0] EPCM, // Exception Program counter to IFU PC logic
output logic [P.XLEN-1:0] TrapVectorM, // Trap vector, to IFU PC logic
// control outputs
output logic RetM, TrapM, // return instruction, or trap
output logic sfencevmaM, // sfence.vma instruction
@ -125,11 +126,11 @@ module privileged import cvw::*; #(parameter cvw_t P) (
privdec #(P) pmd(.clk, .reset, .StallW, .FlushW, .InstrM(InstrM[31:15]),
.PrivilegedM, .IllegalIEUFPUInstrM, .IllegalCSRAccessM,
.PrivilegeModeW, .STATUS_TSR, .STATUS_TVM, .STATUS_TW, .IllegalInstrFaultM,
.EcallFaultM, .BreakpointFaultM, .sretM, .mretM, .wfiM, .wfiW, .sfencevmaM);
.EcallFaultM, .BreakpointFaultM, .sretM, .mretM, .RetM, .wfiM, .wfiW, .sfencevmaM);
// Control and Status Registers
csr #(P) csr(.clk, .reset, .FlushM, .FlushW, .StallE, .StallM, .StallW,
.InstrM, .InstrOrigM, .PCM, .SrcAM, .IEUAdrM, .PC2NextF,
.InstrM, .InstrOrigM, .PCM, .SrcAM, .IEUAdrM,
.CSRReadM, .CSRWriteM, .TrapM, .mretM, .sretM, .InterruptM,
.MTimerInt, .MExtInt, .SExtInt, .MSwInt,
.MTIME_CLINT, .InstrValidM, .FRegWriteM, .LoadStallD, .StoreStallD,
@ -142,7 +143,8 @@ module privileged import cvw::*; #(parameter cvw_t P) (
.MEDELEG_REGW, .MIP_REGW, .MIE_REGW, .MIDELEG_REGW,
.SATP_REGW, .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
.SetFflagsM, .FRM_REGW, .ENVCFG_CBE, .ENVCFG_PBMTE, .ENVCFG_ADUE,
.CSRReadValW,.UnalignedPCNextF, .IllegalCSRAccessM, .BigEndianM);
.EPCM, .TrapVectorM,
.CSRReadValW, .IllegalCSRAccessM, .BigEndianM);
// pipeline early-arriving trap sources
privpiperegs ppr(.clk, .reset, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM,
@ -154,9 +156,8 @@ module privileged import cvw::*; #(parameter cvw_t P) (
.InstrMisalignedFaultM, .InstrAccessFaultM, .HPTWInstrAccessFaultM, .IllegalInstrFaultM,
.BreakpointFaultM, .LoadMisalignedFaultM, .StoreAmoMisalignedFaultM,
.LoadAccessFaultM, .StoreAmoAccessFaultM, .EcallFaultM, .InstrPageFaultM,
.LoadPageFaultM, .StoreAmoPageFaultM,
.mretM, .sretM, .PrivilegeModeW,
.LoadPageFaultM, .StoreAmoPageFaultM, .PrivilegeModeW,
.MIP_REGW, .MIE_REGW, .MIDELEG_REGW, .MEDELEG_REGW, .STATUS_MIE, .STATUS_SIE,
.InstrValidM, .CommittedM, .CommittedF,
.TrapM, .RetM, .wfiM, .wfiW, .InterruptM, .ExceptionM, .IntPendingM, .DelegateM, .CauseM);
.TrapM, .wfiM, .wfiW, .InterruptM, .ExceptionM, .IntPendingM, .DelegateM, .CauseM);
endmodule

15
src/privileged/trap.sv
View File

@ -32,7 +32,6 @@ module trap import cvw::*; #(parameter cvw_t P) (
input logic BreakpointFaultM, LoadMisalignedFaultM, StoreAmoMisalignedFaultM,
input logic LoadAccessFaultM, StoreAmoAccessFaultM, EcallFaultM, InstrPageFaultM,
input logic LoadPageFaultM, StoreAmoPageFaultM, // various trap sources
input logic mretM, sretM, // return instructions
input logic wfiM, wfiW, // wait for interrupt instruction
input logic [1:0] PrivilegeModeW, // current privilege mode
input logic [11:0] MIP_REGW, MIE_REGW, MIDELEG_REGW, // interrupt pending, enabled, and delegate CSRs
@ -41,7 +40,6 @@ module trap import cvw::*; #(parameter cvw_t P) (
input logic InstrValidM, // current instruction is valid, not flushed
input logic CommittedM, CommittedF, // LSU/IFU has committed to a bus operation that can't be interrupted
output logic TrapM, // Trap is occurring
output logic RetM, // Return instruction being executed
output logic InterruptM, // Interrupt is occurring
output logic ExceptionM, // exception is occurring
output logic IntPendingM, // Interrupt is pending, might occur if enabled
@ -74,7 +72,7 @@ module trap import cvw::*; #(parameter cvw_t P) (
(PrivilegeModeW == P.U_MODE | PrivilegeModeW == P.S_MODE);
///////////////////////////////////////////
// Trigger Traps and RET
// Trigger Traps
// According to RISC-V Spec Section 1.6, exceptions are caused by instructions. Interrupts are external asynchronous.
// Traps are the union of exceptions and interrupts.
///////////////////////////////////////////
@ -89,7 +87,6 @@ module trap import cvw::*; #(parameter cvw_t P) (
LoadAccessFaultM | StoreAmoAccessFaultM;
// coverage on
assign TrapM = (ExceptionM & ~CommittedF) | InterruptM; // *** RT: review this additional ~CommittedF with DH and update priv chapter.
assign RetM = mretM | sretM;
///////////////////////////////////////////
// Cause priority defined in privileged spec
@ -112,11 +109,13 @@ module trap import cvw::*; #(parameter cvw_t P) (
// coverage on
else if (BreakpointFaultM) CauseM = 3;
else if (EcallFaultM) CauseM = {2'b10, PrivilegeModeW};
else if (LoadMisalignedFaultM) CauseM = 4;
else if (StoreAmoMisalignedFaultM) CauseM = 6;
else if (LoadPageFaultM) CauseM = 13;
else if (StoreAmoMisalignedFaultM & ~P.ZICCLSM_SUPPORTED) CauseM = 6; // misaligned faults are higher priority if they always are taken
else if (LoadMisalignedFaultM & ~P.ZICCLSM_SUPPORTED) CauseM = 4;
else if (StoreAmoPageFaultM) CauseM = 15;
else if (LoadAccessFaultM) CauseM = 5;
else if (LoadPageFaultM) CauseM = 13;
else if (StoreAmoAccessFaultM) CauseM = 7;
else if (LoadAccessFaultM) CauseM = 5;
else if (StoreAmoMisalignedFaultM & P.ZICCLSM_SUPPORTED) CauseM = 6; // See priority in Privileged Spec 3.1.15
else if (LoadMisalignedFaultM & P.ZICCLSM_SUPPORTED) CauseM = 4;
else CauseM = 0;
endmodule

16
src/wally/wallypipelinedcore.sv
View File

@ -48,8 +48,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
logic StallF, StallD, StallE, StallM, StallW;
logic FlushD, FlushE, FlushM, FlushW;
logic RetM;
logic TrapM;
logic TrapM, RetM;
// signals that must connect through DP
logic IntDivE, W64E;
@ -63,7 +62,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
logic [P.XLEN-1:0] PCSpillF, PCE, PCLinkE;
logic [P.XLEN-1:0] PCM;
logic [P.XLEN-1:0] CSRReadValW, MDUResultW;
logic [P.XLEN-1:0] UnalignedPCNextF, PC2NextF;
logic [P.XLEN-1:0] EPCM, TrapVectorM;
logic [1:0] MemRWE;
logic [1:0] MemRWM;
logic InstrValidD, InstrValidE, InstrValidM;
@ -173,13 +172,13 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
.InstrValidE, .InstrValidD,
.BranchD, .BranchE, .JumpD, .JumpE, .ICacheStallF,
// Fetch
.HRDATA, .PCSpillF, .IFUHADDR, .PC2NextF,
.HRDATA, .PCSpillF, .IFUHADDR,
.IFUStallF, .IFUHBURST, .IFUHTRANS, .IFUHSIZE, .IFUHREADY, .IFUHWRITE,
.ICacheAccess, .ICacheMiss,
// Execute
.PCLinkE, .PCSrcE, .IEUAdrE, .IEUAdrM, .PCE, .BPWrongE, .BPWrongM,
// Mem
.CommittedF, .UnalignedPCNextF, .InvalidateICacheM, .CSRWriteFenceM,
.CommittedF, .EPCM, .TrapVectorM, .RetM, .TrapM, .InvalidateICacheM, .CSRWriteFenceM,
.InstrD, .InstrM, .InstrOrigM, .PCM, .InstrClassM, .BPDirPredWrongM,
.BTAWrongM, .RASPredPCWrongM, .IClassWrongM,
// Faults out
@ -281,8 +280,8 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
privileged #(P) priv(
.clk, .reset,
.FlushD, .FlushE, .FlushM, .FlushW, .StallD, .StallE, .StallM, .StallW,
.CSRReadM, .CSRWriteM, .SrcAM, .PCM, .PC2NextF,
.InstrM, .InstrOrigM, .CSRReadValW, .UnalignedPCNextF,
.CSRReadM, .CSRWriteM, .SrcAM, .PCM,
.InstrM, .InstrOrigM, .CSRReadValW, .EPCM, .TrapVectorM,
.RetM, .TrapM, .sfencevmaM, .InvalidateICacheM, .DCacheStallM, .ICacheStallF,
.InstrValidM, .CommittedM, .CommittedF,
.FRegWriteM, .LoadStallD, .StoreStallD,
@ -301,7 +300,8 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
.FRM_REGW, .ENVCFG_CBE, .ENVCFG_PBMTE, .ENVCFG_ADUE, .wfiM, .IntPendingM, .BigEndianM);
end else begin
assign CSRReadValW = 0;
assign UnalignedPCNextF = PC2NextF;
assign EPCM = 0;
assign TrapVectorM = 0;
assign RetM = 0;
assign TrapM = 0;
assign wfiM = 0;

64
testbench/testbench.sv
View File

@ -93,68 +93,72 @@ module testbench;
//tests = '{};
if (P.XLEN == 64) begin // RV64
case (TEST)
"arch64i": tests = arch64i;
"arch64priv": tests = arch64priv;
"arch64i": tests = arch64i;
"arch64priv": tests = arch64priv;
"arch64c": if (P.C_SUPPORTED)
if (P.ZICSR_SUPPORTED) tests = {arch64c, arch64cpriv};
else tests = {arch64c};
else tests = {arch64c};
"arch64m": if (P.M_SUPPORTED) tests = arch64m;
"arch64a": if (P.A_SUPPORTED) tests = arch64a;
"arch64f": if (P.F_SUPPORTED) tests = arch64f;
"arch64d": if (P.D_SUPPORTED) tests = arch64d;
"arch64f_fma": if (P.F_SUPPORTED) tests = arch64f_fma;
"arch64d_fma": if (P.D_SUPPORTED) tests = arch64d_fma;
"arch64zi": if (P.ZIFENCEI_SUPPORTED) tests = arch64zi;
"imperas64i": tests = imperas64i;
"arch64f_fma": if (P.F_SUPPORTED) tests = arch64f_fma;
"arch64d_fma": if (P.D_SUPPORTED) tests = arch64d_fma;
"arch64zifencei": if (P.ZIFENCEI_SUPPORTED) tests = arch64zifencei;
"imperas64i": tests = imperas64i;
"imperas64f": if (P.F_SUPPORTED) tests = imperas64f;
"imperas64d": if (P.D_SUPPORTED) tests = imperas64d;
"imperas64m": if (P.M_SUPPORTED) tests = imperas64m;
"wally64a": if (P.A_SUPPORTED) tests = wally64a;
"imperas64c": if (P.C_SUPPORTED) tests = imperas64c;
else tests = imperas64iNOc;
"custom": tests = custom;
"wally64i": tests = wally64i;
"wally64priv": tests = wally64priv;
"wally64periph": tests = wally64periph;
"coremark": tests = coremark;
"fpga": tests = fpga;
"ahb" : tests = ahb;
"coverage64gc" : tests = coverage64gc;
else tests = imperas64iNOc;
"custom": tests = custom;
"wally64i": tests = wally64i;
"wally64priv": tests = wally64priv;
"wally64periph": tests = wally64periph;
"coremark": tests = coremark;
"fpga": tests = fpga;
"ahb" : tests = ahb;
"coverage64gc" : tests = coverage64gc;
"arch64zba": if (P.ZBA_SUPPORTED) tests = arch64zba;
"arch64zbb": if (P.ZBB_SUPPORTED) tests = arch64zbb;
"arch64zbc": if (P.ZBC_SUPPORTED) tests = arch64zbc;
"arch64zbs": if (P.ZBS_SUPPORTED) tests = arch64zbs;
"arch64zicboz": if (P.ZICBOZ_SUPPORTED) tests = arch64zicboz;
"arch64zcb": if (P.ZCB_SUPPORTED) tests = arch64zcb;
endcase
end else begin // RV32
case (TEST)
"arch32i": tests = arch32i;
"arch32priv": tests = arch32priv;
"arch32e": tests = arch32e;
"arch32i": tests = arch32i;
"arch32priv": tests = arch32priv;
"arch32c": if (P.C_SUPPORTED)
if (P.ZICSR_SUPPORTED) tests = {arch32c, arch32cpriv};
else tests = {arch32c};
else tests = {arch32c};
"arch32m": if (P.M_SUPPORTED) tests = arch32m;
"arch32a": if (P.A_SUPPORTED) tests = arch32a;
"arch32f": if (P.F_SUPPORTED) tests = arch32f;
"arch32d": if (P.D_SUPPORTED) tests = arch32d;
"arch32f_fma": if (P.F_SUPPORTED) tests = arch32f_fma;
"arch32d_fma": if (P.D_SUPPORTED) tests = arch32d_fma;
"arch32zi": if (P.ZIFENCEI_SUPPORTED) tests = arch32zi;
"imperas32i": tests = imperas32i;
"arch32f_fma": if (P.F_SUPPORTED) tests = arch32f_fma;
"arch32d_fma": if (P.D_SUPPORTED) tests = arch32d_fma;
"arch32zifencei": if (P.ZIFENCEI_SUPPORTED) tests = arch32zifencei;
"imperas32i": tests = imperas32i;
"imperas32f": if (P.F_SUPPORTED) tests = imperas32f;
"imperas32m": if (P.M_SUPPORTED) tests = imperas32m;
"wally32a": if (P.A_SUPPORTED) tests = wally32a;
"imperas32c": if (P.C_SUPPORTED) tests = imperas32c;
else tests = imperas32iNOc;
"wally32i": tests = wally32i;
"wally32e": tests = wally32e;
"wally32priv": tests = wally32priv;
"wally32periph": tests = wally32periph;
"embench": tests = embench;
"coremark": tests = coremark;
else tests = imperas32iNOc;
"wally32i": tests = wally32i;
"wally32priv": tests = wally32priv;
"wally32periph": tests = wally32periph;
"embench": tests = embench;
"coremark": tests = coremark;
"arch32zba": if (P.ZBA_SUPPORTED) tests = arch32zba;
"arch32zbb": if (P.ZBB_SUPPORTED) tests = arch32zbb;
"arch32zbc": if (P.ZBC_SUPPORTED) tests = arch32zbc;
"arch32zbs": if (P.ZBS_SUPPORTED) tests = arch32zbs;
"arch32zicboz": if (P.ZICBOZ_SUPPORTED) tests = arch32zicboz;
"arch32zcb": if (P.ZCB_SUPPORTED) tests = arch32zcb;
endcase
end
if (tests.size() == 0) begin

132
testbench/tests.vh
View File

@ -44,9 +44,9 @@ string tvpaths[] = '{
string coverage64gc[] = '{
`COVERAGE,
"tlbNAPOT",
"priv",
"ieu",
// "tlbNAPOT",
"priv",
"ebu",
"csrwrites",
"ifu",
@ -898,7 +898,7 @@ string imperas32f[] = '{
-----/\----- EXCLUDED -----/\----- */
};
string arch64zi[] = '{
string arch64zifencei[] = '{
`RISCVARCHTEST,
"rv64i_m/Zifencei/src/Fencei.S"
};
@ -917,7 +917,7 @@ string imperas32f[] = '{
};
string arch32zi[] = '{
string arch32zifencei[] = '{
`RISCVARCHTEST,
"rv32i_m/Zifencei/src/Fencei.S"
};
@ -1481,6 +1481,49 @@ string imperas32f[] = '{
"rv64i_m/D/src/fssub.d_b8-01.S"
};
string arch64zicboz[] = '{ // as of 12/17/23 presently cbo.zero is the only CMO insturction with riscv-arch-test support
`RISCVARCHTEST,
"rv64i_m/CMO/src/cbo.zero-01.S"
};
string arch32zicboz[] = '{ // as of 12/17/23 presently cbo.zero is the only CMO insturction with riscv-arch-test support
`RISCVARCHTEST,
"rv32i_m/CMO/src/cbo.zero-01.S"
};
string arch64zcb[] = '{
`RISCVARCHTEST,
"rv64i_m/C/src/clbu-01.S",
"rv64i_m/C/src/clh-01.S",
"rv64i_m/C/src/clhu-01.S",
"rv64i_m/C/src/clbu-01.S",
"rv64i_m/C/src/csb-01.S",
"rv64i_m/C/src/csh-01.S",
"rv64i_m/C/src/csext.b-01.S",
"rv64i_m/C/src/csext.h-01.S",
"rv64i_m/C/src/czext.b-01.S",
"rv64i_m/C/src/czext.h-01.S",
"rv64i_m/C/src/cmul-01.S",
"rv64i_m/C/src/cnot-01.S",
"rv64i_m/C/src/czext.w-01.S"
};
string arch32zcb[] = '{
`RISCVARCHTEST,
"rv32i_m/C/src/clbu-01.S",
"rv32i_m/C/src/clh-01.S",
"rv32i_m/C/src/clhu-01.S",
"rv32i_m/C/src/clbu-01.S",
"rv32i_m/C/src/csb-01.S",
"rv32i_m/C/src/csh-01.S",
"rv32i_m/C/src/csext.b-01.S",
"rv32i_m/C/src/csext.h-01.S",
"rv32i_m/C/src/czext.b-01.S",
"rv32i_m/C/src/czext.h-01.S",
"rv32i_m/C/src/cmul-01.S",
"rv32i_m/C/src/cnot-01.S"
};
string arch64zba[] = '{
`RISCVARCHTEST,
"rv64i_m/B/src/slli.uw-01.S",
@ -1961,6 +2004,46 @@ string arch64zbs[] = '{
"rv32i_m/I/src/xori-01.S"
};
string arch32e[] = '{
`RISCVARCHTEST,
"rv32e_m/E/src/add-01.S",
"rv32e_m/E/src/addi-01.S",
"rv32e_m/E/src/and-01.S",
"rv32e_m/E/src/andi-01.S",
"rv32e_m/E/src/auipc-01.S",
"rv32e_m/E/src/bge-01.S",
"rv32e_m/E/src/bgeu-01.S",
"rv32e_m/E/src/blt-01.S",
"rv32e_m/E/src/bltu-01.S",
"rv32e_m/E/src/bne-01.S",
"rv32e_m/E/src/jal-01.S",
"rv32e_m/E/src/jalr-01.S",
"rv32e_m/E/src/lb-align-01.S",
"rv32e_m/E/src/lbu-align-01.S",
"rv32e_m/E/src/lh-align-01.S",
"rv32e_m/E/src/lhu-align-01.S",
"rv32e_m/E/src/lui-01.S",
"rv32e_m/E/src/lw-align-01.S",
"rv32e_m/E/src/or-01.S",
"rv32e_m/E/src/ori-01.S",
"rv32e_m/E/src/sb-align-01.S",
"rv32e_m/E/src/sh-align-01.S",
"rv32e_m/E/src/sll-01.S",
"rv32e_m/E/src/slli-01.S",
"rv32e_m/E/src/slt-01.S",
"rv32e_m/E/src/slti-01.S",
"rv32e_m/E/src/sltiu-01.S",
"rv32e_m/E/src/sltu-01.S",
"rv32e_m/E/src/sra-01.S",
"rv32e_m/E/src/srai-01.S",
"rv32e_m/E/src/srl-01.S",
"rv32e_m/E/src/srli-01.S",
"rv32e_m/E/src/sub-01.S",
"rv32e_m/E/src/sw-align-01.S",
"rv32e_m/E/src/xor-01.S",
"rv32e_m/E/src/xori-01.S"
};
string wally64i[] = '{
`WALLYTEST,
"rv64i_m/I/src/WALLY-ADD.S",
@ -2017,46 +2100,6 @@ string arch64zbs[] = '{
"rv64i_m/privilege/src/WALLY-spi-01.S"
};
string wally32e[] = '{
`WALLYTEST,
"rv32i_m/I/src/E-add-01.S",
"rv32i_m/I/src/E-addi-01.S",
"rv32i_m/I/src/E-and-01.S",
"rv32i_m/I/src/E-andi-01.S",
"rv32i_m/I/src/E-auipc-01.S",
"rv32i_m/I/src/E-bge-01.S",
"rv32i_m/I/src/E-bgeu-01.S",
"rv32i_m/I/src/E-blt-01.S",
"rv32i_m/I/src/E-bltu-01.S",
"rv32i_m/I/src/E-bne-01.S",
"rv32i_m/I/src/E-jal-01.S",
"rv32i_m/I/src/E-jalr-01.S",
"rv32i_m/I/src/E-lb-align-01.S",
"rv32i_m/I/src/E-lbu-align-01.S",
"rv32i_m/I/src/E-lh-align-01.S",
"rv32i_m/I/src/E-lhu-align-01.S",
"rv32i_m/I/src/E-lui-01.S",
"rv32i_m/I/src/E-lw-align-01.S",
"rv32i_m/I/src/E-or-01.S",
"rv32i_m/I/src/E-ori-01.S",
"rv32i_m/I/src/E-sb-align-01.S",
"rv32i_m/I/src/E-sh-align-01.S",
"rv32i_m/I/src/E-sll-01.S",
"rv32i_m/I/src/E-slli-01.S",
"rv32i_m/I/src/E-slt-01.S",
"rv32i_m/I/src/E-slti-01.S",
"rv32i_m/I/src/E-sltiu-01.S",
"rv32i_m/I/src/E-sltu-01.S",
"rv32i_m/I/src/E-sra-01.S",
"rv32i_m/I/src/E-srai-01.S",
"rv32i_m/I/src/E-srl-01.S",
"rv32i_m/I/src/E-srli-01.S",
"rv32i_m/I/src/E-sub-01.S",
"rv32i_m/I/src/E-sw-align-01.S",
"rv32i_m/I/src/E-xor-01.S",
"rv32i_m/I/src/E-xori-01.S"
};
string wally32i[] = '{
`WALLYTEST,
"rv32i_m/I/src/WALLY-ADD.S",
@ -2102,7 +2145,6 @@ string arch64zbs[] = '{
"rv32i_m/privilege/src/WALLY-plic-01.S",
"rv32i_m/privilege/src/WALLY-plic-s-01.S",
"rv32i_m/privilege/src/WALLY-spi-01.S"
};
string wally32periph[] = '{

15
tests/riscof/Makefile
View File

@ -8,7 +8,7 @@ wally_workdir = $(work)/wally-riscv-arch-test
current_dir = $(shell pwd)
#XLEN ?= 64
all: root arch32 wally32 wally32e arch64 wally64
all: root arch32 wally32 arch32e arch64 wally64
wally-riscv-arch-test: root wally32 wally64
root:
@ -20,10 +20,15 @@ root:
sed 's,{0},$(current_dir),g;s,{1},64gc,g' config.ini > config64.ini
sed 's,{0},$(current_dir),g;s,{1},32e,g' config.ini > config32e.ini
arch32e:
riscof run --work-dir=$(work_dir) --config=config32e.ini --suite=$(arch_dir)/riscv-test-suite/ --env=$(arch_dir)/riscv-test-suite/env --no-browser
rsync -a $(work_dir)/rv32e_m/ $(arch_workdir)/rv32e_m/ || echo "error suppressed"
arch32:
riscof run --work-dir=$(work_dir) --config=config32.ini --suite=$(arch_dir)/riscv-test-suite/ --env=$(arch_dir)/riscv-test-suite/env --no-browser
rsync -a $(work_dir)/rv32i_m/ $(arch_workdir)/rv32i_m/ || echo "error suppressed"
arch64:
riscof run --work-dir=$(work_dir) --config=config64.ini --suite=$(arch_dir)/riscv-test-suite/ --env=$(arch_dir)/riscv-test-suite/env --no-browser
rsync -a $(work_dir)/rv64i_m/ $(arch_workdir)/rv64i_m/ || echo "error suppressed"
@ -38,10 +43,10 @@ wally64:
riscof run --work-dir=$(work_dir) --config=config64.ini --suite=$(wally_dir)/riscv-test-suite/ --env=$(wally_dir)/riscv-test-suite/env --no-browser --no-dut-run
rsync -a $(work_dir)/rv64i_m/ $(wally_workdir)/rv64i_m/ || echo "error suppressed"
wally32e:
riscof run --work-dir=$(work_dir) --config=config32e.ini --suite=$(wally_dir)/riscv-test-suite/ --env=$(wally_dir)/riscv-test-suite/env --no-browser --no-dut-run
rsync -a $(work_dir)/rv32i_m/ $(wally_workdir)/rv32i_m/ || echo "error suppressed"
rsync -a $(work_dir)/rv32e_unratified/ $(wally_workdir)/rv32e_unratified/ || echo "error suppressed"
#wally32e:
# riscof run --work-dir=$(work_dir) --config=config32e.ini --suite=$(wally_dir)/riscv-test-suite/ --env=$(wally_dir)/riscv-test-suite/env --no-browser --no-dut-run
# rsync -a $(work_dir)/rv32i_m/ $(wally_workdir)/rv32i_m/ || echo "error suppressed"
# rsync -a $(work_dir)/rv32e_unratified/ $(wally_workdir)/rv32e_unratified/ || echo "error suppressed"
memfile:

2
tests/riscof/sail_cSim/riscof_sail_cSim.py
View File

@ -55,6 +55,8 @@ class sail_cSim(pluginTemplate):
self.compile_cmd = self.compile_cmd+' -mabi='+('lp64 ' if 64 in ispec['supported_xlen'] else ('ilp32e ' if "E" in ispec["ISA"] else 'ilp32 '))
if "I" in ispec["ISA"]:
self.isa += 'i'
if "E" in ispec["ISA"]:
self.isa += 'e'
if "M" in ispec["ISA"]:
self.isa += 'm'
if "A" in ispec["ISA"]:

10
tests/riscof/spike/riscof_spike.py
View File

@ -97,6 +97,8 @@ class spike(pluginTemplate):
self.isa = 'rv' + self.xlen
if "I" in ispec["ISA"]:
self.isa += 'i'
if "E" in ispec["ISA"]:
self.isa += 'e'
if "M" in ispec["ISA"]:
self.isa += 'm'
if "A" in ispec["ISA"]:
@ -107,6 +109,14 @@ class spike(pluginTemplate):
self.isa += 'd'
if "C" in ispec["ISA"]:
self.isa += 'c'
if "Zicsr" in ispec["ISA"]:
self.isa += '_Zicsr'
if "Zicboz" in ispec["ISA"]:
self.isa += '_Zicboz'
if "Zca" in ispec["ISA"]:
self.isa += '_Zca'
if "Zcb" in ispec["ISA"]:
self.isa += '_Zcb'
if "Zba" in ispec["ISA"]:
self.isa += '_Zba'
if "Zbb" in ispec["ISA"]:

3
tests/riscof/spike/spike_rv32gc_isa.yaml
View File

@ -1,6 +1,7 @@
hart_ids: [0]
hart0:
ISA: RV32IMAFDCZicsr_Zicboz_Zifencei_Zba_Zbb_Zbc_Zbs
ISA: RV32IMAFDCZicsr_Zifencei_Zba_Zbb_Zbc_Zbs
# ISA: RV32IMAFDCZicsr_Zicboz_Zifencei_Zca_Zba_Zbb_Zbc_Zbs # _Zbkb_Zcb
physical_addr_sz: 32
User_Spec_Version: '2.3'
supported_xlen: [32]

3
tests/riscof/spike/spike_rv64gc_isa.yaml
View File

@ -1,6 +1,7 @@
hart_ids: [0]
hart0:
ISA: RV64IMAFDCSUZicsr_Zicboz_Zifencei_Zba_Zbb_Zbc_Zbs
# ISA: RV64IMAFDCSUZicsr_Zicboz_Zifencei_Zca_Zba_Zbb_Zbc_Zbs # Zkbs_Zcb
ISA: RV64IMAFDCSUZicsr_Zifencei_Zbb_Zbc_Zbs # Zkbs_Zcb
physical_addr_sz: 56
User_Spec_Version: '2.3'
supported_xlen: [64]

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/Makefile
View File

@ -1,3 +0,0 @@
include ../../Makefile.include
$(eval $(call compile_template,-march=rv32ec -mabi=ilp32e -DXLEN=$(XLEN)))

61
tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/Makefrag
View File

@ -1,61 +0,0 @@
# RISC-V Architecture Test RV32E Makefrag
#
# Copyright (c) 2017, Codasip Ltd.
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
# * Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# * Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# * Neither the name of the Codasip Ltd. nor the
# names of its contributors may be used to endorse or promote products
# derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd. BE LIABLE FOR ANY
# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Description: Makefrag for RV32E architectural tests
rv32e_sc_tests = \
cadd-01 \
caddi-01 \
caddi16sp-01 \
caddi4spn-01 \
cand-01 \
candi-01 \
cbeqz-01 \
cbnez-01 \
cj-01 \
cjal-01 \
cjalr-01 \
cjr-01 \
cli-01 \
clui-01 \
clw-01 \
clwsp-01 \
cmv-01 \
cnop-01 \
cor-01 \
cslli-01 \
csrai-01 \
csrli-01 \
csub-01 \
csw-01 \
cswsp-01 \
cxor-01
rv32e_tests = $(addsuffix .elf, $(rv32e_sc_tests))
target_tests += $(rv32e_tests)

2980
tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/cadd-01.S
View File

File diff suppressed because it is too large Load Diff

1950
tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/caddi-01.S
View File

File diff suppressed because it is too large Load Diff

430
tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/caddi16sp-01.S
View File

@ -1,430 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version : 0.5.1
// timestamp : Wed Aug 4 06:39:00 2021 GMT
// usage : riscv_ctg \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32ec.cgf \
// --base-isa rv32e \
// --randomize
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the c.addi16sp instruction of the RISC-V C extension for the caddi16sp covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32EC")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",caddi16sp)
RVTEST_SIGBASE( x1,signature_x1_1)
inst_0:
// rd==x2, imm_val == -512, rs1_val == 4194304, rs1_val != imm_val, rs1_val > 0 and imm_val < 0
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x400000; immval:-0x200
TEST_CI_OP( c.addi16sp, x2, 0x3ffe00, 0x400000, -0x200, x1, 0, x3)
inst_1:
// rs1_val == 2147483647, imm_val == 128, rs1_val > 0 and imm_val > 0, rs1_val == (2**(xlen-1)-1)
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x7fffffff; immval:0x80
TEST_CI_OP( c.addi16sp, x2, 0x8000007f, 0x7fffffff, 0x80, x1, 4, x3)
inst_2:
// rs1_val == -1073741825, rs1_val < 0 and imm_val > 0
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x40000001; immval:0x60
TEST_CI_OP( c.addi16sp, x2, 0xc000005f, -0x40000001, 0x60, x1, 8, x3)
inst_3:
// rs1_val == -536870913, rs1_val < 0 and imm_val < 0
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x20000001; immval:-0x60
TEST_CI_OP( c.addi16sp, x2, 0xdfffff9f, -0x20000001, -0x60, x1, 12, x3)
inst_4:
// rs1_val == -268435457, imm_val == -352
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x10000001; immval:-0x160
TEST_CI_OP( c.addi16sp, x2, 0xeffffe9f, -0x10000001, -0x160, x1, 16, x3)
inst_5:
// rs1_val == -134217729, imm_val == -80
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x8000001; immval:-0x50
TEST_CI_OP( c.addi16sp, x2, 0xf7ffffaf, -0x8000001, -0x50, x1, 20, x3)
inst_6:
// rs1_val == -67108865, imm_val == -144
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x4000001; immval:-0x90
TEST_CI_OP( c.addi16sp, x2, 0xfbffff6f, -0x4000001, -0x90, x1, 24, x3)
inst_7:
// rs1_val == -33554433,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x2000001; immval:0xf0
TEST_CI_OP( c.addi16sp, x2, 0xfe0000ef, -0x2000001, 0xf0, x1, 28, x3)
inst_8:
// rs1_val == -16777217,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x1000001; immval:-0x80
TEST_CI_OP( c.addi16sp, x2, 0xfeffff7f, -0x1000001, -0x80, x1, 32, x3)
inst_9:
// rs1_val == -8388609,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x800001; immval:-0x70
TEST_CI_OP( c.addi16sp, x2, 0xff7fff8f, -0x800001, -0x70, x1, 36, x3)
inst_10:
// rs1_val == -4194305, imm_val == 64
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x400001; immval:0x40
TEST_CI_OP( c.addi16sp, x2, 0xffc0003f, -0x400001, 0x40, x1, 40, x3)
inst_11:
// rs1_val == -2097153,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x200001; immval:-0x160
TEST_CI_OP( c.addi16sp, x2, 0xffdffe9f, -0x200001, -0x160, x1, 44, x3)
inst_12:
// rs1_val == -1048577, imm_val == 16
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x100001; immval:0x10
TEST_CI_OP( c.addi16sp, x2, 0xfff0000f, -0x100001, 0x10, x1, 48, x3)
inst_13:
// rs1_val == -524289,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x80001; immval:0x10
TEST_CI_OP( c.addi16sp, x2, 0xfff8000f, -0x80001, 0x10, x1, 52, x3)
inst_14:
// rs1_val == -262145,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x40001; immval:-0x100
TEST_CI_OP( c.addi16sp, x2, 0xfffbfeff, -0x40001, -0x100, x1, 56, x3)
inst_15:
// rs1_val == -131073, imm_val == 336
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x20001; immval:0x150
TEST_CI_OP( c.addi16sp, x2, 0xfffe014f, -0x20001, 0x150, x1, 60, x3)
inst_16:
// rs1_val == -65537,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x10001; immval:-0x50
TEST_CI_OP( c.addi16sp, x2, 0xfffeffaf, -0x10001, -0x50, x1, 64, x3)
inst_17:
// rs1_val == -32769,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x8001; immval:0x40
TEST_CI_OP( c.addi16sp, x2, 0xffff803f, -0x8001, 0x40, x1, 68, x3)
inst_18:
// rs1_val == -16385,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x4001; immval:0x50
TEST_CI_OP( c.addi16sp, x2, 0xffffc04f, -0x4001, 0x50, x1, 72, x3)
inst_19:
// rs1_val == -8193,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x2001; immval:-0x40
TEST_CI_OP( c.addi16sp, x2, 0xffffdfbf, -0x2001, -0x40, x1, 76, x3)
inst_20:
// rs1_val == -4097,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x1001; immval:0x80
TEST_CI_OP( c.addi16sp, x2, 0xfffff07f, -0x1001, 0x80, x1, 80, x3)
inst_21:
// rs1_val == -2049,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x801; immval:0x80
TEST_CI_OP( c.addi16sp, x2, 0xfffff87f, -0x801, 0x80, x1, 84, x3)
inst_22:
// rs1_val == -1025,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x401; immval:-0x10
TEST_CI_OP( c.addi16sp, x2, 0xfffffbef, -0x401, -0x10, x1, 88, x3)
inst_23:
// rs1_val == -513,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x201; immval:0x150
TEST_CI_OP( c.addi16sp, x2, 0xffffff4f, -0x201, 0x150, x1, 92, x3)
inst_24:
// rs1_val == -257, imm_val == -32
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x101; immval:-0x20
TEST_CI_OP( c.addi16sp, x2, 0xfffffedf, -0x101, -0x20, x1, 96, x3)
inst_25:
// rs1_val == -129,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x81; immval:-0x20
TEST_CI_OP( c.addi16sp, x2, 0xffffff5f, -0x81, -0x20, x1, 100, x3)
inst_26:
// rs1_val == -65,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x41; immval:0x90
TEST_CI_OP( c.addi16sp, x2, 0x4f, -0x41, 0x90, x1, 104, x3)
inst_27:
// rs1_val == -33,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x21; immval:0x10
TEST_CI_OP( c.addi16sp, x2, 0xffffffef, -0x21, 0x10, x1, 108, x3)
inst_28:
// rs1_val == -17,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x11; immval:-0x160
TEST_CI_OP( c.addi16sp, x2, 0xfffffe8f, -0x11, -0x160, x1, 112, x3)
inst_29:
// rs1_val == -9,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x9; immval:-0x60
TEST_CI_OP( c.addi16sp, x2, 0xffffff97, -0x9, -0x60, x1, 116, x3)
inst_30:
// rs1_val == -5,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x5; immval:-0x100
TEST_CI_OP( c.addi16sp, x2, 0xfffffefb, -0x5, -0x100, x1, 120, x3)
inst_31:
// rs1_val == -3,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x3; immval:-0x90
TEST_CI_OP( c.addi16sp, x2, 0xffffff6d, -0x3, -0x90, x1, 124, x3)
inst_32:
// rs1_val == -2,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x2; immval:0x70
TEST_CI_OP( c.addi16sp, x2, 0x6e, -0x2, 0x70, x1, 128, x3)
inst_33:
// imm_val == 496,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x400000; immval:0x1f0
TEST_CI_OP( c.addi16sp, x2, 0x4001f0, 0x400000, 0x1f0, x1, 132, x3)
inst_34:
// imm_val == -272,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x5; immval:-0x110
TEST_CI_OP( c.addi16sp, x2, 0xfffffeeb, -0x5, -0x110, x1, 136, x3)
inst_35:
// imm_val == -48,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x400001; immval:-0x30
TEST_CI_OP( c.addi16sp, x2, 0xffbfffcf, -0x400001, -0x30, x1, 140, x3)
inst_36:
// rs1_val == -2147483648, rs1_val == (-2**(xlen-1))
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x80000000; immval:-0xa0
TEST_CI_OP( c.addi16sp, x2, 0x7fffff60, -0x80000000, -0xa0, x1, 144, x3)
inst_37:
// rs1_val == 1073741824, imm_val == 256
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x40000000; immval:0x100
TEST_CI_OP( c.addi16sp, x2, 0x40000100, 0x40000000, 0x100, x1, 148, x3)
inst_38:
// rs1_val == 536870912,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x20000000; immval:-0x10
TEST_CI_OP( c.addi16sp, x2, 0x1ffffff0, 0x20000000, -0x10, x1, 152, x3)
inst_39:
// rs1_val == 268435456,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x10000000; immval:0x30
TEST_CI_OP( c.addi16sp, x2, 0x10000030, 0x10000000, 0x30, x1, 156, x3)
inst_40:
// rs1_val == 134217728,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x8000000; immval:-0xa0
TEST_CI_OP( c.addi16sp, x2, 0x7ffff60, 0x8000000, -0xa0, x1, 160, x3)
inst_41:
// rs1_val == 64,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x40; immval:0x80
TEST_CI_OP( c.addi16sp, x2, 0xc0, 0x40, 0x80, x1, 164, x3)
inst_42:
// rs1_val == 32,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x20; immval:0x1f0
TEST_CI_OP( c.addi16sp, x2, 0x210, 0x20, 0x1f0, x1, 168, x3)
inst_43:
// rs1_val == 16,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x10; immval:0x1f0
TEST_CI_OP( c.addi16sp, x2, 0x200, 0x10, 0x1f0, x1, 172, x3)
inst_44:
// rs1_val == 8,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x8; immval:0x70
TEST_CI_OP( c.addi16sp, x2, 0x78, 0x8, 0x70, x1, 176, x3)
inst_45:
// rs1_val == 4,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x4; immval:-0x110
TEST_CI_OP( c.addi16sp, x2, 0xfffffef4, 0x4, -0x110, x1, 180, x3)
inst_46:
// rs1_val == 2,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x2; immval:-0x50
TEST_CI_OP( c.addi16sp, x2, 0xffffffb2, 0x2, -0x50, x1, 184, x3)
inst_47:
// rs1_val == 1,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x1; immval:0x50
TEST_CI_OP( c.addi16sp, x2, 0x51, 0x1, 0x50, x1, 188, x3)
inst_48:
// imm_val == 32,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x9; immval:0x20
TEST_CI_OP( c.addi16sp, x2, 0x29, 0x9, 0x20, x1, 192, x3)
inst_49:
// rs1_val == -1431655766,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x55555556; immval:0x30
TEST_CI_OP( c.addi16sp, x2, 0xaaaaaada, -0x55555556, 0x30, x1, 196, x3)
inst_50:
// rs1_val == 1431655765,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x55555555; immval:0x60
TEST_CI_OP( c.addi16sp, x2, 0x555555b5, 0x55555555, 0x60, x1, 200, x3)
inst_51:
// rs1_val == 0,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x0; immval:-0x100
TEST_CI_OP( c.addi16sp, x2, 0xffffff00, 0x0, -0x100, x1, 204, x3)
inst_52:
// rs1_val == imm_val,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x40; immval:0x40
TEST_CI_OP( c.addi16sp, x2, 0x80, 0x40, 0x40, x1, 208, x3)
inst_53:
// rs1_val == 67108864,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x4000000; immval:-0x200
TEST_CI_OP( c.addi16sp, x2, 0x3fffe00, 0x4000000, -0x200, x1, 212, x3)
inst_54:
// rs1_val == 33554432,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x2000000; immval:-0x200
TEST_CI_OP( c.addi16sp, x2, 0x1fffe00, 0x2000000, -0x200, x1, 216, x3)
inst_55:
// rs1_val == 16777216,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x1000000; immval:-0x40
TEST_CI_OP( c.addi16sp, x2, 0xffffc0, 0x1000000, -0x40, x1, 220, x3)
inst_56:
// rs1_val == 8388608,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x800000; immval:0x10
TEST_CI_OP( c.addi16sp, x2, 0x800010, 0x800000, 0x10, x1, 224, x3)
inst_57:
// rs1_val == 2097152,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x200000; immval:0x20
TEST_CI_OP( c.addi16sp, x2, 0x200020, 0x200000, 0x20, x1, 228, x3)
inst_58:
// rs1_val == 1048576,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x100000; immval:0x90
TEST_CI_OP( c.addi16sp, x2, 0x100090, 0x100000, 0x90, x1, 232, x3)
inst_59:
// rs1_val == 524288,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x80000; immval:0x50
TEST_CI_OP( c.addi16sp, x2, 0x80050, 0x80000, 0x50, x1, 236, x3)
inst_60:
// rs1_val == 262144,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x40000; immval:-0x160
TEST_CI_OP( c.addi16sp, x2, 0x3fea0, 0x40000, -0x160, x1, 240, x3)
inst_61:
// rs1_val == 131072,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x20000; immval:-0xa0
TEST_CI_OP( c.addi16sp, x2, 0x1ff60, 0x20000, -0xa0, x1, 244, x3)
inst_62:
// rs1_val == 65536,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x10000; immval:0x150
TEST_CI_OP( c.addi16sp, x2, 0x10150, 0x10000, 0x150, x1, 248, x3)
inst_63:
// rs1_val == 32768,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x8000; immval:0x1f0
TEST_CI_OP( c.addi16sp, x2, 0x81f0, 0x8000, 0x1f0, x1, 252, x3)
inst_64:
// rs1_val == 16384,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x4000; immval:0x40
TEST_CI_OP( c.addi16sp, x2, 0x4040, 0x4000, 0x40, x1, 256, x3)
inst_65:
// rs1_val == 8192,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x2000; immval:0x80
TEST_CI_OP( c.addi16sp, x2, 0x2080, 0x2000, 0x80, x1, 260, x3)
inst_66:
// rs1_val == 4096,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x1000; immval:0x1f0
TEST_CI_OP( c.addi16sp, x2, 0x11f0, 0x1000, 0x1f0, x1, 264, x3)
inst_67:
// rs1_val == 2048,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x800; immval:0x100
TEST_CI_OP( c.addi16sp, x2, 0x900, 0x800, 0x100, x1, 268, x3)
inst_68:
// rs1_val == 1024,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x400; immval:0x1f0
TEST_CI_OP( c.addi16sp, x2, 0x5f0, 0x400, 0x1f0, x1, 272, x3)
inst_69:
// rs1_val == 512,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x200; immval:0x150
TEST_CI_OP( c.addi16sp, x2, 0x350, 0x200, 0x150, x1, 276, x3)
inst_70:
// rs1_val == 256,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x100; immval:0x1f0
TEST_CI_OP( c.addi16sp, x2, 0x2f0, 0x100, 0x1f0, x1, 280, x3)
inst_71:
// rs1_val == 128,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x80; immval:0x30
TEST_CI_OP( c.addi16sp, x2, 0xb0, 0x80, 0x30, x1, 284, x3)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
signature_x1_0:
.fill 0*(XLEN/32),4,0xdeadbeef
signature_x1_1:
.fill 72*(XLEN/32),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
RVMODEL_DATA_END

165
tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/caddi4spn-01.S
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@ -1,165 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version : 0.5.1
// timestamp : Wed Aug 4 06:39:00 2021 GMT
// usage : riscv_ctg \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32ec.cgf \
// --base-isa rv32e \
// --randomize
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the c.addi4spn instruction of the RISC-V C extension for the caddi4spn covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32EC")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",caddi4spn)
RVTEST_SIGBASE( x1,signature_x1_1)
inst_0:
// rd==x10, imm_val == 1020, imm_val > 0
// opcode:c.addi4spn; dest:x10; immval:0x3fc
TEST_CADDI4SPN_OP( c.addi4spn, x10, 0x3fc, 0x3fc, x1, 0, x2)
inst_1:
// rd==x13, imm_val == 508,
// opcode:c.addi4spn; dest:x13; immval:0x1fc
TEST_CADDI4SPN_OP( c.addi4spn, x13, 0x1fc, 0x1fc, x1, 4, x2)
inst_2:
// rd==x9, imm_val == 764,
// opcode:c.addi4spn; dest:x9; immval:0x2fc
TEST_CADDI4SPN_OP( c.addi4spn, x9, 0x2fc, 0x2fc, x1, 8, x2)
inst_3:
// rd==x8, imm_val == 892,
// opcode:c.addi4spn; dest:x8; immval:0x37c
TEST_CADDI4SPN_OP( c.addi4spn, x8, 0x37c, 0x37c, x1, 12, x2)
inst_4:
// rd==x14, imm_val == 956,
// opcode:c.addi4spn; dest:x14; immval:0x3bc
TEST_CADDI4SPN_OP( c.addi4spn, x14, 0x3bc, 0x3bc, x1, 16, x2)
inst_5:
// rd==x11, imm_val == 988,
// opcode:c.addi4spn; dest:x11; immval:0x3dc
TEST_CADDI4SPN_OP( c.addi4spn, x11, 0x3dc, 0x3dc, x1, 20, x2)
inst_6:
// rd==x15, imm_val == 1004,
// opcode:c.addi4spn; dest:x15; immval:0x3ec
TEST_CADDI4SPN_OP( c.addi4spn, x15, 0x3ec, 0x3ec, x1, 24, x2)
inst_7:
// rd==x12, imm_val == 1012,
// opcode:c.addi4spn; dest:x12; immval:0x3f4
TEST_CADDI4SPN_OP( c.addi4spn, x12, 0x3f4, 0x3f4, x1, 28, x2)
inst_8:
// imm_val == 1016,
// opcode:c.addi4spn; dest:x10; immval:0x3f8
TEST_CADDI4SPN_OP( c.addi4spn, x10, 0x3f8, 0x3f8, x1, 32, x2)
inst_9:
// imm_val == 512,
// opcode:c.addi4spn; dest:x10; immval:0x200
TEST_CADDI4SPN_OP( c.addi4spn, x10, 0x200, 0x200, x1, 36, x2)
inst_10:
// imm_val == 256,
// opcode:c.addi4spn; dest:x10; immval:0x100
TEST_CADDI4SPN_OP( c.addi4spn, x10, 0x100, 0x100, x1, 40, x2)
inst_11:
// imm_val == 128,
// opcode:c.addi4spn; dest:x10; immval:0x80
TEST_CADDI4SPN_OP( c.addi4spn, x10, 0x80, 0x80, x1, 44, x2)
inst_12:
// imm_val == 4,
// opcode:c.addi4spn; dest:x10; immval:0x4
TEST_CADDI4SPN_OP( c.addi4spn, x10, 0x4, 0x4, x1, 48, x2)
inst_13:
// imm_val == 680,
// opcode:c.addi4spn; dest:x10; immval:0x2a8
TEST_CADDI4SPN_OP( c.addi4spn, x10, 0x2a8, 0x2a8, x1, 52, x2)
inst_14:
// imm_val == 340,
// opcode:c.addi4spn; dest:x10; immval:0x154
TEST_CADDI4SPN_OP( c.addi4spn, x10, 0x154, 0x154, x1, 56, x2)
inst_15:
// imm_val == 64,
// opcode:c.addi4spn; dest:x10; immval:0x40
TEST_CADDI4SPN_OP( c.addi4spn, x10, 0x40, 0x40, x1, 60, x2)
inst_16:
// imm_val == 32,
// opcode:c.addi4spn; dest:x10; immval:0x20
TEST_CADDI4SPN_OP( c.addi4spn, x10, 0x20, 0x20, x1, 64, x2)
inst_17:
// imm_val == 16,
// opcode:c.addi4spn; dest:x10; immval:0x10
TEST_CADDI4SPN_OP( c.addi4spn, x10, 0x10, 0x10, x1, 68, x2)
inst_18:
// imm_val == 8,
// opcode:c.addi4spn; dest:x10; immval:0x8
TEST_CADDI4SPN_OP( c.addi4spn, x10, 0x8, 0x8, x1, 72, x2)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
signature_x1_0:
.fill 0*(XLEN/32),4,0xdeadbeef
signature_x1_1:
.fill 19*(XLEN/32),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
RVMODEL_DATA_END

3005
tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/cand-01.S
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1940
tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/candi-01.S
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490
tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/cbeqz-01.S
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@ -1,490 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version : 0.5.1
// timestamp : Wed Aug 4 06:39:00 2021 GMT
// usage : riscv_ctg \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32ec.cgf \
// --base-isa rv32e \
// --randomize
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the c.beqz instruction of the RISC-V C extension for the cbeqz covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32EC")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",cbeqz)
RVTEST_SIGBASE( x1,signature_x1_1)
inst_0:
// rs1==x10, rs1_val < 0 and imm_val < 0, rs1_val == -4097
// opcode:c.beqz; op1:x10; op1val:-0x1001; immval:0xac
TEST_CBRANCH_OP(c.beqz, x2, x10, -0x1001, 0xac, 1b, x1, 0)
inst_1:
// rs1==x14, rs1_val == 2147483647, rs1_val == (2**(xlen-1)-1), rs1_val > 0 and imm_val < 0
// opcode:c.beqz; op1:x14; op1val:0x7fffffff; immval:0x14
TEST_CBRANCH_OP(c.beqz, x2, x14, 0x7fffffff, 0x14, 1b, x1, 4)
inst_2:
// rs1==x8, rs1_val == -1073741825, rs1_val < 0 and imm_val > 0
// opcode:c.beqz; op1:x8; op1val:-0x40000001; immval:0x20
TEST_CBRANCH_OP(c.beqz, x2, x8, -0x40000001, 0x20, 3f, x1, 8)
inst_3:
// rs1==x15, rs1_val == -536870913,
// opcode:c.beqz; op1:x15; op1val:-0x20000001; immval:0xac
TEST_CBRANCH_OP(c.beqz, x2, x15, -0x20000001, 0xac, 1b, x1, 12)
inst_4:
// rs1==x12, rs1_val == -268435457,
// opcode:c.beqz; op1:x12; op1val:-0x10000001; immval:0x12
TEST_CBRANCH_OP(c.beqz, x2, x12, -0x10000001, 0x12, 3f, x1, 16)
inst_5:
// rs1==x13, rs1_val == -134217729,
// opcode:c.beqz; op1:x13; op1val:-0x8000001; immval:0x7e
TEST_CBRANCH_OP(c.beqz, x2, x13, -0x8000001, 0x7e, 3f, x1, 20)
inst_6:
// rs1==x11, rs1_val == -67108865,
// opcode:c.beqz; op1:x11; op1val:-0x4000001; immval:0xe
TEST_CBRANCH_OP(c.beqz, x2, x11, -0x4000001, 0xe, 1b, x1, 24)
inst_7:
// rs1==x9, rs1_val == -33554433,
// opcode:c.beqz; op1:x9; op1val:-0x2000001; immval:0xc
TEST_CBRANCH_OP(c.beqz, x2, x9, -0x2000001, 0xc, 1b, x1, 28)
inst_8:
// rs1_val == -16777217,
// opcode:c.beqz; op1:x10; op1val:-0x1000001; immval:0x20
TEST_CBRANCH_OP(c.beqz, x2, x10, -0x1000001, 0x20, 3f, x1, 32)
inst_9:
// rs1_val == -8388609,
// opcode:c.beqz; op1:x10; op1val:-0x800001; immval:0x80
TEST_CBRANCH_OP(c.beqz, x2, x10, -0x800001, 0x80, 1b, x1, 36)
inst_10:
// rs1_val == -4194305,
// opcode:c.beqz; op1:x10; op1val:-0x400001; immval:0xe
TEST_CBRANCH_OP(c.beqz, x2, x10, -0x400001, 0xe, 1b, x1, 40)
inst_11:
// rs1_val == -2097153,
// opcode:c.beqz; op1:x10; op1val:-0x200001; immval:0x40
TEST_CBRANCH_OP(c.beqz, x2, x10, -0x200001, 0x40, 3f, x1, 44)
inst_12:
// rs1_val == -1048577,
// opcode:c.beqz; op1:x10; op1val:-0x100001; immval:0x22
TEST_CBRANCH_OP(c.beqz, x2, x10, -0x100001, 0x22, 1b, x1, 48)
inst_13:
// rs1_val == -524289,
// opcode:c.beqz; op1:x10; op1val:-0x80001; immval:0x82
TEST_CBRANCH_OP(c.beqz, x2, x10, -0x80001, 0x82, 1b, x1, 52)
inst_14:
// rs1_val == -262145,
// opcode:c.beqz; op1:x10; op1val:-0x40001; immval:0xc
TEST_CBRANCH_OP(c.beqz, x2, x10, -0x40001, 0xc, 3f, x1, 56)
inst_15:
// rs1_val == -131073,
// opcode:c.beqz; op1:x10; op1val:-0x20001; immval:0x6
TEST_CBRANCH_OP(c.beqz, x2, x10, -0x20001, 0x6, 3f, x1, 60)
inst_16:
// rs1_val == -65537,
// opcode:c.beqz; op1:x10; op1val:-0x10001; immval:0x12
TEST_CBRANCH_OP(c.beqz, x2, x10, -0x10001, 0x12, 3f, x1, 64)
inst_17:
// rs1_val == -32769,
// opcode:c.beqz; op1:x10; op1val:-0x8001; immval:0x42
TEST_CBRANCH_OP(c.beqz, x2, x10, -0x8001, 0x42, 1b, x1, 68)
inst_18:
// rs1_val == -16385,
// opcode:c.beqz; op1:x10; op1val:-0x4001; immval:0x80
TEST_CBRANCH_OP(c.beqz, x2, x10, -0x4001, 0x80, 3f, x1, 72)
inst_19:
// rs1_val == -8193,
// opcode:c.beqz; op1:x10; op1val:-0x2001; immval:0x7e
TEST_CBRANCH_OP(c.beqz, x2, x10, -0x2001, 0x7e, 3f, x1, 76)
inst_20:
// rs1_val == -2049,
// opcode:c.beqz; op1:x10; op1val:-0x801; immval:0xe
TEST_CBRANCH_OP(c.beqz, x2, x10, -0x801, 0xe, 1b, x1, 80)
inst_21:
// rs1_val == -1025,
// opcode:c.beqz; op1:x10; op1val:-0x401; immval:0x80
TEST_CBRANCH_OP(c.beqz, x2, x10, -0x401, 0x80, 1b, x1, 84)
inst_22:
// rs1_val == -513,
// opcode:c.beqz; op1:x10; op1val:-0x201; immval:0xc
TEST_CBRANCH_OP(c.beqz, x2, x10, -0x201, 0xc, 3f, x1, 88)
inst_23:
// rs1_val == -257,
// opcode:c.beqz; op1:x10; op1val:-0x101; immval:0xa
TEST_CBRANCH_OP(c.beqz, x2, x10, -0x101, 0xa, 1b, x1, 92)
inst_24:
// rs1_val == -129,
// opcode:c.beqz; op1:x10; op1val:-0x81; immval:0x14
TEST_CBRANCH_OP(c.beqz, x2, x10, -0x81, 0x14, 1b, x1, 96)
inst_25:
// rs1_val == -65,
// opcode:c.beqz; op1:x10; op1val:-0x41; immval:0xa
TEST_CBRANCH_OP(c.beqz, x2, x10, -0x41, 0xa, 1b, x1, 100)
inst_26:
// rs1_val == -33,
// opcode:c.beqz; op1:x10; op1val:-0x21; immval:0xac
TEST_CBRANCH_OP(c.beqz, x2, x10, -0x21, 0xac, 1b, x1, 104)
inst_27:
// rs1_val == -17,
// opcode:c.beqz; op1:x10; op1val:-0x11; immval:0x12
TEST_CBRANCH_OP(c.beqz, x2, x10, -0x11, 0x12, 1b, x1, 108)
inst_28:
// rs1_val == -9,
// opcode:c.beqz; op1:x10; op1val:-0x9; immval:0x20
TEST_CBRANCH_OP(c.beqz, x2, x10, -0x9, 0x20, 3f, x1, 112)
inst_29:
// rs1_val == -5,
// opcode:c.beqz; op1:x10; op1val:-0x5; immval:0x42
TEST_CBRANCH_OP(c.beqz, x2, x10, -0x5, 0x42, 1b, x1, 116)
inst_30:
// rs1_val == -3,
// opcode:c.beqz; op1:x10; op1val:-0x3; immval:0x42
TEST_CBRANCH_OP(c.beqz, x2, x10, -0x3, 0x42, 1b, x1, 120)
inst_31:
// rs1_val == -2,
// opcode:c.beqz; op1:x10; op1val:-0x2; immval:0xa
TEST_CBRANCH_OP(c.beqz, x2, x10, -0x2, 0xa, 3f, x1, 124)
inst_32:
// rs1_val == -2147483648, rs1_val == (-2**(xlen-1))
// opcode:c.beqz; op1:x10; op1val:-0x80000000; immval:0x6
TEST_CBRANCH_OP(c.beqz, x2, x10, -0x80000000, 0x6, 3f, x1, 128)
inst_33:
// rs1_val == 1073741824, rs1_val > 0 and imm_val > 0
// opcode:c.beqz; op1:x10; op1val:0x40000000; immval:0x7e
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x40000000, 0x7e, 3f, x1, 132)
inst_34:
// rs1_val == 536870912,
// opcode:c.beqz; op1:x10; op1val:0x20000000; immval:0x22
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x20000000, 0x22, 1b, x1, 136)
inst_35:
// rs1_val == 268435456,
// opcode:c.beqz; op1:x10; op1val:0x10000000; immval:0x40
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x10000000, 0x40, 3f, x1, 140)
inst_36:
// rs1_val == 134217728,
// opcode:c.beqz; op1:x10; op1val:0x8000000; immval:0x80
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x8000000, 0x80, 3f, x1, 144)
inst_37:
// rs1_val == 67108864,
// opcode:c.beqz; op1:x10; op1val:0x4000000; immval:0x80
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x4000000, 0x80, 3f, x1, 148)
inst_38:
// rs1_val == 33554432,
// opcode:c.beqz; op1:x10; op1val:0x2000000; immval:0x22
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x2000000, 0x22, 1b, x1, 152)
inst_39:
// rs1_val == 16777216,
// opcode:c.beqz; op1:x10; op1val:0x1000000; immval:0x40
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x1000000, 0x40, 3f, x1, 156)
inst_40:
// rs1_val == 8388608,
// opcode:c.beqz; op1:x10; op1val:0x800000; immval:0xe
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x800000, 0xe, 3f, x1, 160)
inst_41:
// rs1_val == 4194304,
// opcode:c.beqz; op1:x10; op1val:0x400000; immval:0x80
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x400000, 0x80, 3f, x1, 164)
inst_42:
// rs1_val == 2097152,
// opcode:c.beqz; op1:x10; op1val:0x200000; immval:0xe
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x200000, 0xe, 3f, x1, 168)
inst_43:
// rs1_val == 1048576,
// opcode:c.beqz; op1:x10; op1val:0x100000; immval:0x6
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x100000, 0x6, 1b, x1, 172)
inst_44:
// rs1_val == 524288,
// opcode:c.beqz; op1:x10; op1val:0x80000; immval:0x82
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x80000, 0x82, 1b, x1, 176)
inst_45:
// rs1_val == 262144,
// opcode:c.beqz; op1:x10; op1val:0x40000; immval:0x42
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x40000, 0x42, 1b, x1, 180)
inst_46:
// rs1_val == 131072,
// opcode:c.beqz; op1:x10; op1val:0x20000; immval:0xc
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x20000, 0xc, 1b, x1, 184)
inst_47:
// rs1_val == 65536,
// opcode:c.beqz; op1:x10; op1val:0x10000; immval:0x82
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x10000, 0x82, 1b, x1, 188)
inst_48:
// rs1_val == 32768,
// opcode:c.beqz; op1:x10; op1val:0x8000; immval:0x4
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x8000, 0x4, 1b, x1, 192)
inst_49:
// rs1_val == 16384,
// opcode:c.beqz; op1:x10; op1val:0x4000; immval:0xa
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x4000, 0xa, 1b, x1, 196)
inst_50:
// rs1_val == 8192,
// opcode:c.beqz; op1:x10; op1val:0x2000; immval:0x80
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x2000, 0x80, 1b, x1, 200)
inst_51:
// rs1_val == 4096,
// opcode:c.beqz; op1:x10; op1val:0x1000; immval:0x40
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x1000, 0x40, 3f, x1, 204)
inst_52:
// rs1_val == 2048,
// opcode:c.beqz; op1:x10; op1val:0x800; immval:0x20
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x800, 0x20, 3f, x1, 208)
inst_53:
// rs1_val == 1024,
// opcode:c.beqz; op1:x10; op1val:0x400; immval:0xc
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x400, 0xc, 3f, x1, 212)
inst_54:
// rs1_val == 512,
// opcode:c.beqz; op1:x10; op1val:0x200; immval:0x10
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x200, 0x10, 1b, x1, 216)
inst_55:
// rs1_val == 256,
// opcode:c.beqz; op1:x10; op1val:0x100; immval:0x7e
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x100, 0x7e, 3f, x1, 220)
inst_56:
// rs1_val == 128,
// opcode:c.beqz; op1:x10; op1val:0x80; immval:0x6
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x80, 0x6, 3f, x1, 224)
inst_57:
// rs1_val == 64,
// opcode:c.beqz; op1:x10; op1val:0x40; immval:0xa
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x40, 0xa, 3f, x1, 228)
inst_58:
// rs1_val == 32,
// opcode:c.beqz; op1:x10; op1val:0x20; immval:0x12
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x20, 0x12, 1b, x1, 232)
inst_59:
// rs1_val == 16,
// opcode:c.beqz; op1:x10; op1val:0x10; immval:0x4
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x10, 0x4, 1b, x1, 236)
inst_60:
// rs1_val == 1,
// opcode:c.beqz; op1:x10; op1val:0x1; immval:0xe
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x1, 0xe, 3f, x1, 240)
inst_61:
// rs1_val==46341,
// opcode:c.beqz; op1:x10; op1val:0xb505; immval:0x10
TEST_CBRANCH_OP(c.beqz, x2, x10, 0xb505, 0x10, 1b, x1, 244)
inst_62:
// rs1_val==-46339,
// opcode:c.beqz; op1:x10; op1val:-0xb503; immval:0x82
TEST_CBRANCH_OP(c.beqz, x2, x10, -0xb503, 0x82, 1b, x1, 248)
inst_63:
// rs1_val==1717986919,
// opcode:c.beqz; op1:x10; op1val:0x66666667; immval:0x8
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x66666667, 0x8, 3f, x1, 252)
inst_64:
// rs1_val==858993460,
// opcode:c.beqz; op1:x10; op1val:0x33333334; immval:0x8
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x33333334, 0x8, 3f, x1, 256)
inst_65:
// rs1_val==6,
// opcode:c.beqz; op1:x10; op1val:0x6; immval:0x6
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x6, 0x6, 1b, x1, 260)
inst_66:
// rs1_val==-1431655765,
// opcode:c.beqz; op1:x10; op1val:-0x55555555; immval:0x80
TEST_CBRANCH_OP(c.beqz, x2, x10, -0x55555555, 0x80, 3f, x1, 264)
inst_67:
// rs1_val==1431655766,
// opcode:c.beqz; op1:x10; op1val:0x55555556; immval:0x14
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x55555556, 0x14, 1b, x1, 268)
inst_68:
// rs1_val==4, rs1_val == 4
// opcode:c.beqz; op1:x10; op1val:0x4; immval:0x82
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x4, 0x82, 1b, x1, 272)
inst_69:
// rs1_val==46339,
// opcode:c.beqz; op1:x10; op1val:0xb503; immval:0x14
TEST_CBRANCH_OP(c.beqz, x2, x10, 0xb503, 0x14, 1b, x1, 276)
inst_70:
// rs1_val==0, rs1_val == 0, rs1_val == 0 and imm_val > 0
// opcode:c.beqz; op1:x10; op1val:0x0; immval:0xe
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x0, 0xe, 3f, x1, 280)
inst_71:
// rs1_val==1717986917,
// opcode:c.beqz; op1:x10; op1val:0x66666665; immval:0x80
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x66666665, 0x80, 3f, x1, 284)
inst_72:
// rs1_val==858993458,
// opcode:c.beqz; op1:x10; op1val:0x33333332; immval:0xa
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x33333332, 0xa, 1b, x1, 288)
inst_73:
// rs1_val==1431655764,
// opcode:c.beqz; op1:x10; op1val:0x55555554; immval:0xc
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x55555554, 0xc, 1b, x1, 292)
inst_74:
// rs1_val==2, rs1_val == 2
// opcode:c.beqz; op1:x10; op1val:0x2; immval:0xa
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x2, 0xa, 1b, x1, 296)
inst_75:
// rs1_val==46340,
// opcode:c.beqz; op1:x10; op1val:0xb504; immval:0x8
TEST_CBRANCH_OP(c.beqz, x2, x10, 0xb504, 0x8, 1b, x1, 300)
inst_76:
// rs1_val==-46340,
// opcode:c.beqz; op1:x10; op1val:-0xb504; immval:0x7e
TEST_CBRANCH_OP(c.beqz, x2, x10, -0xb504, 0x7e, 3f, x1, 304)
inst_77:
// rs1_val==1717986918,
// opcode:c.beqz; op1:x10; op1val:0x66666666; immval:0xe
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x66666666, 0xe, 3f, x1, 308)
inst_78:
// rs1_val==858993459,
// opcode:c.beqz; op1:x10; op1val:0x33333333; immval:0x12
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x33333333, 0x12, 3f, x1, 312)
inst_79:
// rs1_val==5,
// opcode:c.beqz; op1:x10; op1val:0x5; immval:0x10
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x5, 0x10, 1b, x1, 316)
inst_80:
// rs1_val==-1431655766, rs1_val == -1431655766
// opcode:c.beqz; op1:x10; op1val:-0x55555556; immval:0x40
TEST_CBRANCH_OP(c.beqz, x2, x10, -0x55555556, 0x40, 3f, x1, 320)
inst_81:
// rs1_val == 1431655765, rs1_val==1431655765
// opcode:c.beqz; op1:x10; op1val:0x55555555; immval:0x12
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x55555555, 0x12, 1b, x1, 324)
inst_82:
// rs1_val == 8,
// opcode:c.beqz; op1:x10; op1val:0x8; immval:0xe
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x8, 0xe, 1b, x1, 328)
inst_83:
// rs1_val==3,
// opcode:c.beqz; op1:x10; op1val:0x3; immval:0x4
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x3, 0x4, 1b, x1, 332)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
signature_x1_0:
.fill 0*(XLEN/32),4,0xdeadbeef
signature_x1_1:
.fill 84*(XLEN/32),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
RVMODEL_DATA_END

490
tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/cbnez-01.S
View File

@ -1,490 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version : 0.5.1
// timestamp : Wed Aug 4 06:39:00 2021 GMT
// usage : riscv_ctg \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32ec.cgf \
// --base-isa rv32e \
// --randomize
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the c.bnez instruction of the RISC-V C extension for the cbnez covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32EC")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",cbnez)
RVTEST_SIGBASE( x1,signature_x1_1)
inst_0:
// rs1==x11, rs1_val < 0 and imm_val < 0, rs1_val == -524289
// opcode: c.bnez; op1:x11; op1val:-0x80001; immval:0x4
TEST_CBRANCH_OP(c.bnez, x2, x11, -0x80001, 0x4, 1b, x1, 0)
inst_1:
// rs1==x10, rs1_val == 2147483647, rs1_val > 0 and imm_val > 0, rs1_val == (2**(xlen-1)-1)
// opcode: c.bnez; op1:x10; op1val:0x7fffffff; immval:0x7e
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x7fffffff, 0x7e, 3f, x1, 4)
inst_2:
// rs1==x8, rs1_val == -1073741825, rs1_val < 0 and imm_val > 0
// opcode: c.bnez; op1:x8; op1val:-0x40000001; immval:0xaa
TEST_CBRANCH_OP(c.bnez, x2, x8, -0x40000001, 0xaa, 3f, x1, 8)
inst_3:
// rs1==x12, rs1_val == -536870913,
// opcode: c.bnez; op1:x12; op1val:-0x20000001; immval:0xe
TEST_CBRANCH_OP(c.bnez, x2, x12, -0x20000001, 0xe, 1b, x1, 12)
inst_4:
// rs1==x15, rs1_val == -268435457,
// opcode: c.bnez; op1:x15; op1val:-0x10000001; immval:0x8
TEST_CBRANCH_OP(c.bnez, x2, x15, -0x10000001, 0x8, 3f, x1, 16)
inst_5:
// rs1==x13, rs1_val == -134217729,
// opcode: c.bnez; op1:x13; op1val:-0x8000001; immval:0xa
TEST_CBRANCH_OP(c.bnez, x2, x13, -0x8000001, 0xa, 1b, x1, 20)
inst_6:
// rs1==x9, rs1_val == -67108865,
// opcode: c.bnez; op1:x9; op1val:-0x4000001; immval:0xe
TEST_CBRANCH_OP(c.bnez, x2, x9, -0x4000001, 0xe, 1b, x1, 24)
inst_7:
// rs1==x14, rs1_val == -33554433,
// opcode: c.bnez; op1:x14; op1val:-0x2000001; immval:0x4
TEST_CBRANCH_OP(c.bnez, x2, x14, -0x2000001, 0x4, 3f, x1, 28)
inst_8:
// rs1_val == -16777217,
// opcode: c.bnez; op1:x10; op1val:-0x1000001; immval:0xaa
TEST_CBRANCH_OP(c.bnez, x2, x10, -0x1000001, 0xaa, 3f, x1, 32)
inst_9:
// rs1_val == -8388609,
// opcode: c.bnez; op1:x10; op1val:-0x800001; immval:0xc
TEST_CBRANCH_OP(c.bnez, x2, x10, -0x800001, 0xc, 3f, x1, 36)
inst_10:
// rs1_val == -4194305,
// opcode: c.bnez; op1:x10; op1val:-0x400001; immval:0x6
TEST_CBRANCH_OP(c.bnez, x2, x10, -0x400001, 0x6, 1b, x1, 40)
inst_11:
// rs1_val == -2097153,
// opcode: c.bnez; op1:x10; op1val:-0x200001; immval:0x40
TEST_CBRANCH_OP(c.bnez, x2, x10, -0x200001, 0x40, 3f, x1, 44)
inst_12:
// rs1_val == -1048577,
// opcode: c.bnez; op1:x10; op1val:-0x100001; immval:0xaa
TEST_CBRANCH_OP(c.bnez, x2, x10, -0x100001, 0xaa, 3f, x1, 48)
inst_13:
// rs1_val == -262145,
// opcode: c.bnez; op1:x10; op1val:-0x40001; immval:0xe
TEST_CBRANCH_OP(c.bnez, x2, x10, -0x40001, 0xe, 3f, x1, 52)
inst_14:
// rs1_val == -131073,
// opcode: c.bnez; op1:x10; op1val:-0x20001; immval:0x20
TEST_CBRANCH_OP(c.bnez, x2, x10, -0x20001, 0x20, 3f, x1, 56)
inst_15:
// rs1_val == -65537,
// opcode: c.bnez; op1:x10; op1val:-0x10001; immval:0x40
TEST_CBRANCH_OP(c.bnez, x2, x10, -0x10001, 0x40, 3f, x1, 60)
inst_16:
// rs1_val == -32769,
// opcode: c.bnez; op1:x10; op1val:-0x8001; immval:0xa
TEST_CBRANCH_OP(c.bnez, x2, x10, -0x8001, 0xa, 1b, x1, 64)
inst_17:
// rs1_val == -16385,
// opcode: c.bnez; op1:x10; op1val:-0x4001; immval:0x12
TEST_CBRANCH_OP(c.bnez, x2, x10, -0x4001, 0x12, 3f, x1, 68)
inst_18:
// rs1_val == -8193,
// opcode: c.bnez; op1:x10; op1val:-0x2001; immval:0xc
TEST_CBRANCH_OP(c.bnez, x2, x10, -0x2001, 0xc, 1b, x1, 72)
inst_19:
// rs1_val == -4097,
// opcode: c.bnez; op1:x10; op1val:-0x1001; immval:0x42
TEST_CBRANCH_OP(c.bnez, x2, x10, -0x1001, 0x42, 1b, x1, 76)
inst_20:
// rs1_val == -2049,
// opcode: c.bnez; op1:x10; op1val:-0x801; immval:0x80
TEST_CBRANCH_OP(c.bnez, x2, x10, -0x801, 0x80, 3f, x1, 80)
inst_21:
// rs1_val == -1025,
// opcode: c.bnez; op1:x10; op1val:-0x401; immval:0x12
TEST_CBRANCH_OP(c.bnez, x2, x10, -0x401, 0x12, 3f, x1, 84)
inst_22:
// rs1_val == -513,
// opcode: c.bnez; op1:x10; op1val:-0x201; immval:0x82
TEST_CBRANCH_OP(c.bnez, x2, x10, -0x201, 0x82, 1b, x1, 88)
inst_23:
// rs1_val == -257,
// opcode: c.bnez; op1:x10; op1val:-0x101; immval:0x80
TEST_CBRANCH_OP(c.bnez, x2, x10, -0x101, 0x80, 1b, x1, 92)
inst_24:
// rs1_val == -129,
// opcode: c.bnez; op1:x10; op1val:-0x81; immval:0xe
TEST_CBRANCH_OP(c.bnez, x2, x10, -0x81, 0xe, 3f, x1, 96)
inst_25:
// rs1_val == -65,
// opcode: c.bnez; op1:x10; op1val:-0x41; immval:0x10
TEST_CBRANCH_OP(c.bnez, x2, x10, -0x41, 0x10, 3f, x1, 100)
inst_26:
// rs1_val == -33,
// opcode: c.bnez; op1:x10; op1val:-0x21; immval:0x7e
TEST_CBRANCH_OP(c.bnez, x2, x10, -0x21, 0x7e, 3f, x1, 104)
inst_27:
// rs1_val == -17,
// opcode: c.bnez; op1:x10; op1val:-0x11; immval:0x20
TEST_CBRANCH_OP(c.bnez, x2, x10, -0x11, 0x20, 3f, x1, 108)
inst_28:
// rs1_val == -9,
// opcode: c.bnez; op1:x10; op1val:-0x9; immval:0x4
TEST_CBRANCH_OP(c.bnez, x2, x10, -0x9, 0x4, 1b, x1, 112)
inst_29:
// rs1_val == -5,
// opcode: c.bnez; op1:x10; op1val:-0x5; immval:0x80
TEST_CBRANCH_OP(c.bnez, x2, x10, -0x5, 0x80, 1b, x1, 116)
inst_30:
// rs1_val == -3,
// opcode: c.bnez; op1:x10; op1val:-0x3; immval:0xaa
TEST_CBRANCH_OP(c.bnez, x2, x10, -0x3, 0xaa, 3f, x1, 120)
inst_31:
// rs1_val == -2,
// opcode: c.bnez; op1:x10; op1val:-0x2; immval:0x10
TEST_CBRANCH_OP(c.bnez, x2, x10, -0x2, 0x10, 1b, x1, 124)
inst_32:
// rs1_val == -2147483648, rs1_val == (-2**(xlen-1))
// opcode: c.bnez; op1:x10; op1val:-0x80000000; immval:0x80
TEST_CBRANCH_OP(c.bnez, x2, x10, -0x80000000, 0x80, 1b, x1, 128)
inst_33:
// rs1_val == 1073741824,
// opcode: c.bnez; op1:x10; op1val:0x40000000; immval:0x7e
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x40000000, 0x7e, 3f, x1, 132)
inst_34:
// rs1_val == 536870912, rs1_val > 0 and imm_val < 0
// opcode: c.bnez; op1:x10; op1val:0x20000000; immval:0xc
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x20000000, 0xc, 1b, x1, 136)
inst_35:
// rs1_val == 268435456,
// opcode: c.bnez; op1:x10; op1val:0x10000000; immval:0x7e
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x10000000, 0x7e, 3f, x1, 140)
inst_36:
// rs1_val == 134217728,
// opcode: c.bnez; op1:x10; op1val:0x8000000; immval:0x82
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x8000000, 0x82, 1b, x1, 144)
inst_37:
// rs1_val == 67108864,
// opcode: c.bnez; op1:x10; op1val:0x4000000; immval:0xaa
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x4000000, 0xaa, 3f, x1, 148)
inst_38:
// rs1_val == 33554432,
// opcode: c.bnez; op1:x10; op1val:0x2000000; immval:0xe
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x2000000, 0xe, 1b, x1, 152)
inst_39:
// rs1_val == 16777216,
// opcode: c.bnez; op1:x10; op1val:0x1000000; immval:0xc
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x1000000, 0xc, 3f, x1, 156)
inst_40:
// rs1_val == 8388608,
// opcode: c.bnez; op1:x10; op1val:0x800000; immval:0x20
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x800000, 0x20, 3f, x1, 160)
inst_41:
// rs1_val == 4194304,
// opcode: c.bnez; op1:x10; op1val:0x400000; immval:0x8
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x400000, 0x8, 3f, x1, 164)
inst_42:
// rs1_val == 2097152,
// opcode: c.bnez; op1:x10; op1val:0x200000; immval:0x22
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x200000, 0x22, 1b, x1, 168)
inst_43:
// rs1_val == 1048576,
// opcode: c.bnez; op1:x10; op1val:0x100000; immval:0x4
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x100000, 0x4, 1b, x1, 172)
inst_44:
// rs1_val == 524288,
// opcode: c.bnez; op1:x10; op1val:0x80000; immval:0x8
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x80000, 0x8, 1b, x1, 176)
inst_45:
// rs1_val == 262144,
// opcode: c.bnez; op1:x10; op1val:0x40000; immval:0x6
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x40000, 0x6, 1b, x1, 180)
inst_46:
// rs1_val == 131072,
// opcode: c.bnez; op1:x10; op1val:0x20000; immval:0x6
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x20000, 0x6, 1b, x1, 184)
inst_47:
// rs1_val == 65536,
// opcode: c.bnez; op1:x10; op1val:0x10000; immval:0x7e
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x10000, 0x7e, 3f, x1, 188)
inst_48:
// rs1_val == 32768,
// opcode: c.bnez; op1:x10; op1val:0x8000; immval:0x7e
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x8000, 0x7e, 3f, x1, 192)
inst_49:
// rs1_val == 16384,
// opcode: c.bnez; op1:x10; op1val:0x4000; immval:0xac
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x4000, 0xac, 1b, x1, 196)
inst_50:
// rs1_val == 8192,
// opcode: c.bnez; op1:x10; op1val:0x2000; immval:0x10
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x2000, 0x10, 3f, x1, 200)
inst_51:
// rs1_val == 4096,
// opcode: c.bnez; op1:x10; op1val:0x1000; immval:0xc
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x1000, 0xc, 1b, x1, 204)
inst_52:
// rs1_val == 2048,
// opcode: c.bnez; op1:x10; op1val:0x800; immval:0x7e
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x800, 0x7e, 3f, x1, 208)
inst_53:
// rs1_val == 1024,
// opcode: c.bnez; op1:x10; op1val:0x400; immval:0xa
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x400, 0xa, 1b, x1, 212)
inst_54:
// rs1_val == 512,
// opcode: c.bnez; op1:x10; op1val:0x200; immval:0x12
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x200, 0x12, 3f, x1, 216)
inst_55:
// rs1_val == 256,
// opcode: c.bnez; op1:x10; op1val:0x100; immval:0xe
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x100, 0xe, 3f, x1, 220)
inst_56:
// rs1_val == 128,
// opcode: c.bnez; op1:x10; op1val:0x80; immval:0xe
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x80, 0xe, 1b, x1, 224)
inst_57:
// rs1_val == 64,
// opcode: c.bnez; op1:x10; op1val:0x40; immval:0x22
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x40, 0x22, 1b, x1, 228)
inst_58:
// rs1_val == 32,
// opcode: c.bnez; op1:x10; op1val:0x20; immval:0x4
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x20, 0x4, 1b, x1, 232)
inst_59:
// rs1_val == 16,
// opcode: c.bnez; op1:x10; op1val:0x10; immval:0x8
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x10, 0x8, 3f, x1, 236)
inst_60:
// rs1_val == 1,
// opcode: c.bnez; op1:x10; op1val:0x1; immval:0x4
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x1, 0x4, 3f, x1, 240)
inst_61:
// rs1_val==46341,
// opcode: c.bnez; op1:x10; op1val:0xb505; immval:0x12
TEST_CBRANCH_OP(c.bnez, x2, x10, 0xb505, 0x12, 1b, x1, 244)
inst_62:
// rs1_val==-46339,
// opcode: c.bnez; op1:x10; op1val:-0xb503; immval:0x22
TEST_CBRANCH_OP(c.bnez, x2, x10, -0xb503, 0x22, 1b, x1, 248)
inst_63:
// rs1_val==1717986919,
// opcode: c.bnez; op1:x10; op1val:0x66666667; immval:0x8
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x66666667, 0x8, 3f, x1, 252)
inst_64:
// rs1_val==858993460,
// opcode: c.bnez; op1:x10; op1val:0x33333334; immval:0x4
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x33333334, 0x4, 1b, x1, 256)
inst_65:
// rs1_val==6,
// opcode: c.bnez; op1:x10; op1val:0x6; immval:0x6
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x6, 0x6, 1b, x1, 260)
inst_66:
// rs1_val==-1431655765,
// opcode: c.bnez; op1:x10; op1val:-0x55555555; immval:0x20
TEST_CBRANCH_OP(c.bnez, x2, x10, -0x55555555, 0x20, 3f, x1, 264)
inst_67:
// rs1_val==1431655766,
// opcode: c.bnez; op1:x10; op1val:0x55555556; immval:0x12
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x55555556, 0x12, 3f, x1, 268)
inst_68:
// rs1_val==4, rs1_val == 4
// opcode: c.bnez; op1:x10; op1val:0x4; immval:0xac
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x4, 0xac, 1b, x1, 272)
inst_69:
// rs1_val==46339,
// opcode: c.bnez; op1:x10; op1val:0xb503; immval:0x7e
TEST_CBRANCH_OP(c.bnez, x2, x10, 0xb503, 0x7e, 3f, x1, 276)
inst_70:
// rs1_val==0, rs1_val == 0, rs1_val == 0 and imm_val < 0
// opcode: c.bnez; op1:x10; op1val:0x0; immval:0x12
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x0, 0x12, 1b, x1, 280)
inst_71:
// rs1_val==1717986917,
// opcode: c.bnez; op1:x10; op1val:0x66666665; immval:0x8
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x66666665, 0x8, 3f, x1, 284)
inst_72:
// rs1_val==858993458,
// opcode: c.bnez; op1:x10; op1val:0x33333332; immval:0x80
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x33333332, 0x80, 1b, x1, 288)
inst_73:
// rs1_val==1431655764,
// opcode: c.bnez; op1:x10; op1val:0x55555554; immval:0x12
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x55555554, 0x12, 3f, x1, 292)
inst_74:
// rs1_val==2, rs1_val == 2
// opcode: c.bnez; op1:x10; op1val:0x2; immval:0x12
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x2, 0x12, 1b, x1, 296)
inst_75:
// rs1_val==46340,
// opcode: c.bnez; op1:x10; op1val:0xb504; immval:0xaa
TEST_CBRANCH_OP(c.bnez, x2, x10, 0xb504, 0xaa, 3f, x1, 300)
inst_76:
// rs1_val==-46340,
// opcode: c.bnez; op1:x10; op1val:-0xb504; immval:0x4
TEST_CBRANCH_OP(c.bnez, x2, x10, -0xb504, 0x4, 1b, x1, 304)
inst_77:
// rs1_val==1717986918,
// opcode: c.bnez; op1:x10; op1val:0x66666666; immval:0x8
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x66666666, 0x8, 3f, x1, 308)
inst_78:
// rs1_val==858993459,
// opcode: c.bnez; op1:x10; op1val:0x33333333; immval:0x22
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x33333333, 0x22, 1b, x1, 312)
inst_79:
// rs1_val==5,
// opcode: c.bnez; op1:x10; op1val:0x5; immval:0x12
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x5, 0x12, 1b, x1, 316)
inst_80:
// rs1_val==-1431655766, rs1_val == -1431655766
// opcode: c.bnez; op1:x10; op1val:-0x55555556; immval:0xac
TEST_CBRANCH_OP(c.bnez, x2, x10, -0x55555556, 0xac, 1b, x1, 320)
inst_81:
// rs1_val==1431655765, rs1_val == 1431655765
// opcode: c.bnez; op1:x10; op1val:0x55555555; immval:0x4
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x55555555, 0x4, 1b, x1, 324)
inst_82:
// rs1_val == 8,
// opcode: c.bnez; op1:x10; op1val:0x8; immval:0xaa
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x8, 0xaa, 3f, x1, 328)
inst_83:
// rs1_val==3,
// opcode: c.bnez; op1:x10; op1val:0x3; immval:0xaa
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x3, 0xaa, 3f, x1, 332)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
signature_x1_0:
.fill 0*(XLEN/32),4,0xdeadbeef
signature_x1_1:
.fill 84*(XLEN/32),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
RVMODEL_DATA_END

155
tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/cj-01.S
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@ -1,155 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version : 0.5.1
// timestamp : Wed Aug 4 06:39:00 2021 GMT
// usage : riscv_ctg \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32ec.cgf \
// --base-isa rv32e \
// --randomize
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the c.j instruction of the RISC-V C extension for the cj covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32EC")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",cj)
RVTEST_SIGBASE( x1,signature_x1_1)
inst_0:
// imm_val < 0, imm_val == -66
// opcode:c.j; immval:0x42
TEST_CJ_OP(c.j, x2, 0x42, 1b, x1, 0)
inst_1:
// imm_val == -1026,
// opcode:c.j; immval:0x402
TEST_CJ_OP(c.j, x2, 0x402, 1b, x1, 4)
inst_2:
// imm_val == -514,
// opcode:c.j; immval:0x202
TEST_CJ_OP(c.j, x2, 0x202, 1b, x1, 8)
inst_3:
// imm_val == -258,
// opcode:c.j; immval:0x102
TEST_CJ_OP(c.j, x2, 0x102, 1b, x1, 12)
inst_4:
// imm_val == -130,
// opcode:c.j; immval:0x82
TEST_CJ_OP(c.j, x2, 0x82, 1b, x1, 16)
inst_5:
// imm_val == -34,
// opcode:c.j; immval:0x22
TEST_CJ_OP(c.j, x2, 0x22, 1b, x1, 20)
inst_6:
// imm_val == -18,
// opcode:c.j; immval:0x12
TEST_CJ_OP(c.j, x2, 0x12, 1b, x1, 24)
inst_7:
// imm_val == -10,
// opcode:c.j; immval:0xa
TEST_CJ_OP(c.j, x2, 0xa, 1b, x1, 28)
inst_8:
// imm_val == 1024, imm_val > 0
// opcode:c.j; immval:0x400
TEST_CJ_OP(c.j, x2, 0x400, 3f, x1, 32)
inst_9:
// imm_val == 512,
// opcode:c.j; immval:0x200
TEST_CJ_OP(c.j, x2, 0x200, 3f, x1, 36)
inst_10:
// imm_val == 1364,
// opcode:c.j; immval:0x554
TEST_CJ_OP(c.j, x2, 0x554, 3f, x1, 40)
inst_11:
// imm_val == -1366,
// opcode:c.j; immval:0x556
TEST_CJ_OP(c.j, x2, 0x556, 1b, x1, 44)
inst_12:
// imm_val == 256,
// opcode:c.j; immval:0x100
TEST_CJ_OP(c.j, x2, 0x100, 3f, x1, 48)
inst_13:
// imm_val == 128,
// opcode:c.j; immval:0x80
TEST_CJ_OP(c.j, x2, 0x80, 3f, x1, 52)
inst_14:
// imm_val == 64,
// opcode:c.j; immval:0x40
TEST_CJ_OP(c.j, x2, 0x40, 3f, x1, 56)
inst_15:
// imm_val == 32,
// opcode:c.j; immval:0x20
TEST_CJ_OP(c.j, x2, 0x20, 3f, x1, 60)
inst_16:
// imm_val == 16,
// opcode:c.j; immval:0x10
TEST_CJ_OP(c.j, x2, 0x10, 3f, x1, 64)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
signature_x1_0:
.fill 0*(XLEN/32),4,0xdeadbeef
signature_x1_1:
.fill 17*(XLEN/32),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
RVMODEL_DATA_END

160
tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/cjal-01.S
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@ -1,160 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version : 0.5.1
// timestamp : Wed Aug 4 06:39:00 2021 GMT
// usage : riscv_ctg \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32ec.cgf \
// --base-isa rv32e \
// --randomize
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the c.jal instruction of the RISC-V C extension for the cjal covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32EC")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*RV32.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",cjal)
RVTEST_SIGBASE( x2,signature_x2_1)
inst_0:
// imm_val < 0,
// opcode:c.jal; immval:0x10
TEST_CJAL_OP(c.jal, x3, 0x10, 1b, x2, 0)
inst_1:
// imm_val == -1026,
// opcode:c.jal; immval:0x402
TEST_CJAL_OP(c.jal, x3, 0x402, 1b, x2, 4)
inst_2:
// imm_val == -514,
// opcode:c.jal; immval:0x202
TEST_CJAL_OP(c.jal, x3, 0x202, 1b, x2, 8)
inst_3:
// imm_val == -258,
// opcode:c.jal; immval:0x102
TEST_CJAL_OP(c.jal, x3, 0x102, 1b, x2, 12)
inst_4:
// imm_val == -130,
// opcode:c.jal; immval:0x82
TEST_CJAL_OP(c.jal, x3, 0x82, 1b, x2, 16)
inst_5:
// imm_val == -66,
// opcode:c.jal; immval:0x42
TEST_CJAL_OP(c.jal, x3, 0x42, 1b, x2, 20)
inst_6:
// imm_val == -34,
// opcode:c.jal; immval:0x22
TEST_CJAL_OP(c.jal, x3, 0x22, 1b, x2, 24)
inst_7:
// imm_val == -18,
// opcode:c.jal; immval:0x12
TEST_CJAL_OP(c.jal, x3, 0x12, 1b, x2, 28)
inst_8:
// imm_val == -10,
// opcode:c.jal; immval:0xa
TEST_CJAL_OP(c.jal, x3, 0xa, 1b, x2, 32)
inst_9:
// imm_val == 1024, imm_val > 0
// opcode:c.jal; immval:0x400
TEST_CJAL_OP(c.jal, x3, 0x400, 3f, x2, 36)
inst_10:
// imm_val == 512,
// opcode:c.jal; immval:0x200
TEST_CJAL_OP(c.jal, x3, 0x200, 3f, x2, 40)
inst_11:
// imm_val == 1364,
// opcode:c.jal; immval:0x554
TEST_CJAL_OP(c.jal, x3, 0x554, 3f, x2, 44)
inst_12:
// imm_val == -1366,
// opcode:c.jal; immval:0x556
TEST_CJAL_OP(c.jal, x3, 0x556, 1b, x2, 48)
inst_13:
// imm_val == 256,
// opcode:c.jal; immval:0x100
TEST_CJAL_OP(c.jal, x3, 0x100, 3f, x2, 52)
inst_14:
// imm_val == 128,
// opcode:c.jal; immval:0x80
TEST_CJAL_OP(c.jal, x3, 0x80, 3f, x2, 56)
inst_15:
// imm_val == 64,
// opcode:c.jal; immval:0x40
TEST_CJAL_OP(c.jal, x3, 0x40, 3f, x2, 60)
inst_16:
// imm_val == 32,
// opcode:c.jal; immval:0x20
TEST_CJAL_OP(c.jal, x3, 0x20, 3f, x2, 64)
inst_17:
// imm_val == 16,
// opcode:c.jal; immval:0x10
TEST_CJAL_OP(c.jal, x3, 0x10, 3f, x2, 68)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
signature_x2_0:
.fill 0*(XLEN/32),4,0xdeadbeef
signature_x2_1:
.fill 18*(XLEN/32),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
RVMODEL_DATA_END

150
tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/cjalr-01.S
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@ -1,150 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version : 0.5.1
// timestamp : Wed Aug 4 06:39:00 2021 GMT
// usage : riscv_ctg \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32ec.cgf \
// --base-isa rv32e \
// --randomize
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the c.jalr instruction of the RISC-V C extension for the cjalr covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32EC")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",cjalr)
RVTEST_SIGBASE( x10,signature_x10_1)
inst_0:
// rs1==x6,
// opcode:c.jalr; op1:x6
TEST_CJALR_OP(x11, x6, x10, 0)
inst_1:
// rs1==x4,
// opcode:c.jalr; op1:x4
TEST_CJALR_OP(x11, x4, x10, 4)
inst_2:
// rs1==x3,
// opcode:c.jalr; op1:x3
TEST_CJALR_OP(x11, x3, x10, 8)
inst_3:
// rs1==x1,
// opcode:c.jalr; op1:x1
TEST_CJALR_OP(x11, x1, x10, 12)
inst_4:
// rs1==x12,
// opcode:c.jalr; op1:x12
TEST_CJALR_OP(x11, x12, x10, 16)
inst_5:
// rs1==x2,
// opcode:c.jalr; op1:x2
TEST_CJALR_OP(x11, x2, x10, 20)
inst_6:
// rs1==x8,
// opcode:c.jalr; op1:x8
TEST_CJALR_OP(x11, x8, x10, 24)
inst_7:
// rs1==x7,
// opcode:c.jalr; op1:x7
TEST_CJALR_OP(x11, x7, x10, 28)
inst_8:
// rs1==x15,
// opcode:c.jalr; op1:x15
TEST_CJALR_OP(x11, x15, x10, 32)
inst_9:
// rs1==x5,
// opcode:c.jalr; op1:x5
TEST_CJALR_OP(x11, x5, x10, 36)
inst_10:
// rs1==x9,
// opcode:c.jalr; op1:x9
TEST_CJALR_OP(x11, x9, x10, 40)
inst_11:
// rs1==x14,
// opcode:c.jalr; op1:x14
TEST_CJALR_OP(x3, x14, x10, 44)
RVTEST_SIGBASE( x2,signature_x2_0)
inst_12:
// rs1==x11,
// opcode:c.jalr; op1:x11
TEST_CJALR_OP(x3, x11, x2, 0)
inst_13:
// rs1==x13,
// opcode:c.jalr; op1:x13
TEST_CJALR_OP(x3, x13, x2, 4)
inst_14:
// rs1==x10,
// opcode:c.jalr; op1:x10
TEST_CJALR_OP(x3, x10, x2, 8)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
signature_x10_0:
.fill 0*(XLEN/32),4,0xdeadbeef
signature_x10_1:
.fill 12*(XLEN/32),4,0xdeadbeef
signature_x2_0:
.fill 3*(XLEN/32),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
RVMODEL_DATA_END

150
tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/cjr-01.S
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@ -1,150 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version : 0.5.1
// timestamp : Wed Aug 4 06:39:00 2021 GMT
// usage : riscv_ctg \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32ec.cgf \
// --base-isa rv32e \
// --randomize
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the c.jr instruction of the RISC-V C extension for the cjr covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32EC")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",cjr)
RVTEST_SIGBASE( x1,signature_x1_1)
inst_0:
// rs1==x6,
// opcode: c.jr; op1:x6
TEST_CJR_OP(x7, x6, x1, 0)
inst_1:
// rs1==x15,
// opcode: c.jr; op1:x15
TEST_CJR_OP(x7, x15, x1, 4)
inst_2:
// rs1==x14,
// opcode: c.jr; op1:x14
TEST_CJR_OP(x7, x14, x1, 8)
inst_3:
// rs1==x13,
// opcode: c.jr; op1:x13
TEST_CJR_OP(x7, x13, x1, 12)
inst_4:
// rs1==x3,
// opcode: c.jr; op1:x3
TEST_CJR_OP(x7, x3, x1, 16)
inst_5:
// rs1==x8,
// opcode: c.jr; op1:x8
TEST_CJR_OP(x7, x8, x1, 20)
inst_6:
// rs1==x2,
// opcode: c.jr; op1:x2
TEST_CJR_OP(x7, x2, x1, 24)
inst_7:
// rs1==x4,
// opcode: c.jr; op1:x4
TEST_CJR_OP(x7, x4, x1, 28)
inst_8:
// rs1==x12,
// opcode: c.jr; op1:x12
TEST_CJR_OP(x7, x12, x1, 32)
inst_9:
// rs1==x5,
// opcode: c.jr; op1:x5
TEST_CJR_OP(x7, x5, x1, 36)
inst_10:
// rs1==x7,
// opcode: c.jr; op1:x7
TEST_CJR_OP(x3, x7, x1, 40)
RVTEST_SIGBASE( x2,signature_x2_0)
inst_11:
// rs1==x9,
// opcode: c.jr; op1:x9
TEST_CJR_OP(x3, x9, x2, 0)
inst_12:
// rs1==x1,
// opcode: c.jr; op1:x1
TEST_CJR_OP(x3, x1, x2, 4)
inst_13:
// rs1==x11,
// opcode: c.jr; op1:x11
TEST_CJR_OP(x3, x11, x2, 8)
inst_14:
// rs1==x10,
// opcode: c.jr; op1:x10
TEST_CJR_OP(x3, x10, x2, 12)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
signature_x1_0:
.fill 0*(XLEN/32),4,0xdeadbeef
signature_x1_1:
.fill 11*(XLEN/32),4,0xdeadbeef
signature_x2_0:
.fill 4*(XLEN/32),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
RVMODEL_DATA_END

160
tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/cli-01.S
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@ -1,160 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version : 0.5.1
// timestamp : Wed Aug 4 06:39:00 2021 GMT
// usage : riscv_ctg \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32ec.cgf \
// --base-isa rv32e \
// --randomize
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the c.li instruction of the RISC-V C extension for the cli covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32EC")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",cli)
RVTEST_SIGBASE( x4,signature_x4_1)
inst_0:
// rd==x15, imm_val == (-2**(6-1)), imm_val == -32
// opcode:c.li; dest:x15; immval:-0x20
TEST_CASE(x7, x15, -0x20, x4, 0, c.li x15, -0x20;)
inst_1:
// rd==x8, imm_val == 31, imm_val == (2**(6-1)-1)
// opcode:c.li; dest:x8; immval:0x1f
TEST_CASE(x7, x8, 0x1f, x4, 4, c.li x8, 0x1f;)
inst_2:
// rd==x13, imm_val == -17,
// opcode:c.li; dest:x13; immval:-0x11
TEST_CASE(x7, x13, -0x11, x4, 8, c.li x13, -0x11;)
inst_3:
// rd==x6, imm_val == -9,
// opcode:c.li; dest:x6; immval:-0x9
TEST_CASE(x7, x6, -0x9, x4, 12, c.li x6, -0x9;)
inst_4:
// rd==x2, imm_val == -5,
// opcode:c.li; dest:x2; immval:-0x5
TEST_CASE(x7, x2, -0x5, x4, 16, c.li x2, -0x5;)
inst_5:
// rd==x12, imm_val == -3,
// opcode:c.li; dest:x12; immval:-0x3
TEST_CASE(x7, x12, -0x3, x4, 20, c.li x12, -0x3;)
inst_6:
// rd==x1, imm_val == -2,
// opcode:c.li; dest:x1; immval:-0x2
TEST_CASE(x7, x1, -0x2, x4, 24, c.li x1, -0x2;)
inst_7:
// rd==x14, imm_val == 16,
// opcode:c.li; dest:x14; immval:0x10
TEST_CASE(x7, x14, 0x10, x4, 28, c.li x14, 0x10;)
inst_8:
// rd==x3, imm_val == 0,
// opcode:c.li; dest:x3; immval:0x0
TEST_CASE(x7, x3, 0x0, x4, 32, c.li x3, 0x0;)
inst_9:
// rd==x5, imm_val == 8,
// opcode:c.li; dest:x5; immval:0x8
TEST_CASE(x7, x5, 0x8, x4, 36, c.li x5, 0x8;)
inst_10:
// rd==x10, imm_val == 4,
// opcode:c.li; dest:x10; immval:0x4
TEST_CASE(x7, x10, 0x4, x4, 40, c.li x10, 0x4;)
inst_11:
// rd==x0, imm_val == 2,
// opcode:c.li; dest:x0; immval:0x2
TEST_CASE(x2, x0, 0, x4, 44, c.li x0, 0x2;)
inst_12:
// rd==x11, imm_val == 1,
// opcode:c.li; dest:x11; immval:0x1
TEST_CASE(x2, x11, 0x1, x4, 48, c.li x11, 0x1;)
RVTEST_SIGBASE( x1,signature_x1_0)
inst_13:
// rd==x7, imm_val == -22,
// opcode:c.li; dest:x7; immval:-0x16
TEST_CASE(x2, x7, -0x16, x1, 0, c.li x7, -0x16;)
inst_14:
// rd==x4, imm_val == 21,
// opcode:c.li; dest:x4; immval:0x15
TEST_CASE(x2, x4, 0x15, x1, 4, c.li x4, 0x15;)
inst_15:
// rd==x9,
// opcode:c.li; dest:x9; immval:0x0
TEST_CASE(x2, x9, 0x0, x1, 8, c.li x9, 0x0;)
inst_16:
// imm_val == 2,
// opcode:c.li; dest:x10; immval:0x2
TEST_CASE(x2, x10, 0x2, x1, 12, c.li x10, 0x2;)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
signature_x4_0:
.fill 0*(XLEN/32),4,0xdeadbeef
signature_x4_1:
.fill 13*(XLEN/32),4,0xdeadbeef
signature_x1_0:
.fill 4*(XLEN/32),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
RVMODEL_DATA_END

150
tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/clui-01.S
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@ -1,150 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version : 0.5.1
// timestamp : Wed Aug 4 06:39:00 2021 GMT
// usage : riscv_ctg \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32ec.cgf \
// --base-isa rv32e \
// --randomize
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the c.lui instruction of the RISC-V C extension for the clui covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32EC")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",clui)
RVTEST_SIGBASE( x2,signature_x2_1)
inst_0:
// rd==x8, rs1_val < 0 and imm_val < 32 and imm_val !=0 , imm_val == 4
// opcode:c.lui; op1:x8; dest:x8 op1val:-0x1000001; immval:0x4
TEST_CI_OP( c.lui, x8, 0x4000, -0x1000001, 0x4, x2, 0, x5)
inst_1:
// rd==x10, imm_val == 31,
// opcode:c.lui; op1:x10; dest:x10 op1val:-0x4; immval:0x1f
TEST_CI_OP( c.lui, x10, 0x1f000, -0x4, 0x1f, x2, 4, x5)
inst_2:
// rd==x6, imm_val == 47, rs1_val > 0 and imm_val > 32
// opcode:c.lui; op1:x6; dest:x6 op1val:0x4000; immval:0xfffef
TEST_CI_OP( c.lui, x6, -0x11000, 0x4000, 0xfffef, x2, 8, x5)
inst_3:
// rd==x9, imm_val == 55, rs1_val < 0 and imm_val > 32
// opcode:c.lui; op1:x9; dest:x9 op1val:-0x3; immval:0xffff7
TEST_CI_OP( c.lui, x9, -0x9000, -0x3, 0xffff7, x2, 12, x5)
inst_4:
// rd==x15, imm_val == 59,
// opcode:c.lui; op1:x15; dest:x15 op1val:0x4; immval:0xffffb
TEST_CI_OP( c.lui, x15, -0x5000, 0x4, 0xffffb, x2, 16, x5)
inst_5:
// rd==x1, imm_val == 61,
// opcode:c.lui; op1:x1; dest:x1 op1val:-0x20000001; immval:0xffffd
TEST_CI_OP( c.lui, x1, -0x3000, -0x20000001, 0xffffd, x2, 20, x5)
inst_6:
// rd==x0, imm_val == 62,
// opcode:c.lui; op1:x0; dest:x0 op1val:-0x20000001; immval:0xffffe
TEST_CI_OP( c.lui, x0, 0, -0x20000001, 0xffffe, x2, 24, x5)
inst_7:
// rd==x7, imm_val == 32,
// opcode:c.lui; op1:x7; dest:x7 op1val:0x4000; immval:0xfffe0
TEST_CI_OP( c.lui, x7, -0x20000, 0x4000, 0xfffe0, x2, 28, x5)
inst_8:
// rd==x3, rs1_val > 0 and imm_val < 32 and imm_val !=0 ,
// opcode:c.lui; op1:x3; dest:x3 op1val:0x10; immval:0xc
TEST_CI_OP( c.lui, x3, 0xc000, 0x10, 0xc, x2, 32, x5)
inst_9:
// rd==x4, imm_val == 16,
// opcode:c.lui; op1:x4; dest:x4 op1val:0x7fffffff; immval:0x10
TEST_CI_OP( c.lui, x4, 0x10000, 0x7fffffff, 0x10, x2, 36, x5)
inst_10:
// rd==x11, imm_val == 8,
// opcode:c.lui; op1:x11; dest:x11 op1val:-0x20001; immval:0x8
TEST_CI_OP( c.lui, x11, 0x8000, -0x20001, 0x8, x2, 40, x5)
inst_11:
// rd==x12, imm_val == 2,
// opcode:c.lui; op1:x12; dest:x12 op1val:0x200000; immval:0x2
TEST_CI_OP( c.lui, x12, 0x2000, 0x200000, 0x2, x2, 44, x5)
inst_12:
// rd==x13, imm_val == 1,
// opcode:c.lui; op1:x13; dest:x13 op1val:-0x2001; immval:0x1
TEST_CI_OP( c.lui, x13, 0x1000, -0x2001, 0x1, x2, 48, x3)
RVTEST_SIGBASE( x1,signature_x1_0)
inst_13:
// rd==x14, imm_val == 42,
// opcode:c.lui; op1:x14; dest:x14 op1val:0x400000; immval:0xfffea
TEST_CI_OP( c.lui, x14, -0x16000, 0x400000, 0xfffea, x1, 0, x3)
inst_14:
// rd==x5, imm_val == 21,
// opcode:c.lui; op1:x5; dest:x5 op1val:-0x10001; immval:0x15
TEST_CI_OP( c.lui, x5, 0x15000, -0x10001, 0x15, x1, 4, x3)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
signature_x2_0:
.fill 0*(XLEN/32),4,0xdeadbeef
signature_x2_1:
.fill 13*(XLEN/32),4,0xdeadbeef
signature_x1_0:
.fill 2*(XLEN/32),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
RVMODEL_DATA_END

135
tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/clw-01.S
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@ -1,135 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version : 0.5.1
// timestamp : Wed Aug 4 06:39:00 2021 GMT
// usage : riscv_ctg \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32ec.cgf \
// --base-isa rv32e \
// --randomize
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the c.lw instruction of the RISC-V C extension for the clw covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32EC")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",clw)
RVTEST_SIGBASE( x1,signature_x1_1)
inst_0:
// rs1 == rd, rd==x8, rs1==x8, imm_val == 0,
// opcode: c.lw; op1:x8; dest:x8; immval:0x0
TEST_LOAD(x1,x2,0,x8,x8,0x0,0,c.lw,0)
inst_1:
// rs1 != rd, rd==x14, rs1==x12, imm_val == 60, imm_val > 0
// opcode: c.lw; op1:x12; dest:x14; immval:0x3c
TEST_LOAD(x1,x2,0,x12,x14,0x3c,4,c.lw,0)
inst_2:
// rd==x15, rs1==x11, imm_val == 92,
// opcode: c.lw; op1:x11; dest:x15; immval:0x5c
TEST_LOAD(x1,x2,0,x11,x15,0x5c,8,c.lw,0)
inst_3:
// rd==x10, rs1==x15, imm_val == 108,
// opcode: c.lw; op1:x15; dest:x10; immval:0x6c
TEST_LOAD(x1,x2,0,x15,x10,0x6c,12,c.lw,0)
inst_4:
// rd==x13, rs1==x14, imm_val == 116,
// opcode: c.lw; op1:x14; dest:x13; immval:0x74
TEST_LOAD(x1,x2,0,x14,x13,0x74,16,c.lw,0)
inst_5:
// rd==x11, rs1==x13, imm_val == 120,
// opcode: c.lw; op1:x13; dest:x11; immval:0x78
TEST_LOAD(x1,x2,0,x13,x11,0x78,20,c.lw,0)
inst_6:
// rd==x12, rs1==x10, imm_val == 64,
// opcode: c.lw; op1:x10; dest:x12; immval:0x40
TEST_LOAD(x1,x2,0,x10,x12,0x40,24,c.lw,0)
inst_7:
// rd==x9, imm_val == 32,
// opcode: c.lw; op1:x10; dest:x9; immval:0x20
TEST_LOAD(x1,x2,0,x10,x9,0x20,28,c.lw,0)
inst_8:
// rs1==x9, imm_val == 16,
// opcode: c.lw; op1:x9; dest:x8; immval:0x10
TEST_LOAD(x1,x2,0,x9,x8,0x10,32,c.lw,0)
inst_9:
// imm_val == 8,
// opcode: c.lw; op1:x11; dest:x10; immval:0x8
TEST_LOAD(x1,x2,0,x11,x10,0x8,36,c.lw,0)
inst_10:
// imm_val == 4,
// opcode: c.lw; op1:x11; dest:x10; immval:0x4
TEST_LOAD(x1,x2,0,x11,x10,0x4,40,c.lw,0)
inst_11:
// imm_val == 40,
// opcode: c.lw; op1:x11; dest:x10; immval:0x28
TEST_LOAD(x1,x2,0,x11,x10,0x28,44,c.lw,0)
inst_12:
// imm_val == 84,
// opcode: c.lw; op1:x11; dest:x10; immval:0x54
TEST_LOAD(x1,x2,0,x11,x10,0x54,48,c.lw,0)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
signature_x1_0:
.fill 0*(XLEN/32),4,0xdeadbeef
signature_x1_1:
.fill 13*(XLEN/32),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
RVMODEL_DATA_END

150
tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/clwsp-01.S
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@ -1,150 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version : 0.5.1
// timestamp : Wed Aug 4 06:39:00 2021 GMT
// usage : riscv_ctg \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32ec.cgf \
// --base-isa rv32e \
// --randomize
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the c.lwsp instruction of the RISC-V C extension for the clwsp covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32EC")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",clwsp)
RVTEST_SIGBASE( x5,signature_x5_1)
inst_0:
// rd==x2, imm_val == 0,
// opcode: c.lwsp; op1:x2; dest:x2; immval:0x0
TEST_LOAD(x5,x7,0,x2,x2,0x0,0,c.lwsp,0)
inst_1:
// rd==x11, imm_val == 124, imm_val > 0
// opcode: c.lwsp; op1:x2; dest:x11; immval:0x7c
TEST_LOAD(x5,x7,0,x2,x11,0x7c,4,c.lwsp,0)
inst_2:
// rd==x3, imm_val == 188,
// opcode: c.lwsp; op1:x2; dest:x3; immval:0xbc
TEST_LOAD(x5,x7,0,x2,x3,0xbc,8,c.lwsp,0)
inst_3:
// rd==x6, imm_val == 220,
// opcode: c.lwsp; op1:x2; dest:x6; immval:0xdc
TEST_LOAD(x5,x7,0,x2,x6,0xdc,12,c.lwsp,0)
inst_4:
// rd==x9, imm_val == 236,
// opcode: c.lwsp; op1:x2; dest:x9; immval:0xec
TEST_LOAD(x5,x7,0,x2,x9,0xec,16,c.lwsp,0)
inst_5:
// rd==x1, imm_val == 244,
// opcode: c.lwsp; op1:x2; dest:x1; immval:0xf4
TEST_LOAD(x5,x7,0,x2,x1,0xf4,20,c.lwsp,0)
inst_6:
// rd==x4, imm_val == 248,
// opcode: c.lwsp; op1:x2; dest:x4; immval:0xf8
TEST_LOAD(x5,x7,0,x2,x4,0xf8,24,c.lwsp,0)
inst_7:
// rd==x8, imm_val == 128,
// opcode: c.lwsp; op1:x2; dest:x8; immval:0x80
TEST_LOAD(x5,x7,0,x2,x8,0x80,28,c.lwsp,0)
inst_8:
// rd==x15, imm_val == 64,
// opcode: c.lwsp; op1:x2; dest:x15; immval:0x40
TEST_LOAD(x5,x7,0,x2,x15,0x40,32,c.lwsp,0)
inst_9:
// rd==x12, imm_val == 32,
// opcode: c.lwsp; op1:x2; dest:x12; immval:0x20
TEST_LOAD(x5,x7,0,x2,x12,0x20,36,c.lwsp,0)
inst_10:
// rd==x10, imm_val == 16,
// opcode: c.lwsp; op1:x2; dest:x10; immval:0x10
TEST_LOAD(x5,x7,0,x2,x10,0x10,40,c.lwsp,0)
inst_11:
// rd==x14, imm_val == 8,
// opcode: c.lwsp; op1:x2; dest:x14; immval:0x8
TEST_LOAD(x5,x3,0,x2,x14,0x8,44,c.lwsp,0)
RVTEST_SIGBASE( x1,signature_x1_0)
inst_12:
// rd==x13, imm_val == 4,
// opcode: c.lwsp; op1:x2; dest:x13; immval:0x4
TEST_LOAD(x1,x3,0,x2,x13,0x4,0,c.lwsp,0)
inst_13:
// rd==x5, imm_val == 168,
// opcode: c.lwsp; op1:x2; dest:x5; immval:0xa8
TEST_LOAD(x1,x3,0,x2,x5,0xa8,4,c.lwsp,0)
inst_14:
// rd==x7, imm_val == 84,
// opcode: c.lwsp; op1:x2; dest:x7; immval:0x54
TEST_LOAD(x1,x3,0,x2,x7,0x54,8,c.lwsp,0)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
signature_x5_0:
.fill 0*(XLEN/32),4,0xdeadbeef
signature_x5_1:
.fill 12*(XLEN/32),4,0xdeadbeef
signature_x1_0:
.fill 3*(XLEN/32),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
RVMODEL_DATA_END

500
tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/cmv-01.S
View File

@ -1,500 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version : 0.5.1
// timestamp : Wed Aug 4 06:39:00 2021 GMT
// usage : riscv_ctg \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32ec.cgf \
// --base-isa rv32e \
// --randomize
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the c.mv instruction of the RISC-V C extension for the cmv covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32EC")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",cmv)
RVTEST_SIGBASE( x4,signature_x4_1)
inst_0:
// rs2 == rd and rs2 != 0, rd==x13, rs2==x13, rs2_val == (-2**(xlen-1)), rs2_val == -2147483648
// opcode: c.mv; op2:x13; dest:x13; op2val:-0x80000000
TEST_CMV_OP( c.mv, x13, x13, -0x80000000, -0x80000000, x4, 0, x10)
inst_1:
// rs2 != rd and rs2 != 0, rd==x3, rs2==x14, rs2_val == 2147483647, rs2_val == (2**(xlen-1)-1)
// opcode: c.mv; op2:x14; dest:x3; op2val:0x7fffffff
TEST_CMV_OP( c.mv, x3, x14, 0x7fffffff, 0x7fffffff, x4, 4, x10)
inst_2:
// rd==x15, rs2==x5, rs2_val == -1073741825,
// opcode: c.mv; op2:x5; dest:x15; op2val:-0x40000001
TEST_CMV_OP( c.mv, x15, x5, -0x40000001, -0x40000001, x4, 8, x10)
inst_3:
// rd==x6, rs2==x2, rs2_val == -536870913,
// opcode: c.mv; op2:x2; dest:x6; op2val:-0x20000001
TEST_CMV_OP( c.mv, x6, x2, -0x20000001, -0x20000001, x4, 12, x10)
inst_4:
// rd==x9, rs2==x7, rs2_val == -268435457,
// opcode: c.mv; op2:x7; dest:x9; op2val:-0x10000001
TEST_CMV_OP( c.mv, x9, x7, -0x10000001, -0x10000001, x4, 16, x10)
inst_5:
// rd==x2, rs2==x11, rs2_val == -134217729,
// opcode: c.mv; op2:x11; dest:x2; op2val:-0x8000001
TEST_CMV_OP( c.mv, x2, x11, -0x8000001, -0x8000001, x4, 20, x10)
inst_6:
// rd==x5, rs2==x15, rs2_val == -67108865,
// opcode: c.mv; op2:x15; dest:x5; op2val:-0x4000001
TEST_CMV_OP( c.mv, x5, x15, -0x4000001, -0x4000001, x4, 24, x10)
inst_7:
// rd==x11, rs2==x9, rs2_val == -33554433,
// opcode: c.mv; op2:x9; dest:x11; op2val:-0x2000001
TEST_CMV_OP( c.mv, x11, x9, -0x2000001, -0x2000001, x4, 28, x10)
inst_8:
// rd==x1, rs2==x8, rs2_val == -16777217,
// opcode: c.mv; op2:x8; dest:x1; op2val:-0x1000001
TEST_CMV_OP( c.mv, x1, x8, -0x1000001, -0x1000001, x4, 32, x10)
RVTEST_SIGBASE( x2,signature_x2_0)
inst_9:
// rd==x7, rs2==x6, rs2_val == -8388609,
// opcode: c.mv; op2:x6; dest:x7; op2val:-0x800001
TEST_CMV_OP( c.mv, x7, x6, -0x800001, -0x800001, x2, 0, x5)
inst_10:
// rd==x12, rs2==x1, rs2_val == -4194305,
// opcode: c.mv; op2:x1; dest:x12; op2val:-0x400001
TEST_CMV_OP( c.mv, x12, x1, -0x400001, -0x400001, x2, 4, x5)
inst_11:
// rd==x14, rs2==x4, rs2_val == -2097153,
// opcode: c.mv; op2:x4; dest:x14; op2val:-0x200001
TEST_CMV_OP( c.mv, x14, x4, -0x200001, -0x200001, x2, 8, x5)
inst_12:
// rd==x10, rs2==x12, rs2_val == -1048577,
// opcode: c.mv; op2:x12; dest:x10; op2val:-0x100001
TEST_CMV_OP( c.mv, x10, x12, -0x100001, -0x100001, x2, 12, x5)
inst_13:
// rd==x8, rs2==x3, rs2_val == -524289,
// opcode: c.mv; op2:x3; dest:x8; op2val:-0x80001
TEST_CMV_OP( c.mv, x8, x3, -0x80001, -0x80001, x2, 16, x5)
inst_14:
// rd==x0, rs2==x10, rs2_val == -262145,
// opcode: c.mv; op2:x10; dest:x0; op2val:-0x40001
TEST_CMV_OP( c.mv, x0, x10, 0, -0x40001, x2, 20, x5)
inst_15:
// rd==x4, rs2_val == -131073,
// opcode: c.mv; op2:x12; dest:x4; op2val:-0x20001
TEST_CMV_OP( c.mv, x4, x12, -0x20001, -0x20001, x2, 24, x5)
inst_16:
// rs2_val == -65537,
// opcode: c.mv; op2:x11; dest:x10; op2val:-0x10001
TEST_CMV_OP( c.mv, x10, x11, -0x10001, -0x10001, x2, 28, x5)
inst_17:
// rs2_val == -32769,
// opcode: c.mv; op2:x11; dest:x10; op2val:-0x8001
TEST_CMV_OP( c.mv, x10, x11, -0x8001, -0x8001, x2, 32, x5)
inst_18:
// rs2_val == -16385,
// opcode: c.mv; op2:x11; dest:x10; op2val:-0x4001
TEST_CMV_OP( c.mv, x10, x11, -0x4001, -0x4001, x2, 36, x5)
inst_19:
// rs2_val == -8193,
// opcode: c.mv; op2:x11; dest:x10; op2val:-0x2001
TEST_CMV_OP( c.mv, x10, x11, -0x2001, -0x2001, x2, 40, x5)
inst_20:
// rs2_val == -4097,
// opcode: c.mv; op2:x11; dest:x10; op2val:-0x1001
TEST_CMV_OP( c.mv, x10, x11, -0x1001, -0x1001, x2, 44, x5)
inst_21:
// rs2_val == -2049,
// opcode: c.mv; op2:x11; dest:x10; op2val:-0x801
TEST_CMV_OP( c.mv, x10, x11, -0x801, -0x801, x2, 48, x5)
inst_22:
// rs2_val == -1025,
// opcode: c.mv; op2:x11; dest:x10; op2val:-0x401
TEST_CMV_OP( c.mv, x10, x11, -0x401, -0x401, x2, 52, x5)
inst_23:
// rs2_val == -513,
// opcode: c.mv; op2:x11; dest:x10; op2val:-0x201
TEST_CMV_OP( c.mv, x10, x11, -0x201, -0x201, x2, 56, x5)
inst_24:
// rs2_val == -257,
// opcode: c.mv; op2:x11; dest:x10; op2val:-0x101
TEST_CMV_OP( c.mv, x10, x11, -0x101, -0x101, x2, 60, x5)
inst_25:
// rs2_val == -129,
// opcode: c.mv; op2:x11; dest:x10; op2val:-0x81
TEST_CMV_OP( c.mv, x10, x11, -0x81, -0x81, x2, 64, x5)
inst_26:
// rs2_val == -65,
// opcode: c.mv; op2:x11; dest:x10; op2val:-0x41
TEST_CMV_OP( c.mv, x10, x11, -0x41, -0x41, x2, 68, x5)
inst_27:
// rs2_val == -33,
// opcode: c.mv; op2:x11; dest:x10; op2val:-0x21
TEST_CMV_OP( c.mv, x10, x11, -0x21, -0x21, x2, 72, x5)
inst_28:
// rs2_val == -17,
// opcode: c.mv; op2:x11; dest:x10; op2val:-0x11
TEST_CMV_OP( c.mv, x10, x11, -0x11, -0x11, x2, 76, x5)
inst_29:
// rs2_val == -9,
// opcode: c.mv; op2:x11; dest:x10; op2val:-0x9
TEST_CMV_OP( c.mv, x10, x11, -0x9, -0x9, x2, 80, x5)
inst_30:
// rs2_val == -5,
// opcode: c.mv; op2:x11; dest:x10; op2val:-0x5
TEST_CMV_OP( c.mv, x10, x11, -0x5, -0x5, x2, 84, x5)
inst_31:
// rs2_val == -3,
// opcode: c.mv; op2:x11; dest:x10; op2val:-0x3
TEST_CMV_OP( c.mv, x10, x11, -0x3, -0x3, x2, 88, x5)
inst_32:
// rs2_val == -2,
// opcode: c.mv; op2:x11; dest:x10; op2val:-0x2
TEST_CMV_OP( c.mv, x10, x11, -0x2, -0x2, x2, 92, x5)
inst_33:
// rs2_val == 1073741824,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x40000000
TEST_CMV_OP( c.mv, x10, x11, 0x40000000, 0x40000000, x2, 96, x5)
inst_34:
// rs2_val == 536870912,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x20000000
TEST_CMV_OP( c.mv, x10, x11, 0x20000000, 0x20000000, x2, 100, x5)
inst_35:
// rs2_val == 268435456,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x10000000
TEST_CMV_OP( c.mv, x10, x11, 0x10000000, 0x10000000, x2, 104, x5)
inst_36:
// rs2_val == 134217728,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x8000000
TEST_CMV_OP( c.mv, x10, x11, 0x8000000, 0x8000000, x2, 108, x5)
inst_37:
// rs2_val == 67108864,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x4000000
TEST_CMV_OP( c.mv, x10, x11, 0x4000000, 0x4000000, x2, 112, x5)
inst_38:
// rs2_val == 33554432,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x2000000
TEST_CMV_OP( c.mv, x10, x11, 0x2000000, 0x2000000, x2, 116, x5)
inst_39:
// rs2_val == 16777216,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x1000000
TEST_CMV_OP( c.mv, x10, x11, 0x1000000, 0x1000000, x2, 120, x5)
inst_40:
// rs2_val == 8388608,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x800000
TEST_CMV_OP( c.mv, x10, x11, 0x800000, 0x800000, x2, 124, x5)
inst_41:
// rs2_val == 4194304,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x400000
TEST_CMV_OP( c.mv, x10, x11, 0x400000, 0x400000, x2, 128, x5)
inst_42:
// rs2_val == 2097152,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x200000
TEST_CMV_OP( c.mv, x10, x11, 0x200000, 0x200000, x2, 132, x5)
inst_43:
// rs2_val == 1048576,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x100000
TEST_CMV_OP( c.mv, x10, x11, 0x100000, 0x100000, x2, 136, x5)
inst_44:
// rs2_val == 524288,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x80000
TEST_CMV_OP( c.mv, x10, x11, 0x80000, 0x80000, x2, 140, x5)
inst_45:
// rs2_val == 262144,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x40000
TEST_CMV_OP( c.mv, x10, x11, 0x40000, 0x40000, x2, 144, x5)
inst_46:
// rs2_val == 131072,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x20000
TEST_CMV_OP( c.mv, x10, x11, 0x20000, 0x20000, x2, 148, x5)
inst_47:
// rs2_val == 65536,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x10000
TEST_CMV_OP( c.mv, x10, x11, 0x10000, 0x10000, x2, 152, x5)
inst_48:
// rs2_val == 32768,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x8000
TEST_CMV_OP( c.mv, x10, x11, 0x8000, 0x8000, x2, 156, x5)
inst_49:
// rs2_val == 16384,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x4000
TEST_CMV_OP( c.mv, x10, x11, 0x4000, 0x4000, x2, 160, x5)
inst_50:
// rs2_val == 8192,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x2000
TEST_CMV_OP( c.mv, x10, x11, 0x2000, 0x2000, x2, 164, x5)
inst_51:
// rs2_val == 4096,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x1000
TEST_CMV_OP( c.mv, x10, x11, 0x1000, 0x1000, x2, 168, x5)
inst_52:
// rs2_val == 2048,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x800
TEST_CMV_OP( c.mv, x10, x11, 0x800, 0x800, x2, 172, x5)
inst_53:
// rs2_val == 1024,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x400
TEST_CMV_OP( c.mv, x10, x11, 0x400, 0x400, x2, 176, x5)
inst_54:
// rs2_val == 512,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x200
TEST_CMV_OP( c.mv, x10, x11, 0x200, 0x200, x2, 180, x5)
inst_55:
// rs2_val == 256,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x100
TEST_CMV_OP( c.mv, x10, x11, 0x100, 0x100, x2, 184, x5)
inst_56:
// rs2_val == 128,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x80
TEST_CMV_OP( c.mv, x10, x11, 0x80, 0x80, x2, 188, x5)
inst_57:
// rs2_val == 64,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x40
TEST_CMV_OP( c.mv, x10, x11, 0x40, 0x40, x2, 192, x5)
inst_58:
// rs2_val == 1,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x1
TEST_CMV_OP( c.mv, x10, x11, 0x1, 0x1, x2, 196, x5)
inst_59:
// rs2_val==46341,
// opcode: c.mv; op2:x11; dest:x10; op2val:0xb505
TEST_CMV_OP( c.mv, x10, x11, 0xb505, 0xb505, x2, 200, x5)
inst_60:
// rs2_val==-46339,
// opcode: c.mv; op2:x11; dest:x10; op2val:-0xb503
TEST_CMV_OP( c.mv, x10, x11, -0xb503, -0xb503, x2, 204, x5)
inst_61:
// rs2_val==1717986919,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x66666667
TEST_CMV_OP( c.mv, x10, x11, 0x66666667, 0x66666667, x2, 208, x5)
inst_62:
// rs2_val==858993460,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x33333334
TEST_CMV_OP( c.mv, x10, x11, 0x33333334, 0x33333334, x2, 212, x5)
inst_63:
// rs2_val==6,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x6
TEST_CMV_OP( c.mv, x10, x11, 0x6, 0x6, x2, 216, x5)
inst_64:
// rs2_val==-1431655765,
// opcode: c.mv; op2:x11; dest:x10; op2val:-0x55555555
TEST_CMV_OP( c.mv, x10, x11, -0x55555555, -0x55555555, x2, 220, x5)
inst_65:
// rs2_val==1431655766,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x55555556
TEST_CMV_OP( c.mv, x10, x11, 0x55555556, 0x55555556, x2, 224, x5)
inst_66:
// rs2_val==4, rs2_val == 4
// opcode: c.mv; op2:x11; dest:x10; op2val:0x4
TEST_CMV_OP( c.mv, x10, x11, 0x4, 0x4, x2, 228, x5)
inst_67:
// rs2_val==46339,
// opcode: c.mv; op2:x11; dest:x10; op2val:0xb503
TEST_CMV_OP( c.mv, x10, x11, 0xb503, 0xb503, x2, 232, x5)
inst_68:
// rs2_val==0, rs2_val == 0
// opcode: c.mv; op2:x11; dest:x10; op2val:0x0
TEST_CMV_OP( c.mv, x10, x11, 0x0, 0x0, x2, 236, x5)
inst_69:
// rs2_val==1717986917,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x66666665
TEST_CMV_OP( c.mv, x10, x11, 0x66666665, 0x66666665, x2, 240, x5)
inst_70:
// rs2_val==858993458,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x33333332
TEST_CMV_OP( c.mv, x10, x11, 0x33333332, 0x33333332, x2, 244, x5)
inst_71:
// rs2_val==1431655764,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x55555554
TEST_CMV_OP( c.mv, x10, x11, 0x55555554, 0x55555554, x2, 248, x5)
inst_72:
// rs2_val==2, rs2_val == 2
// opcode: c.mv; op2:x11; dest:x10; op2val:0x2
TEST_CMV_OP( c.mv, x10, x11, 0x2, 0x2, x2, 252, x5)
inst_73:
// rs2_val==46340,
// opcode: c.mv; op2:x11; dest:x10; op2val:0xb504
TEST_CMV_OP( c.mv, x10, x11, 0xb504, 0xb504, x2, 256, x5)
inst_74:
// rs2_val==-46340,
// opcode: c.mv; op2:x11; dest:x10; op2val:-0xb504
TEST_CMV_OP( c.mv, x10, x11, -0xb504, -0xb504, x2, 260, x5)
inst_75:
// rs2_val==1717986918,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x66666666
TEST_CMV_OP( c.mv, x10, x11, 0x66666666, 0x66666666, x2, 264, x5)
inst_76:
// rs2_val==858993459,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x33333333
TEST_CMV_OP( c.mv, x10, x11, 0x33333333, 0x33333333, x2, 268, x5)
inst_77:
// rs2_val==5,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x5
TEST_CMV_OP( c.mv, x10, x11, 0x5, 0x5, x2, 272, x5)
inst_78:
// rs2_val==-1431655766, rs2_val == -1431655766
// opcode: c.mv; op2:x11; dest:x10; op2val:-0x55555556
TEST_CMV_OP( c.mv, x10, x11, -0x55555556, -0x55555556, x2, 276, x5)
inst_79:
// rs2_val==1431655765, rs2_val == 1431655765
// opcode: c.mv; op2:x11; dest:x10; op2val:0x55555555
TEST_CMV_OP( c.mv, x10, x11, 0x55555555, 0x55555555, x2, 280, x5)
inst_80:
// rs2_val == 32,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x20
TEST_CMV_OP( c.mv, x10, x11, 0x20, 0x20, x2, 284, x5)
inst_81:
// rs2_val == 16,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x10
TEST_CMV_OP( c.mv, x10, x11, 0x10, 0x10, x2, 288, x5)
inst_82:
// rs2_val == 8,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x8
TEST_CMV_OP( c.mv, x10, x11, 0x8, 0x8, x2, 292, x5)
inst_83:
// rs2_val==3,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x3
TEST_CMV_OP( c.mv, x10, x11, 0x3, 0x3, x2, 296, x5)
inst_84:
// rs2_val == -262145,
// opcode: c.mv; op2:x11; dest:x10; op2val:-0x40001
TEST_CMV_OP( c.mv, x10, x11, -0x40001, -0x40001, x2, 300, x5)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
signature_x4_0:
.fill 0*(XLEN/32),4,0xdeadbeef
signature_x4_1:
.fill 9*(XLEN/32),4,0xdeadbeef
signature_x2_0:
.fill 76*(XLEN/32),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
RVMODEL_DATA_END

140
tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/cnop-01.S
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@ -1,140 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version : 0.5.1
// timestamp : Wed Aug 4 06:39:00 2021 GMT
// usage : riscv_ctg \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32ec.cgf \
// --base-isa rv32e \
// --randomize
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the c.nop instruction of the RISC-V C extension for the cnop covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32EC")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",cnop)
RVTEST_SIGBASE( x1,signature_x1_1)
inst_0:
// imm_val == 21,
// opcode:c.nop; immval:0x15
TEST_CNOP_OP(c.nop, x2, 0x15, x1, 0)
inst_1:
// imm_val == 31,
// opcode:c.nop; immval:0x1f
TEST_CNOP_OP(c.nop, x2, 0x1f, x1, 4)
inst_2:
// imm_val == -17,
// opcode:c.nop; immval:-0x11
TEST_CNOP_OP(c.nop, x2, -0x11, x1, 8)
inst_3:
// imm_val == -9,
// opcode:c.nop; immval:-0x9
TEST_CNOP_OP(c.nop, x2, -0x9, x1, 12)
inst_4:
// imm_val == -5,
// opcode:c.nop; immval:-0x5
TEST_CNOP_OP(c.nop, x2, -0x5, x1, 16)
inst_5:
// imm_val == -3,
// opcode:c.nop; immval:-0x3
TEST_CNOP_OP(c.nop, x2, -0x3, x1, 20)
inst_6:
// imm_val == -2,
// opcode:c.nop; immval:-0x2
TEST_CNOP_OP(c.nop, x2, -0x2, x1, 24)
inst_7:
// imm_val == -32,
// opcode:c.nop; immval:-0x20
TEST_CNOP_OP(c.nop, x2, -0x20, x1, 28)
inst_8:
// imm_val == 16,
// opcode:c.nop; immval:0x10
TEST_CNOP_OP(c.nop, x2, 0x10, x1, 32)
inst_9:
// imm_val == 8,
// opcode:c.nop; immval:0x8
TEST_CNOP_OP(c.nop, x2, 0x8, x1, 36)
inst_10:
// imm_val == 4,
// opcode:c.nop; immval:0x4
TEST_CNOP_OP(c.nop, x2, 0x4, x1, 40)
inst_11:
// imm_val == 2,
// opcode:c.nop; immval:0x2
TEST_CNOP_OP(c.nop, x2, 0x2, x1, 44)
inst_12:
// imm_val == 1,
// opcode:c.nop; immval:0x1
TEST_CNOP_OP(c.nop, x2, 0x1, x1, 48)
inst_13:
// imm_val == -22,
// opcode:c.nop; immval:-0x16
TEST_CNOP_OP(c.nop, x2, -0x16, x1, 52)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
signature_x1_0:
.fill 0*(XLEN/32),4,0xdeadbeef
signature_x1_1:
.fill 14*(XLEN/32),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
RVMODEL_DATA_END

2985
tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/cor-01.S
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File diff suppressed because it is too large Load Diff

500
tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/cslli-01.S
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@ -1,500 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version : 0.5.1
// timestamp : Wed Aug 4 06:39:00 2021 GMT
// usage : riscv_ctg \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32ec.cgf \
// --base-isa rv32e \
// --randomize
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the c.slli instruction of the RISC-V C extension for the cslli covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32EC")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",cslli)
RVTEST_SIGBASE( x1,signature_x1_1)
inst_0:
// rd==x11, rs1_val < 0 and imm_val < xlen, rs1_val == -65537, imm_val == 29
// opcode:c.slli; op1:x11; dest:x11 op1val:-0x10001; immval:0x1d
TEST_CI_OP( c.slli, x11, 0xe0000000, -0x10001, 0x1d, x1, 0, x2)
inst_1:
// rd==x8, rs1_val == 2147483647, rs1_val > 0 and imm_val < xlen, rs1_val == (2**(xlen-1)-1) and imm_val != 0 and imm_val < xlen
// opcode:c.slli; op1:x8; dest:x8 op1val:0x7fffffff; immval:0xb
TEST_CI_OP( c.slli, x8, 0xfffff800, 0x7fffffff, 0xb, x1, 4, x2)
inst_2:
// rd==x9, rs1_val == -1073741825,
// opcode:c.slli; op1:x9; dest:x9 op1val:-0x40000001; immval:0xc
TEST_CI_OP( c.slli, x9, 0xfffff000, -0x40000001, 0xc, x1, 8, x2)
inst_3:
// rd==x12, rs1_val == -536870913,
// opcode:c.slli; op1:x12; dest:x12 op1val:-0x20000001; immval:0x7
TEST_CI_OP( c.slli, x12, 0xffffff80, -0x20000001, 0x7, x1, 12, x2)
inst_4:
// rd==x14, rs1_val == -268435457,
// opcode:c.slli; op1:x14; dest:x14 op1val:-0x10000001; immval:0x3
TEST_CI_OP( c.slli, x14, 0x7ffffff8, -0x10000001, 0x3, x1, 16, x2)
inst_5:
// rd==x10, rs1_val == -134217729,
// opcode:c.slli; op1:x10; dest:x10 op1val:-0x8000001; immval:0x1f
TEST_CI_OP( c.slli, x10, 0x80000000, -0x8000001, 0x1f, x1, 20, x2)
inst_6:
// rd==x13, rs1_val == -67108865,
// opcode:c.slli; op1:x13; dest:x13 op1val:-0x4000001; immval:0x13
TEST_CI_OP( c.slli, x13, 0xfff80000, -0x4000001, 0x13, x1, 24, x2)
inst_7:
// rd==x15, rs1_val == -33554433, imm_val == 10
// opcode:c.slli; op1:x15; dest:x15 op1val:-0x2000001; immval:0xa
TEST_CI_OP( c.slli, x15, 0xfffffc00, -0x2000001, 0xa, x1, 28, x2)
inst_8:
// rs1_val == -16777217,
// opcode:c.slli; op1:x10; dest:x10 op1val:-0x1000001; immval:0x5
TEST_CI_OP( c.slli, x10, 0xdfffffe0, -0x1000001, 0x5, x1, 32, x2)
inst_9:
// rs1_val == -8388609,
// opcode:c.slli; op1:x10; dest:x10 op1val:-0x800001; immval:0x1f
TEST_CI_OP( c.slli, x10, 0x80000000, -0x800001, 0x1f, x1, 36, x2)
inst_10:
// rs1_val == -4194305,
// opcode:c.slli; op1:x10; dest:x10 op1val:-0x400001; immval:0x13
TEST_CI_OP( c.slli, x10, 0xfff80000, -0x400001, 0x13, x1, 40, x2)
inst_11:
// rs1_val == -2097153,
// opcode:c.slli; op1:x10; dest:x10 op1val:-0x200001; immval:0x11
TEST_CI_OP( c.slli, x10, 0xfffe0000, -0x200001, 0x11, x1, 44, x2)
inst_12:
// rs1_val == -1048577,
// opcode:c.slli; op1:x10; dest:x10 op1val:-0x100001; immval:0x9
TEST_CI_OP( c.slli, x10, 0xdffffe00, -0x100001, 0x9, x1, 48, x2)
inst_13:
// rs1_val == -524289, imm_val == 21
// opcode:c.slli; op1:x10; dest:x10 op1val:-0x80001; immval:0x15
TEST_CI_OP( c.slli, x10, 0xffe00000, -0x80001, 0x15, x1, 52, x2)
inst_14:
// rs1_val == -262145, imm_val == 27
// opcode:c.slli; op1:x10; dest:x10 op1val:-0x40001; immval:0x1b
TEST_CI_OP( c.slli, x10, 0xf8000000, -0x40001, 0x1b, x1, 56, x2)
inst_15:
// rs1_val == -131073, imm_val == 2
// opcode:c.slli; op1:x10; dest:x10 op1val:-0x20001; immval:0x2
TEST_CI_OP( c.slli, x10, 0xfff7fffc, -0x20001, 0x2, x1, 60, x2)
inst_16:
// rs1_val == -32769,
// opcode:c.slli; op1:x10; dest:x10 op1val:-0x8001; immval:0x1f
TEST_CI_OP( c.slli, x10, 0x80000000, -0x8001, 0x1f, x1, 64, x2)
inst_17:
// rs1_val == -16385,
// opcode:c.slli; op1:x10; dest:x10 op1val:-0x4001; immval:0xd
TEST_CI_OP( c.slli, x10, 0xf7ffe000, -0x4001, 0xd, x1, 68, x2)
inst_18:
// rs1_val == -8193,
// opcode:c.slli; op1:x10; dest:x10 op1val:-0x2001; immval:0x1d
TEST_CI_OP( c.slli, x10, 0xe0000000, -0x2001, 0x1d, x1, 72, x2)
inst_19:
// rs1_val == -4097,
// opcode:c.slli; op1:x10; dest:x10 op1val:-0x1001; immval:0x1b
TEST_CI_OP( c.slli, x10, 0xf8000000, -0x1001, 0x1b, x1, 76, x2)
inst_20:
// rs1_val == -2049, imm_val == 15
// opcode:c.slli; op1:x10; dest:x10 op1val:-0x801; immval:0xf
TEST_CI_OP( c.slli, x10, 0xfbff8000, -0x801, 0xf, x1, 80, x2)
inst_21:
// rs1_val == -1025,
// opcode:c.slli; op1:x10; dest:x10 op1val:-0x401; immval:0x1f
TEST_CI_OP( c.slli, x10, 0x80000000, -0x401, 0x1f, x1, 84, x2)
inst_22:
// rs1_val == -513,
// opcode:c.slli; op1:x10; dest:x10 op1val:-0x201; immval:0x5
TEST_CI_OP( c.slli, x10, 0xffffbfe0, -0x201, 0x5, x1, 88, x2)
inst_23:
// rs1_val == -257,
// opcode:c.slli; op1:x10; dest:x10 op1val:-0x101; immval:0x1f
TEST_CI_OP( c.slli, x10, 0x80000000, -0x101, 0x1f, x1, 92, x2)
inst_24:
// rs1_val == -129, imm_val == 30
// opcode:c.slli; op1:x10; dest:x10 op1val:-0x81; immval:0x1e
TEST_CI_OP( c.slli, x10, 0xc0000000, -0x81, 0x1e, x1, 96, x2)
inst_25:
// rs1_val == -65,
// opcode:c.slli; op1:x10; dest:x10 op1val:-0x41; immval:0x3
TEST_CI_OP( c.slli, x10, 0xfffffdf8, -0x41, 0x3, x1, 100, x2)
inst_26:
// rs1_val == -33, imm_val == 23
// opcode:c.slli; op1:x10; dest:x10 op1val:-0x21; immval:0x17
TEST_CI_OP( c.slli, x10, 0xef800000, -0x21, 0x17, x1, 104, x2)
inst_27:
// rs1_val == -17, imm_val == 1
// opcode:c.slli; op1:x10; dest:x10 op1val:-0x11; immval:0x1
TEST_CI_OP( c.slli, x10, 0xffffffde, -0x11, 0x1, x1, 108, x2)
inst_28:
// rs1_val == -9,
// opcode:c.slli; op1:x10; dest:x10 op1val:-0x9; immval:0x1d
TEST_CI_OP( c.slli, x10, 0xe0000000, -0x9, 0x1d, x1, 112, x2)
inst_29:
// rs1_val == -5,
// opcode:c.slli; op1:x10; dest:x10 op1val:-0x5; immval:0x17
TEST_CI_OP( c.slli, x10, 0xfd800000, -0x5, 0x17, x1, 116, x2)
inst_30:
// rs1_val == -3,
// opcode:c.slli; op1:x10; dest:x10 op1val:-0x3; immval:0x1b
TEST_CI_OP( c.slli, x10, 0xe8000000, -0x3, 0x1b, x1, 120, x2)
inst_31:
// rs1_val == -2,
// opcode:c.slli; op1:x10; dest:x10 op1val:-0x2; immval:0x1e
TEST_CI_OP( c.slli, x10, 0x80000000, -0x2, 0x1e, x1, 124, x2)
inst_32:
// rs1_val == -2147483648, rs1_val == (-2**(xlen-1)) and imm_val != 0 and imm_val < xlen
// opcode:c.slli; op1:x10; dest:x10 op1val:-0x80000000; immval:0x1d
TEST_CI_OP( c.slli, x10, 0x0, -0x80000000, 0x1d, x1, 128, x2)
inst_33:
// rs1_val == 1073741824,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x40000000; immval:0x1b
TEST_CI_OP( c.slli, x10, 0x0, 0x40000000, 0x1b, x1, 132, x2)
inst_34:
// rs1_val == 536870912,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x20000000; immval:0x13
TEST_CI_OP( c.slli, x10, 0x0, 0x20000000, 0x13, x1, 136, x2)
inst_35:
// rs1_val == 268435456,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x10000000; immval:0x1e
TEST_CI_OP( c.slli, x10, 0x0, 0x10000000, 0x1e, x1, 140, x2)
inst_36:
// rs1_val == 134217728,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x8000000; immval:0x9
TEST_CI_OP( c.slli, x10, 0x0, 0x8000000, 0x9, x1, 144, x2)
inst_37:
// rs1_val == 67108864,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x4000000; immval:0x2
TEST_CI_OP( c.slli, x10, 0x10000000, 0x4000000, 0x2, x1, 148, x2)
inst_38:
// rs1_val == 33554432,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x2000000; immval:0x5
TEST_CI_OP( c.slli, x10, 0x40000000, 0x2000000, 0x5, x1, 152, x2)
inst_39:
// rs1_val == 16777216,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x1000000; immval:0x5
TEST_CI_OP( c.slli, x10, 0x20000000, 0x1000000, 0x5, x1, 156, x2)
inst_40:
// rs1_val == 8388608,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x800000; immval:0x6
TEST_CI_OP( c.slli, x10, 0x20000000, 0x800000, 0x6, x1, 160, x2)
inst_41:
// rs1_val == 4194304,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x400000; immval:0xe
TEST_CI_OP( c.slli, x10, 0x0, 0x400000, 0xe, x1, 164, x2)
inst_42:
// rs1_val == 2097152,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x200000; immval:0x7
TEST_CI_OP( c.slli, x10, 0x10000000, 0x200000, 0x7, x1, 168, x2)
inst_43:
// rs1_val == 1048576,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x100000; immval:0x1b
TEST_CI_OP( c.slli, x10, 0x0, 0x100000, 0x1b, x1, 172, x2)
inst_44:
// rs1_val == 524288,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x80000; immval:0x13
TEST_CI_OP( c.slli, x10, 0x0, 0x80000, 0x13, x1, 176, x2)
inst_45:
// rs1_val == 262144,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x40000; immval:0x9
TEST_CI_OP( c.slli, x10, 0x8000000, 0x40000, 0x9, x1, 180, x2)
inst_46:
// rs1_val == 131072,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x20000; immval:0x12
TEST_CI_OP( c.slli, x10, 0x0, 0x20000, 0x12, x1, 184, x2)
inst_47:
// rs1_val == 65536,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x10000; immval:0xb
TEST_CI_OP( c.slli, x10, 0x8000000, 0x10000, 0xb, x1, 188, x2)
inst_48:
// rs1_val == 32768,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x8000; immval:0x1
TEST_CI_OP( c.slli, x10, 0x10000, 0x8000, 0x1, x1, 192, x2)
inst_49:
// rs1_val == 16384,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x4000; immval:0x1e
TEST_CI_OP( c.slli, x10, 0x0, 0x4000, 0x1e, x1, 196, x2)
inst_50:
// rs1_val == 8192,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x2000; immval:0x1
TEST_CI_OP( c.slli, x10, 0x4000, 0x2000, 0x1, x1, 200, x2)
inst_51:
// rs1_val == 4096,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x1000; immval:0x9
TEST_CI_OP( c.slli, x10, 0x200000, 0x1000, 0x9, x1, 204, x2)
inst_52:
// rs1_val == 2048,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x800; immval:0x11
TEST_CI_OP( c.slli, x10, 0x10000000, 0x800, 0x11, x1, 208, x2)
inst_53:
// rs1_val == 1024,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x400; immval:0x1d
TEST_CI_OP( c.slli, x10, 0x0, 0x400, 0x1d, x1, 212, x2)
inst_54:
// rs1_val == 512,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x200; immval:0xd
TEST_CI_OP( c.slli, x10, 0x400000, 0x200, 0xd, x1, 216, x2)
inst_55:
// rs1_val == 256,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x100; immval:0x12
TEST_CI_OP( c.slli, x10, 0x4000000, 0x100, 0x12, x1, 220, x2)
inst_56:
// rs1_val == 128,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x80; immval:0x6
TEST_CI_OP( c.slli, x10, 0x2000, 0x80, 0x6, x1, 224, x2)
inst_57:
// rs1_val == 64,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x40; immval:0x9
TEST_CI_OP( c.slli, x10, 0x8000, 0x40, 0x9, x1, 228, x2)
inst_58:
// rs1_val == 32,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x20; immval:0x1b
TEST_CI_OP( c.slli, x10, 0x0, 0x20, 0x1b, x1, 232, x2)
inst_59:
// rs1_val == 16, rs1_val == imm_val and imm_val != 0 and imm_val < xlen, imm_val == 16
// opcode:c.slli; op1:x10; dest:x10 op1val:0x10; immval:0x10
TEST_CI_OP( c.slli, x10, 0x100000, 0x10, 0x10, x1, 236, x2)
inst_60:
// rs1_val == 8,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x8; immval:0x13
TEST_CI_OP( c.slli, x10, 0x400000, 0x8, 0x13, x1, 240, x2)
inst_61:
// rs1_val == 4, rs1_val==4
// opcode:c.slli; op1:x10; dest:x10 op1val:0x4; immval:0x15
TEST_CI_OP( c.slli, x10, 0x800000, 0x4, 0x15, x1, 244, x2)
inst_62:
// rs1_val == 2, rs1_val==2
// opcode:c.slli; op1:x10; dest:x10 op1val:0x2; immval:0x1b
TEST_CI_OP( c.slli, x10, 0x10000000, 0x2, 0x1b, x1, 248, x2)
inst_63:
// rs1_val == 1, rs1_val == 1 and imm_val != 0 and imm_val < xlen
// opcode:c.slli; op1:x10; dest:x10 op1val:0x1; immval:0x13
TEST_CI_OP( c.slli, x10, 0x80000, 0x1, 0x13, x1, 252, x2)
inst_64:
// imm_val == 8,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x400000; immval:0x8
TEST_CI_OP( c.slli, x10, 0x40000000, 0x400000, 0x8, x1, 256, x2)
inst_65:
// imm_val == 4,
// opcode:c.slli; op1:x10; dest:x10 op1val:-0x8001; immval:0x4
TEST_CI_OP( c.slli, x10, 0xfff7fff0, -0x8001, 0x4, x1, 260, x2)
inst_66:
// rs1_val==46341,
// opcode:c.slli; op1:x10; dest:x10 op1val:0xb505; immval:0xf
TEST_CI_OP( c.slli, x10, 0x5a828000, 0xb505, 0xf, x1, 264, x2)
inst_67:
// rs1_val==-46339,
// opcode:c.slli; op1:x10; dest:x10 op1val:-0xb503; immval:0xa
TEST_CI_OP( c.slli, x10, 0xfd2bf400, -0xb503, 0xa, x1, 268, x2)
inst_68:
// rs1_val==1717986919,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x66666667; immval:0x1e
TEST_CI_OP( c.slli, x10, 0xc0000000, 0x66666667, 0x1e, x1, 272, x2)
inst_69:
// rs1_val==858993460,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x33333334; immval:0x4
TEST_CI_OP( c.slli, x10, 0x33333340, 0x33333334, 0x4, x1, 276, x2)
inst_70:
// rs1_val==6,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x6; immval:0x3
TEST_CI_OP( c.slli, x10, 0x30, 0x6, 0x3, x1, 280, x2)
inst_71:
// rs1_val==-1431655765,
// opcode:c.slli; op1:x10; dest:x10 op1val:-0x55555555; immval:0x17
TEST_CI_OP( c.slli, x10, 0x55800000, -0x55555555, 0x17, x1, 284, x2)
inst_72:
// rs1_val==1431655766,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x55555556; immval:0x8
TEST_CI_OP( c.slli, x10, 0x55555600, 0x55555556, 0x8, x1, 288, x2)
inst_73:
// rs1_val==46339,
// opcode:c.slli; op1:x10; dest:x10 op1val:0xb503; immval:0x1b
TEST_CI_OP( c.slli, x10, 0x18000000, 0xb503, 0x1b, x1, 292, x2)
inst_74:
// rs1_val==3,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x3; immval:0x1b
TEST_CI_OP( c.slli, x10, 0x18000000, 0x3, 0x1b, x1, 296, x2)
inst_75:
// rs1_val == -1431655766, rs1_val==-1431655766
// opcode:c.slli; op1:x10; dest:x10 op1val:-0x55555556; immval:0x3
TEST_CI_OP( c.slli, x10, 0x55555550, -0x55555556, 0x3, x1, 300, x2)
inst_76:
// rs1_val == 1431655765, rs1_val==1431655765
// opcode:c.slli; op1:x10; dest:x10 op1val:0x55555555; immval:0x4
TEST_CI_OP( c.slli, x10, 0x55555550, 0x55555555, 0x4, x1, 304, x2)
inst_77:
// rs1_val == 0 and imm_val != 0 and imm_val < xlen, rs1_val==0
// opcode:c.slli; op1:x10; dest:x10 op1val:0x0; immval:0x15
TEST_CI_OP( c.slli, x10, 0x0, 0x0, 0x15, x1, 308, x2)
inst_78:
// rs1_val==1717986917,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x66666665; immval:0x5
TEST_CI_OP( c.slli, x10, 0xcccccca0, 0x66666665, 0x5, x1, 312, x2)
inst_79:
// rs1_val==858993458,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x33333332; immval:0x10
TEST_CI_OP( c.slli, x10, 0x33320000, 0x33333332, 0x10, x1, 316, x2)
inst_80:
// rs1_val==1431655764,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x55555554; immval:0x17
TEST_CI_OP( c.slli, x10, 0xaa000000, 0x55555554, 0x17, x1, 320, x2)
inst_81:
// rs1_val==46340,
// opcode:c.slli; op1:x10; dest:x10 op1val:0xb504; immval:0x6
TEST_CI_OP( c.slli, x10, 0x2d4100, 0xb504, 0x6, x1, 324, x2)
inst_82:
// rs1_val==-46340,
// opcode:c.slli; op1:x10; dest:x10 op1val:-0xb504; immval:0xa
TEST_CI_OP( c.slli, x10, 0xfd2bf000, -0xb504, 0xa, x1, 328, x2)
inst_83:
// rs1_val==1717986918,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x66666666; immval:0x12
TEST_CI_OP( c.slli, x10, 0x99980000, 0x66666666, 0x12, x1, 332, x2)
inst_84:
// rs1_val==858993459,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x33333333; immval:0x1
TEST_CI_OP( c.slli, x10, 0x66666666, 0x33333333, 0x1, x1, 336, x2)
inst_85:
// rs1_val==5,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x5; immval:0x4
TEST_CI_OP( c.slli, x10, 0x50, 0x5, 0x4, x1, 340, x2)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
signature_x1_0:
.fill 0*(XLEN/32),4,0xdeadbeef
signature_x1_1:
.fill 86*(XLEN/32),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
RVMODEL_DATA_END

495
tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/csrai-01.S
View File

@ -1,495 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version : 0.5.1
// timestamp : Wed Aug 4 06:39:00 2021 GMT
// usage : riscv_ctg \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32ec.cgf \
// --base-isa rv32e \
// --randomize
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the c.srai instruction of the RISC-V C extension for the csrai covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32EC")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",csrai)
RVTEST_SIGBASE( x1,signature_x1_1)
inst_0:
// rs1==x10, rs1_val < 0 and imm_val < xlen, rs1_val == -1431655766, rs1_val==-1431655766
// opcode:c.srai; op1:x10; dest:x10 op1val:-0x55555556; immval:0xe
TEST_CI_OP( c.srai, x10, 0xfffeaaaa, -0x55555556, 0xe, x1, 0, x2)
inst_1:
// rs1==x9, rs1_val == 2147483647, rs1_val > 0 and imm_val < xlen, rs1_val == (2**(xlen-1)-1) and imm_val != 0 and imm_val < xlen
// opcode:c.srai; op1:x9; dest:x9 op1val:0x7fffffff; immval:0x9
TEST_CI_OP( c.srai, x9, 0x3fffff, 0x7fffffff, 0x9, x1, 4, x2)
inst_2:
// rs1==x11, rs1_val == -1073741825,
// opcode:c.srai; op1:x11; dest:x11 op1val:-0x40000001; immval:0x5
TEST_CI_OP( c.srai, x11, 0xfdffffff, -0x40000001, 0x5, x1, 8, x2)
inst_3:
// rs1==x12, rs1_val == -536870913, imm_val == 4
// opcode:c.srai; op1:x12; dest:x12 op1val:-0x20000001; immval:0x4
TEST_CI_OP( c.srai, x12, 0xfdffffff, -0x20000001, 0x4, x1, 12, x2)
inst_4:
// rs1==x14, rs1_val == -268435457, imm_val == 21
// opcode:c.srai; op1:x14; dest:x14 op1val:-0x10000001; immval:0x15
TEST_CI_OP( c.srai, x14, 0xffffff7f, -0x10000001, 0x15, x1, 16, x2)
inst_5:
// rs1==x8, rs1_val == -134217729,
// opcode:c.srai; op1:x8; dest:x8 op1val:-0x8000001; immval:0x13
TEST_CI_OP( c.srai, x8, 0xfffffeff, -0x8000001, 0x13, x1, 20, x2)
inst_6:
// rs1==x13, rs1_val == -67108865,
// opcode:c.srai; op1:x13; dest:x13 op1val:-0x4000001; immval:0xc
TEST_CI_OP( c.srai, x13, 0xffffbfff, -0x4000001, 0xc, x1, 24, x2)
inst_7:
// rs1==x15, rs1_val == -33554433, imm_val == 29
// opcode:c.srai; op1:x15; dest:x15 op1val:-0x2000001; immval:0x1d
TEST_CI_OP( c.srai, x15, 0xffffffff, -0x2000001, 0x1d, x1, 28, x2)
inst_8:
// rs1_val == -16777217,
// opcode:c.srai; op1:x10; dest:x10 op1val:-0x1000001; immval:0xd
TEST_CI_OP( c.srai, x10, 0xfffff7ff, -0x1000001, 0xd, x1, 32, x2)
inst_9:
// rs1_val == -8388609,
// opcode:c.srai; op1:x10; dest:x10 op1val:-0x800001; immval:0x3
TEST_CI_OP( c.srai, x10, 0xffefffff, -0x800001, 0x3, x1, 36, x2)
inst_10:
// rs1_val == -4194305, imm_val == 10
// opcode:c.srai; op1:x10; dest:x10 op1val:-0x400001; immval:0xa
TEST_CI_OP( c.srai, x10, 0xffffefff, -0x400001, 0xa, x1, 40, x2)
inst_11:
// rs1_val == -2097153,
// opcode:c.srai; op1:x10; dest:x10 op1val:-0x200001; immval:0xd
TEST_CI_OP( c.srai, x10, 0xfffffeff, -0x200001, 0xd, x1, 44, x2)
inst_12:
// rs1_val == -1048577,
// opcode:c.srai; op1:x10; dest:x10 op1val:-0x100001; immval:0xd
TEST_CI_OP( c.srai, x10, 0xffffff7f, -0x100001, 0xd, x1, 48, x2)
inst_13:
// rs1_val == -524289,
// opcode:c.srai; op1:x10; dest:x10 op1val:-0x80001; immval:0x5
TEST_CI_OP( c.srai, x10, 0xffffbfff, -0x80001, 0x5, x1, 52, x2)
inst_14:
// rs1_val == -262145,
// opcode:c.srai; op1:x10; dest:x10 op1val:-0x40001; immval:0x4
TEST_CI_OP( c.srai, x10, 0xffffbfff, -0x40001, 0x4, x1, 56, x2)
inst_15:
// rs1_val == -131073,
// opcode:c.srai; op1:x10; dest:x10 op1val:-0x20001; immval:0x1d
TEST_CI_OP( c.srai, x10, 0xffffffff, -0x20001, 0x1d, x1, 60, x2)
inst_16:
// rs1_val == -65537,
// opcode:c.srai; op1:x10; dest:x10 op1val:-0x10001; immval:0x15
TEST_CI_OP( c.srai, x10, 0xffffffff, -0x10001, 0x15, x1, 64, x2)
inst_17:
// rs1_val == -32769, imm_val == 2
// opcode:c.srai; op1:x10; dest:x10 op1val:-0x8001; immval:0x2
TEST_CI_OP( c.srai, x10, 0xffffdfff, -0x8001, 0x2, x1, 68, x2)
inst_18:
// rs1_val == -16385,
// opcode:c.srai; op1:x10; dest:x10 op1val:-0x4001; immval:0x7
TEST_CI_OP( c.srai, x10, 0xffffff7f, -0x4001, 0x7, x1, 72, x2)
inst_19:
// rs1_val == -8193,
// opcode:c.srai; op1:x10; dest:x10 op1val:-0x2001; immval:0x12
TEST_CI_OP( c.srai, x10, 0xffffffff, -0x2001, 0x12, x1, 76, x2)
inst_20:
// rs1_val == -4097,
// opcode:c.srai; op1:x10; dest:x10 op1val:-0x1001; immval:0x6
TEST_CI_OP( c.srai, x10, 0xffffffbf, -0x1001, 0x6, x1, 80, x2)
inst_21:
// rs1_val == -2049,
// opcode:c.srai; op1:x10; dest:x10 op1val:-0x801; immval:0x13
TEST_CI_OP( c.srai, x10, 0xffffffff, -0x801, 0x13, x1, 84, x2)
inst_22:
// rs1_val == -1025,
// opcode:c.srai; op1:x10; dest:x10 op1val:-0x401; immval:0x3
TEST_CI_OP( c.srai, x10, 0xffffff7f, -0x401, 0x3, x1, 88, x2)
inst_23:
// rs1_val == -513, imm_val == 15
// opcode:c.srai; op1:x10; dest:x10 op1val:-0x201; immval:0xf
TEST_CI_OP( c.srai, x10, 0xffffffff, -0x201, 0xf, x1, 92, x2)
inst_24:
// rs1_val == -257,
// opcode:c.srai; op1:x10; dest:x10 op1val:-0x101; immval:0x7
TEST_CI_OP( c.srai, x10, 0xfffffffd, -0x101, 0x7, x1, 96, x2)
inst_25:
// rs1_val == -129,
// opcode:c.srai; op1:x10; dest:x10 op1val:-0x81; immval:0xa
TEST_CI_OP( c.srai, x10, 0xffffffff, -0x81, 0xa, x1, 100, x2)
inst_26:
// rs1_val == -65, imm_val == 23
// opcode:c.srai; op1:x10; dest:x10 op1val:-0x41; immval:0x17
TEST_CI_OP( c.srai, x10, 0xffffffff, -0x41, 0x17, x1, 104, x2)
inst_27:
// rs1_val == -33, imm_val == 30
// opcode:c.srai; op1:x10; dest:x10 op1val:-0x21; immval:0x1e
TEST_CI_OP( c.srai, x10, 0xffffffff, -0x21, 0x1e, x1, 108, x2)
inst_28:
// rs1_val == -17,
// opcode:c.srai; op1:x10; dest:x10 op1val:-0x11; immval:0x1e
TEST_CI_OP( c.srai, x10, 0xffffffff, -0x11, 0x1e, x1, 112, x2)
inst_29:
// rs1_val == -9,
// opcode:c.srai; op1:x10; dest:x10 op1val:-0x9; immval:0x7
TEST_CI_OP( c.srai, x10, 0xffffffff, -0x9, 0x7, x1, 116, x2)
inst_30:
// rs1_val == -5,
// opcode:c.srai; op1:x10; dest:x10 op1val:-0x5; immval:0x9
TEST_CI_OP( c.srai, x10, 0xffffffff, -0x5, 0x9, x1, 120, x2)
inst_31:
// rs1_val == -3,
// opcode:c.srai; op1:x10; dest:x10 op1val:-0x3; immval:0x13
TEST_CI_OP( c.srai, x10, 0xffffffff, -0x3, 0x13, x1, 124, x2)
inst_32:
// rs1_val == -2,
// opcode:c.srai; op1:x10; dest:x10 op1val:-0x2; immval:0x17
TEST_CI_OP( c.srai, x10, 0xffffffff, -0x2, 0x17, x1, 128, x2)
inst_33:
// imm_val == 27, rs1_val == 32
// opcode:c.srai; op1:x10; dest:x10 op1val:0x20; immval:0x1b
TEST_CI_OP( c.srai, x10, 0x0, 0x20, 0x1b, x1, 132, x2)
inst_34:
// rs1_val == -2147483648, rs1_val == (-2**(xlen-1)) and imm_val != 0 and imm_val < xlen
// opcode:c.srai; op1:x10; dest:x10 op1val:-0x80000000; immval:0x12
TEST_CI_OP( c.srai, x10, 0xffffe000, -0x80000000, 0x12, x1, 136, x2)
inst_35:
// rs1_val == 1073741824,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x40000000; immval:0x11
TEST_CI_OP( c.srai, x10, 0x2000, 0x40000000, 0x11, x1, 140, x2)
inst_36:
// rs1_val == 536870912,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x20000000; immval:0x1b
TEST_CI_OP( c.srai, x10, 0x4, 0x20000000, 0x1b, x1, 144, x2)
inst_37:
// rs1_val == 268435456,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x10000000; immval:0x15
TEST_CI_OP( c.srai, x10, 0x80, 0x10000000, 0x15, x1, 148, x2)
inst_38:
// rs1_val == 134217728,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x8000000; immval:0x12
TEST_CI_OP( c.srai, x10, 0x200, 0x8000000, 0x12, x1, 152, x2)
inst_39:
// rs1_val == 67108864,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x4000000; immval:0x15
TEST_CI_OP( c.srai, x10, 0x20, 0x4000000, 0x15, x1, 156, x2)
inst_40:
// rs1_val == 33554432,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x2000000; immval:0x4
TEST_CI_OP( c.srai, x10, 0x200000, 0x2000000, 0x4, x1, 160, x2)
inst_41:
// rs1_val == 16777216,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x1000000; immval:0x1e
TEST_CI_OP( c.srai, x10, 0x0, 0x1000000, 0x1e, x1, 164, x2)
inst_42:
// rs1_val == 8388608,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x800000; immval:0x1e
TEST_CI_OP( c.srai, x10, 0x0, 0x800000, 0x1e, x1, 168, x2)
inst_43:
// rs1_val == 4194304,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x400000; immval:0xd
TEST_CI_OP( c.srai, x10, 0x200, 0x400000, 0xd, x1, 172, x2)
inst_44:
// rs1_val == 2097152,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x200000; immval:0xd
TEST_CI_OP( c.srai, x10, 0x100, 0x200000, 0xd, x1, 176, x2)
inst_45:
// rs1_val == 1048576,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x100000; immval:0x13
TEST_CI_OP( c.srai, x10, 0x2, 0x100000, 0x13, x1, 180, x2)
inst_46:
// rs1_val == 524288,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x80000; immval:0x9
TEST_CI_OP( c.srai, x10, 0x400, 0x80000, 0x9, x1, 184, x2)
inst_47:
// rs1_val == 262144,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x40000; immval:0x13
TEST_CI_OP( c.srai, x10, 0x0, 0x40000, 0x13, x1, 188, x2)
inst_48:
// rs1_val == 131072,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x20000; immval:0x4
TEST_CI_OP( c.srai, x10, 0x2000, 0x20000, 0x4, x1, 192, x2)
inst_49:
// rs1_val == 65536, imm_val == 8
// opcode:c.srai; op1:x10; dest:x10 op1val:0x10000; immval:0x8
TEST_CI_OP( c.srai, x10, 0x100, 0x10000, 0x8, x1, 196, x2)
inst_50:
// rs1_val == 32768,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x8000; immval:0x5
TEST_CI_OP( c.srai, x10, 0x400, 0x8000, 0x5, x1, 200, x2)
inst_51:
// rs1_val == 16384,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x4000; immval:0x17
TEST_CI_OP( c.srai, x10, 0x0, 0x4000, 0x17, x1, 204, x2)
inst_52:
// rs1_val == 8192,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x2000; immval:0x5
TEST_CI_OP( c.srai, x10, 0x100, 0x2000, 0x5, x1, 208, x2)
inst_53:
// rs1_val == 4096,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x1000; immval:0x17
TEST_CI_OP( c.srai, x10, 0x0, 0x1000, 0x17, x1, 212, x2)
inst_54:
// rs1_val == 2048,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x800; immval:0xa
TEST_CI_OP( c.srai, x10, 0x2, 0x800, 0xa, x1, 216, x2)
inst_55:
// rs1_val == 1024,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x400; immval:0x1e
TEST_CI_OP( c.srai, x10, 0x0, 0x400, 0x1e, x1, 220, x2)
inst_56:
// rs1_val == 512,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x200; immval:0xb
TEST_CI_OP( c.srai, x10, 0x0, 0x200, 0xb, x1, 224, x2)
inst_57:
// rs1_val == 256,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x100; immval:0x1f
TEST_CI_OP( c.srai, x10, 0x0, 0x100, 0x1f, x1, 228, x2)
inst_58:
// rs1_val == 128,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x80; immval:0x3
TEST_CI_OP( c.srai, x10, 0x10, 0x80, 0x3, x1, 232, x2)
inst_59:
// rs1_val == 64,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x40; immval:0x1b
TEST_CI_OP( c.srai, x10, 0x0, 0x40, 0x1b, x1, 236, x2)
inst_60:
// rs1_val == 16,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x10; immval:0x6
TEST_CI_OP( c.srai, x10, 0x0, 0x10, 0x6, x1, 240, x2)
inst_61:
// rs1_val == 8,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x8; immval:0x11
TEST_CI_OP( c.srai, x10, 0x0, 0x8, 0x11, x1, 244, x2)
inst_62:
// rs1_val == 4, rs1_val==4
// opcode:c.srai; op1:x10; dest:x10 op1val:0x4; immval:0x13
TEST_CI_OP( c.srai, x10, 0x0, 0x4, 0x13, x1, 248, x2)
inst_63:
// rs1_val == 2, rs1_val==2
// opcode:c.srai; op1:x10; dest:x10 op1val:0x2; immval:0x4
TEST_CI_OP( c.srai, x10, 0x0, 0x2, 0x4, x1, 252, x2)
inst_64:
// rs1_val == 1, rs1_val == 1 and imm_val != 0 and imm_val < xlen
// opcode:c.srai; op1:x10; dest:x10 op1val:0x1; immval:0x1f
TEST_CI_OP( c.srai, x10, 0x0, 0x1, 0x1f, x1, 256, x2)
inst_65:
// imm_val == 16,
// opcode:c.srai; op1:x10; dest:x10 op1val:-0x801; immval:0x10
TEST_CI_OP( c.srai, x10, 0xffffffff, -0x801, 0x10, x1, 260, x2)
inst_66:
// imm_val == 1, rs1_val == 1431655765, rs1_val==1431655765
// opcode:c.srai; op1:x10; dest:x10 op1val:0x55555555; immval:0x1
TEST_CI_OP( c.srai, x10, 0x2aaaaaaa, 0x55555555, 0x1, x1, 264, x2)
inst_67:
// rs1_val==46341,
// opcode:c.srai; op1:x10; dest:x10 op1val:0xb505; immval:0xd
TEST_CI_OP( c.srai, x10, 0x5, 0xb505, 0xd, x1, 268, x2)
inst_68:
// rs1_val==-46339,
// opcode:c.srai; op1:x10; dest:x10 op1val:-0xb503; immval:0x5
TEST_CI_OP( c.srai, x10, 0xfffffa57, -0xb503, 0x5, x1, 272, x2)
inst_69:
// rs1_val==1717986919,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x66666667; immval:0x15
TEST_CI_OP( c.srai, x10, 0x333, 0x66666667, 0x15, x1, 276, x2)
inst_70:
// rs1_val==858993460,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x33333334; immval:0x17
TEST_CI_OP( c.srai, x10, 0x66, 0x33333334, 0x17, x1, 280, x2)
inst_71:
// rs1_val==6,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x6; immval:0x3
TEST_CI_OP( c.srai, x10, 0x0, 0x6, 0x3, x1, 284, x2)
inst_72:
// rs1_val==3, rs1_val == imm_val and imm_val != 0 and imm_val < xlen
// opcode:c.srai; op1:x10; dest:x10 op1val:0x3; immval:0x3
TEST_CI_OP( c.srai, x10, 0x0, 0x3, 0x3, x1, 288, x2)
inst_73:
// rs1_val == 0 and imm_val != 0 and imm_val < xlen, rs1_val==0
// opcode:c.srai; op1:x10; dest:x10 op1val:0x0; immval:0x12
TEST_CI_OP( c.srai, x10, 0x0, 0x0, 0x12, x1, 292, x2)
inst_74:
// rs1_val==-1431655765,
// opcode:c.srai; op1:x10; dest:x10 op1val:-0x55555555; immval:0x6
TEST_CI_OP( c.srai, x10, 0xfeaaaaaa, -0x55555555, 0x6, x1, 296, x2)
inst_75:
// rs1_val==1431655766,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x55555556; immval:0x11
TEST_CI_OP( c.srai, x10, 0x2aaa, 0x55555556, 0x11, x1, 300, x2)
inst_76:
// rs1_val==46339,
// opcode:c.srai; op1:x10; dest:x10 op1val:0xb503; immval:0xe
TEST_CI_OP( c.srai, x10, 0x2, 0xb503, 0xe, x1, 304, x2)
inst_77:
// rs1_val==1717986917,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x66666665; immval:0x5
TEST_CI_OP( c.srai, x10, 0x3333333, 0x66666665, 0x5, x1, 308, x2)
inst_78:
// rs1_val==858993458,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x33333332; immval:0x8
TEST_CI_OP( c.srai, x10, 0x333333, 0x33333332, 0x8, x1, 312, x2)
inst_79:
// rs1_val==1431655764,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x55555554; immval:0x8
TEST_CI_OP( c.srai, x10, 0x555555, 0x55555554, 0x8, x1, 316, x2)
inst_80:
// rs1_val==46340,
// opcode:c.srai; op1:x10; dest:x10 op1val:0xb504; immval:0x1f
TEST_CI_OP( c.srai, x10, 0x0, 0xb504, 0x1f, x1, 320, x2)
inst_81:
// rs1_val==-46340,
// opcode:c.srai; op1:x10; dest:x10 op1val:-0xb504; immval:0x8
TEST_CI_OP( c.srai, x10, 0xffffff4a, -0xb504, 0x8, x1, 324, x2)
inst_82:
// rs1_val==1717986918,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x66666666; immval:0xd
TEST_CI_OP( c.srai, x10, 0x33333, 0x66666666, 0xd, x1, 328, x2)
inst_83:
// rs1_val==858993459,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x33333333; immval:0x17
TEST_CI_OP( c.srai, x10, 0x66, 0x33333333, 0x17, x1, 332, x2)
inst_84:
// rs1_val==5,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x5; immval:0x1
TEST_CI_OP( c.srai, x10, 0x2, 0x5, 0x1, x1, 336, x2)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
signature_x1_0:
.fill 0*(XLEN/32),4,0xdeadbeef
signature_x1_1:
.fill 85*(XLEN/32),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
RVMODEL_DATA_END

505
tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/csrli-01.S
View File

@ -1,505 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version : 0.5.1
// timestamp : Wed Aug 4 06:39:00 2021 GMT
// usage : riscv_ctg \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32ec.cgf \
// --base-isa rv32e \
// --randomize
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the c.srli instruction of the RISC-V C extension for the csrli covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32EC")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",csrli)
RVTEST_SIGBASE( x1,signature_x1_1)
inst_0:
// rs1==x15, rs1_val < 0 and imm_val < xlen, rs1_val == -2
// opcode:c.srli; op1:x15; dest:x15 op1val:-0x2; immval:0xe
TEST_CI_OP( c.srli, x15, 0x3ffff, -0x2, 0xe, x1, 0, x2)
inst_1:
// rs1==x8, rs1_val == 2147483647, rs1_val > 0 and imm_val < xlen, rs1_val == (2**(xlen-1)-1) and imm_val != 0 and imm_val < xlen
// opcode:c.srli; op1:x8; dest:x8 op1val:0x7fffffff; immval:0x7
TEST_CI_OP( c.srli, x8, 0xffffff, 0x7fffffff, 0x7, x1, 4, x2)
inst_2:
// rs1==x11, rs1_val == -1073741825, imm_val == 15
// opcode:c.srli; op1:x11; dest:x11 op1val:-0x40000001; immval:0xf
TEST_CI_OP( c.srli, x11, 0x17fff, -0x40000001, 0xf, x1, 8, x2)
inst_3:
// rs1==x10, rs1_val == -536870913,
// opcode:c.srli; op1:x10; dest:x10 op1val:-0x20000001; immval:0xb
TEST_CI_OP( c.srli, x10, 0x1bffff, -0x20000001, 0xb, x1, 12, x2)
inst_4:
// rs1==x9, rs1_val == -268435457,
// opcode:c.srli; op1:x9; dest:x9 op1val:-0x10000001; immval:0xc
TEST_CI_OP( c.srli, x9, 0xeffff, -0x10000001, 0xc, x1, 16, x2)
inst_5:
// rs1==x13, rs1_val == -134217729, imm_val == 4
// opcode:c.srli; op1:x13; dest:x13 op1val:-0x8000001; immval:0x4
TEST_CI_OP( c.srli, x13, 0xf7fffff, -0x8000001, 0x4, x1, 20, x2)
inst_6:
// rs1==x12, rs1_val == -67108865,
// opcode:c.srli; op1:x12; dest:x12 op1val:-0x4000001; immval:0x3
TEST_CI_OP( c.srli, x12, 0x1f7fffff, -0x4000001, 0x3, x1, 24, x2)
inst_7:
// rs1==x14, rs1_val == -33554433,
// opcode:c.srli; op1:x14; dest:x14 op1val:-0x2000001; immval:0x11
TEST_CI_OP( c.srli, x14, 0x7eff, -0x2000001, 0x11, x1, 28, x2)
inst_8:
// rs1_val == -16777217,
// opcode:c.srli; op1:x10; dest:x10 op1val:-0x1000001; immval:0x6
TEST_CI_OP( c.srli, x10, 0x3fbffff, -0x1000001, 0x6, x1, 32, x2)
inst_9:
// rs1_val == -8388609,
// opcode:c.srli; op1:x10; dest:x10 op1val:-0x800001; immval:0xf
TEST_CI_OP( c.srli, x10, 0x1feff, -0x800001, 0xf, x1, 36, x2)
inst_10:
// rs1_val == -4194305, imm_val == 21
// opcode:c.srli; op1:x10; dest:x10 op1val:-0x400001; immval:0x15
TEST_CI_OP( c.srli, x10, 0x7fd, -0x400001, 0x15, x1, 40, x2)
inst_11:
// rs1_val == -2097153,
// opcode:c.srli; op1:x10; dest:x10 op1val:-0x200001; immval:0x3
TEST_CI_OP( c.srli, x10, 0x1ffbffff, -0x200001, 0x3, x1, 44, x2)
inst_12:
// rs1_val == -1048577, imm_val == 2
// opcode:c.srli; op1:x10; dest:x10 op1val:-0x100001; immval:0x2
TEST_CI_OP( c.srli, x10, 0x3ffbffff, -0x100001, 0x2, x1, 48, x2)
inst_13:
// rs1_val == -524289, imm_val == 16
// opcode:c.srli; op1:x10; dest:x10 op1val:-0x80001; immval:0x10
TEST_CI_OP( c.srli, x10, 0xfff7, -0x80001, 0x10, x1, 52, x2)
inst_14:
// rs1_val == -262145,
// opcode:c.srli; op1:x10; dest:x10 op1val:-0x40001; immval:0x6
TEST_CI_OP( c.srli, x10, 0x3ffefff, -0x40001, 0x6, x1, 56, x2)
inst_15:
// rs1_val == -131073,
// opcode:c.srli; op1:x10; dest:x10 op1val:-0x20001; immval:0x10
TEST_CI_OP( c.srli, x10, 0xfffd, -0x20001, 0x10, x1, 60, x2)
inst_16:
// rs1_val == -65537,
// opcode:c.srli; op1:x10; dest:x10 op1val:-0x10001; immval:0x9
TEST_CI_OP( c.srli, x10, 0x7fff7f, -0x10001, 0x9, x1, 64, x2)
inst_17:
// rs1_val == -32769,
// opcode:c.srli; op1:x10; dest:x10 op1val:-0x8001; immval:0x9
TEST_CI_OP( c.srli, x10, 0x7fffbf, -0x8001, 0x9, x1, 68, x2)
inst_18:
// rs1_val == -16385,
// opcode:c.srli; op1:x10; dest:x10 op1val:-0x4001; immval:0xc
TEST_CI_OP( c.srli, x10, 0xffffb, -0x4001, 0xc, x1, 72, x2)
inst_19:
// rs1_val == -8193,
// opcode:c.srli; op1:x10; dest:x10 op1val:-0x2001; immval:0xe
TEST_CI_OP( c.srli, x10, 0x3ffff, -0x2001, 0xe, x1, 76, x2)
inst_20:
// rs1_val == -4097,
// opcode:c.srli; op1:x10; dest:x10 op1val:-0x1001; immval:0x5
TEST_CI_OP( c.srli, x10, 0x7ffff7f, -0x1001, 0x5, x1, 80, x2)
inst_21:
// rs1_val == -2049,
// opcode:c.srli; op1:x10; dest:x10 op1val:-0x801; immval:0x15
TEST_CI_OP( c.srli, x10, 0x7ff, -0x801, 0x15, x1, 84, x2)
inst_22:
// rs1_val == -1025, imm_val == 29
// opcode:c.srli; op1:x10; dest:x10 op1val:-0x401; immval:0x1d
TEST_CI_OP( c.srli, x10, 0x7, -0x401, 0x1d, x1, 88, x2)
inst_23:
// rs1_val == -513,
// opcode:c.srli; op1:x10; dest:x10 op1val:-0x201; immval:0xc
TEST_CI_OP( c.srli, x10, 0xfffff, -0x201, 0xc, x1, 92, x2)
inst_24:
// rs1_val == -257,
// opcode:c.srli; op1:x10; dest:x10 op1val:-0x101; immval:0xc
TEST_CI_OP( c.srli, x10, 0xfffff, -0x101, 0xc, x1, 96, x2)
inst_25:
// rs1_val == -129,
// opcode:c.srli; op1:x10; dest:x10 op1val:-0x81; immval:0x7
TEST_CI_OP( c.srli, x10, 0x1fffffe, -0x81, 0x7, x1, 100, x2)
inst_26:
// rs1_val == -65,
// opcode:c.srli; op1:x10; dest:x10 op1val:-0x41; immval:0x1d
TEST_CI_OP( c.srli, x10, 0x7, -0x41, 0x1d, x1, 104, x2)
inst_27:
// rs1_val == -33,
// opcode:c.srli; op1:x10; dest:x10 op1val:-0x21; immval:0xf
TEST_CI_OP( c.srli, x10, 0x1ffff, -0x21, 0xf, x1, 108, x2)
inst_28:
// rs1_val == -17,
// opcode:c.srli; op1:x10; dest:x10 op1val:-0x11; immval:0xc
TEST_CI_OP( c.srli, x10, 0xfffff, -0x11, 0xc, x1, 112, x2)
inst_29:
// rs1_val == -9,
// opcode:c.srli; op1:x10; dest:x10 op1val:-0x9; immval:0x7
TEST_CI_OP( c.srli, x10, 0x1ffffff, -0x9, 0x7, x1, 116, x2)
inst_30:
// rs1_val == -5, imm_val == 30
// opcode:c.srli; op1:x10; dest:x10 op1val:-0x5; immval:0x1e
TEST_CI_OP( c.srli, x10, 0x3, -0x5, 0x1e, x1, 120, x2)
inst_31:
// rs1_val == -3,
// opcode:c.srli; op1:x10; dest:x10 op1val:-0x3; immval:0xb
TEST_CI_OP( c.srli, x10, 0x1fffff, -0x3, 0xb, x1, 124, x2)
inst_32:
// imm_val == 23, rs1_val==5
// opcode:c.srli; op1:x10; dest:x10 op1val:0x5; immval:0x17
TEST_CI_OP( c.srli, x10, 0x0, 0x5, 0x17, x1, 128, x2)
inst_33:
// imm_val == 27,
// opcode:c.srli; op1:x10; dest:x10 op1val:-0x81; immval:0x1b
TEST_CI_OP( c.srli, x10, 0x1f, -0x81, 0x1b, x1, 132, x2)
inst_34:
// rs1_val == -2147483648, rs1_val == (-2**(xlen-1)) and imm_val != 0 and imm_val < xlen
// opcode:c.srli; op1:x10; dest:x10 op1val:-0x80000000; immval:0x9
TEST_CI_OP( c.srli, x10, 0x400000, -0x80000000, 0x9, x1, 136, x2)
inst_35:
// rs1_val == 1073741824,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x40000000; immval:0x7
TEST_CI_OP( c.srli, x10, 0x800000, 0x40000000, 0x7, x1, 140, x2)
inst_36:
// rs1_val == 536870912,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x20000000; immval:0x6
TEST_CI_OP( c.srli, x10, 0x800000, 0x20000000, 0x6, x1, 144, x2)
inst_37:
// rs1_val == 268435456,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x10000000; immval:0x9
TEST_CI_OP( c.srli, x10, 0x80000, 0x10000000, 0x9, x1, 148, x2)
inst_38:
// rs1_val == 134217728,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x8000000; immval:0x1e
TEST_CI_OP( c.srli, x10, 0x0, 0x8000000, 0x1e, x1, 152, x2)
inst_39:
// rs1_val == 67108864,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x4000000; immval:0x11
TEST_CI_OP( c.srli, x10, 0x200, 0x4000000, 0x11, x1, 156, x2)
inst_40:
// rs1_val == 33554432,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x2000000; immval:0x15
TEST_CI_OP( c.srli, x10, 0x10, 0x2000000, 0x15, x1, 160, x2)
inst_41:
// rs1_val == 16777216,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x1000000; immval:0x10
TEST_CI_OP( c.srli, x10, 0x100, 0x1000000, 0x10, x1, 164, x2)
inst_42:
// rs1_val == 8388608,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x800000; immval:0x1d
TEST_CI_OP( c.srli, x10, 0x0, 0x800000, 0x1d, x1, 168, x2)
inst_43:
// rs1_val == 4194304,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x400000; immval:0xc
TEST_CI_OP( c.srli, x10, 0x400, 0x400000, 0xc, x1, 172, x2)
inst_44:
// rs1_val == 2097152,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x200000; immval:0xc
TEST_CI_OP( c.srli, x10, 0x200, 0x200000, 0xc, x1, 176, x2)
inst_45:
// rs1_val == 1048576,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x100000; immval:0x17
TEST_CI_OP( c.srli, x10, 0x0, 0x100000, 0x17, x1, 180, x2)
inst_46:
// rs1_val == 524288,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x80000; immval:0x1f
TEST_CI_OP( c.srli, x10, 0x0, 0x80000, 0x1f, x1, 184, x2)
inst_47:
// rs1_val == 262144,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x40000; immval:0x13
TEST_CI_OP( c.srli, x10, 0x0, 0x40000, 0x13, x1, 188, x2)
inst_48:
// rs1_val == 131072,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x20000; immval:0x1f
TEST_CI_OP( c.srli, x10, 0x0, 0x20000, 0x1f, x1, 192, x2)
inst_49:
// rs1_val == 65536, imm_val == 8
// opcode:c.srli; op1:x10; dest:x10 op1val:0x10000; immval:0x8
TEST_CI_OP( c.srli, x10, 0x100, 0x10000, 0x8, x1, 196, x2)
inst_50:
// rs1_val == 32768,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x8000; immval:0x1d
TEST_CI_OP( c.srli, x10, 0x0, 0x8000, 0x1d, x1, 200, x2)
inst_51:
// rs1_val == 16384,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x4000; immval:0x3
TEST_CI_OP( c.srli, x10, 0x800, 0x4000, 0x3, x1, 204, x2)
inst_52:
// rs1_val == 8192,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x2000; immval:0x1d
TEST_CI_OP( c.srli, x10, 0x0, 0x2000, 0x1d, x1, 208, x2)
inst_53:
// rs1_val == 4096,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x1000; immval:0x17
TEST_CI_OP( c.srli, x10, 0x0, 0x1000, 0x17, x1, 212, x2)
inst_54:
// rs1_val == 2048,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x800; immval:0x7
TEST_CI_OP( c.srli, x10, 0x10, 0x800, 0x7, x1, 216, x2)
inst_55:
// rs1_val == 1024,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x400; immval:0x10
TEST_CI_OP( c.srli, x10, 0x0, 0x400, 0x10, x1, 220, x2)
inst_56:
// rs1_val == 512,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x200; immval:0x1d
TEST_CI_OP( c.srli, x10, 0x0, 0x200, 0x1d, x1, 224, x2)
inst_57:
// rs1_val == 256, imm_val == 1
// opcode:c.srli; op1:x10; dest:x10 op1val:0x100; immval:0x1
TEST_CI_OP( c.srli, x10, 0x80, 0x100, 0x1, x1, 228, x2)
inst_58:
// rs1_val == 128,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x80; immval:0x7
TEST_CI_OP( c.srli, x10, 0x1, 0x80, 0x7, x1, 232, x2)
inst_59:
// rs1_val == 64,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x40; immval:0xd
TEST_CI_OP( c.srli, x10, 0x0, 0x40, 0xd, x1, 236, x2)
inst_60:
// rs1_val == 32,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x20; immval:0x1e
TEST_CI_OP( c.srli, x10, 0x0, 0x20, 0x1e, x1, 240, x2)
inst_61:
// rs1_val == 16,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x10; immval:0x11
TEST_CI_OP( c.srli, x10, 0x0, 0x10, 0x11, x1, 244, x2)
inst_62:
// rs1_val == 8,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x8; immval:0x1b
TEST_CI_OP( c.srli, x10, 0x0, 0x8, 0x1b, x1, 248, x2)
inst_63:
// rs1_val == 4, rs1_val==4
// opcode:c.srli; op1:x10; dest:x10 op1val:0x4; immval:0x11
TEST_CI_OP( c.srli, x10, 0x0, 0x4, 0x11, x1, 252, x2)
inst_64:
// rs1_val == 2, rs1_val==2
// opcode:c.srli; op1:x10; dest:x10 op1val:0x2; immval:0x15
TEST_CI_OP( c.srli, x10, 0x0, 0x2, 0x15, x1, 256, x2)
inst_65:
// rs1_val == 1, rs1_val == 1 and imm_val != 0 and imm_val < xlen
// opcode:c.srli; op1:x10; dest:x10 op1val:0x1; immval:0x12
TEST_CI_OP( c.srli, x10, 0x0, 0x1, 0x12, x1, 260, x2)
inst_66:
// rs1_val==46341,
// opcode:c.srli; op1:x10; dest:x10 op1val:0xb505; immval:0x10
TEST_CI_OP( c.srli, x10, 0x0, 0xb505, 0x10, x1, 264, x2)
inst_67:
// rs1_val==-46339,
// opcode:c.srli; op1:x10; dest:x10 op1val:-0xb503; immval:0x15
TEST_CI_OP( c.srli, x10, 0x7ff, -0xb503, 0x15, x1, 268, x2)
inst_68:
// rs1_val==1717986919,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x66666667; immval:0x9
TEST_CI_OP( c.srli, x10, 0x333333, 0x66666667, 0x9, x1, 272, x2)
inst_69:
// rs1_val==858993460,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x33333334; immval:0xf
TEST_CI_OP( c.srli, x10, 0x6666, 0x33333334, 0xf, x1, 276, x2)
inst_70:
// rs1_val==6,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x6; immval:0x10
TEST_CI_OP( c.srli, x10, 0x0, 0x6, 0x10, x1, 280, x2)
inst_71:
// rs1_val==-1431655765,
// opcode:c.srli; op1:x10; dest:x10 op1val:-0x55555555; immval:0x5
TEST_CI_OP( c.srli, x10, 0x5555555, -0x55555555, 0x5, x1, 284, x2)
inst_72:
// rs1_val==1431655766,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x55555556; immval:0xf
TEST_CI_OP( c.srli, x10, 0xaaaa, 0x55555556, 0xf, x1, 288, x2)
inst_73:
// rs1_val==46339,
// opcode:c.srli; op1:x10; dest:x10 op1val:0xb503; immval:0x2
TEST_CI_OP( c.srli, x10, 0x2d40, 0xb503, 0x2, x1, 292, x2)
inst_74:
// rs1_val==0, rs1_val == 0 and imm_val != 0 and imm_val < xlen
// opcode:c.srli; op1:x10; dest:x10 op1val:0x0; immval:0xf
TEST_CI_OP( c.srli, x10, 0x0, 0x0, 0xf, x1, 296, x2)
inst_75:
// rs1_val==3,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x3; immval:0x6
TEST_CI_OP( c.srli, x10, 0x0, 0x3, 0x6, x1, 300, x2)
inst_76:
// rs1_val == -1431655766, rs1_val==-1431655766
// opcode:c.srli; op1:x10; dest:x10 op1val:-0x55555556; immval:0x2
TEST_CI_OP( c.srli, x10, 0x2aaaaaaa, -0x55555556, 0x2, x1, 304, x2)
inst_77:
// rs1_val == 1431655765, rs1_val==1431655765
// opcode:c.srli; op1:x10; dest:x10 op1val:0x55555555; immval:0xb
TEST_CI_OP( c.srli, x10, 0xaaaaa, 0x55555555, 0xb, x1, 308, x2)
inst_78:
// imm_val == 10,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x0; immval:0xa
TEST_CI_OP( c.srli, x10, 0x0, 0x0, 0xa, x1, 312, x2)
inst_79:
// rs1_val == imm_val and imm_val != 0 and imm_val < xlen,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x4; immval:0x4
TEST_CI_OP( c.srli, x10, 0x0, 0x4, 0x4, x1, 316, x2)
inst_80:
// rs1_val==1717986917,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x66666665; immval:0xe
TEST_CI_OP( c.srli, x10, 0x19999, 0x66666665, 0xe, x1, 320, x2)
inst_81:
// rs1_val==858993458,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x33333332; immval:0x6
TEST_CI_OP( c.srli, x10, 0xcccccc, 0x33333332, 0x6, x1, 324, x2)
inst_82:
// rs1_val==1431655764,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x55555554; immval:0x3
TEST_CI_OP( c.srli, x10, 0xaaaaaaa, 0x55555554, 0x3, x1, 328, x2)
inst_83:
// rs1_val==46340,
// opcode:c.srli; op1:x10; dest:x10 op1val:0xb504; immval:0x11
TEST_CI_OP( c.srli, x10, 0x0, 0xb504, 0x11, x1, 332, x2)
inst_84:
// rs1_val==-46340,
// opcode:c.srli; op1:x10; dest:x10 op1val:-0xb504; immval:0x5
TEST_CI_OP( c.srli, x10, 0x7fffa57, -0xb504, 0x5, x1, 336, x2)
inst_85:
// rs1_val==1717986918,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x66666666; immval:0x3
TEST_CI_OP( c.srli, x10, 0xccccccc, 0x66666666, 0x3, x1, 340, x2)
inst_86:
// rs1_val==858993459,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x33333333; immval:0x1f
TEST_CI_OP( c.srli, x10, 0x0, 0x33333333, 0x1f, x1, 344, x2)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
signature_x1_0:
.fill 0*(XLEN/32),4,0xdeadbeef
signature_x1_1:
.fill 87*(XLEN/32),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
RVMODEL_DATA_END

2980
tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/csub-01.S
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410
tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/csw-01.S
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@ -1,410 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version : 0.5.1
// timestamp : Wed Aug 4 06:39:00 2021 GMT
// usage : riscv_ctg \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32ec.cgf \
// --base-isa rv32e \
// --randomize
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the c.sw instruction of the RISC-V C extension for the csw covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32EC")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",csw)
RVTEST_SIGBASE( x1,signature_x1_1)
inst_0:
// rs1 != rs2, rs1==x15, rs2==x14, imm_val == 0, rs2_val == -16385
// opcode:c.sw; op1:x15; op2:x14; op2val:-0x4001; immval:0x0
TEST_STORE(x1,x2,0,x15,x14,-0x4001,0x0,0,c.sw,0)
inst_1:
// rs1==x11, rs2==x10, rs2_val == 2147483647, rs2_val == (2**(xlen-1)-1), imm_val > 0
// opcode:c.sw; op1:x11; op2:x10; op2val:0x7fffffff; immval:0x14
TEST_STORE(x1,x2,0,x11,x10,0x7fffffff,0x14,4,c.sw,0)
inst_2:
// rs1==x13, rs2==x8, rs2_val == -1073741825,
// opcode:c.sw; op1:x13; op2:x8; op2val:-0x40000001; immval:0x14
TEST_STORE(x1,x2,0,x13,x8,-0x40000001,0x14,8,c.sw,0)
inst_3:
// rs1==x9, rs2==x13, rs2_val == -536870913,
// opcode:c.sw; op1:x9; op2:x13; op2val:-0x20000001; immval:0x24
TEST_STORE(x1,x2,0,x9,x13,-0x20000001,0x24,12,c.sw,0)
inst_4:
// rs1==x10, rs2==x12, rs2_val == -268435457, imm_val == 32
// opcode:c.sw; op1:x10; op2:x12; op2val:-0x10000001; immval:0x20
TEST_STORE(x1,x2,0,x10,x12,-0x10000001,0x20,16,c.sw,0)
inst_5:
// rs1==x14, rs2==x15, rs2_val == -134217729,
// opcode:c.sw; op1:x14; op2:x15; op2val:-0x8000001; immval:0x4c
TEST_STORE(x1,x2,0,x14,x15,-0x8000001,0x4c,20,c.sw,0)
inst_6:
// rs1==x8, rs2==x9, rs2_val == -67108865,
// opcode:c.sw; op1:x8; op2:x9; op2val:-0x4000001; immval:0x48
TEST_STORE(x1,x2,0,x8,x9,-0x4000001,0x48,24,c.sw,0)
inst_7:
// rs1==x12, rs2==x11, rs2_val == -33554433, imm_val == 84
// opcode:c.sw; op1:x12; op2:x11; op2val:-0x2000001; immval:0x54
TEST_STORE(x1,x2,0,x12,x11,-0x2000001,0x54,28,c.sw,0)
inst_8:
// rs2_val == -16777217,
// opcode:c.sw; op1:x10; op2:x11; op2val:-0x1000001; immval:0x7c
TEST_STORE(x1,x2,0,x10,x11,-0x1000001,0x7c,32,c.sw,0)
inst_9:
// rs2_val == -8388609, imm_val == 4
// opcode:c.sw; op1:x10; op2:x11; op2val:-0x800001; immval:0x4
TEST_STORE(x1,x2,0,x10,x11,-0x800001,0x4,36,c.sw,0)
inst_10:
// rs2_val == -4194305, imm_val == 60
// opcode:c.sw; op1:x10; op2:x11; op2val:-0x400001; immval:0x3c
TEST_STORE(x1,x2,0,x10,x11,-0x400001,0x3c,40,c.sw,0)
inst_11:
// rs2_val == -2097153,
// opcode:c.sw; op1:x10; op2:x11; op2val:-0x200001; immval:0x30
TEST_STORE(x1,x2,0,x10,x11,-0x200001,0x30,44,c.sw,0)
inst_12:
// rs2_val == -1048577,
// opcode:c.sw; op1:x10; op2:x11; op2val:-0x100001; immval:0x7c
TEST_STORE(x1,x2,0,x10,x11,-0x100001,0x7c,48,c.sw,0)
inst_13:
// rs2_val == -524289,
// opcode:c.sw; op1:x10; op2:x11; op2val:-0x80001; immval:0x18
TEST_STORE(x1,x2,0,x10,x11,-0x80001,0x18,52,c.sw,0)
inst_14:
// rs2_val == -262145, imm_val == 40
// opcode:c.sw; op1:x10; op2:x11; op2val:-0x40001; immval:0x28
TEST_STORE(x1,x2,0,x10,x11,-0x40001,0x28,56,c.sw,0)
inst_15:
// rs2_val == -131073,
// opcode:c.sw; op1:x10; op2:x11; op2val:-0x20001; immval:0x7c
TEST_STORE(x1,x2,0,x10,x11,-0x20001,0x7c,60,c.sw,0)
inst_16:
// rs2_val == -65537,
// opcode:c.sw; op1:x10; op2:x11; op2val:-0x10001; immval:0x14
TEST_STORE(x1,x2,0,x10,x11,-0x10001,0x14,64,c.sw,0)
inst_17:
// rs2_val == -32769, imm_val == 64
// opcode:c.sw; op1:x10; op2:x11; op2val:-0x8001; immval:0x40
TEST_STORE(x1,x2,0,x10,x11,-0x8001,0x40,68,c.sw,0)
inst_18:
// rs2_val == -8193,
// opcode:c.sw; op1:x10; op2:x11; op2val:-0x2001; immval:0x0
TEST_STORE(x1,x2,0,x10,x11,-0x2001,0x0,72,c.sw,0)
inst_19:
// rs2_val == -4097,
// opcode:c.sw; op1:x10; op2:x11; op2val:-0x1001; immval:0x48
TEST_STORE(x1,x2,0,x10,x11,-0x1001,0x48,76,c.sw,0)
inst_20:
// rs2_val == -2049,
// opcode:c.sw; op1:x10; op2:x11; op2val:-0x801; immval:0x24
TEST_STORE(x1,x2,0,x10,x11,-0x801,0x24,80,c.sw,0)
inst_21:
// rs2_val == -1025,
// opcode:c.sw; op1:x10; op2:x11; op2val:-0x401; immval:0x28
TEST_STORE(x1,x2,0,x10,x11,-0x401,0x28,84,c.sw,0)
inst_22:
// rs2_val == -513, imm_val == 120
// opcode:c.sw; op1:x10; op2:x11; op2val:-0x201; immval:0x78
TEST_STORE(x1,x2,0,x10,x11,-0x201,0x78,88,c.sw,0)
inst_23:
// rs2_val == -257,
// opcode:c.sw; op1:x10; op2:x11; op2val:-0x101; immval:0x24
TEST_STORE(x1,x2,0,x10,x11,-0x101,0x24,92,c.sw,0)
inst_24:
// rs2_val == -129,
// opcode:c.sw; op1:x10; op2:x11; op2val:-0x81; immval:0x4c
TEST_STORE(x1,x2,0,x10,x11,-0x81,0x4c,96,c.sw,0)
inst_25:
// rs2_val == -65,
// opcode:c.sw; op1:x10; op2:x11; op2val:-0x41; immval:0x14
TEST_STORE(x1,x2,0,x10,x11,-0x41,0x14,100,c.sw,0)
inst_26:
// rs2_val == -33,
// opcode:c.sw; op1:x10; op2:x11; op2val:-0x21; immval:0x28
TEST_STORE(x1,x2,0,x10,x11,-0x21,0x28,104,c.sw,0)
inst_27:
// rs2_val == -17,
// opcode:c.sw; op1:x10; op2:x11; op2val:-0x11; immval:0x34
TEST_STORE(x1,x2,0,x10,x11,-0x11,0x34,108,c.sw,0)
inst_28:
// rs2_val == -9,
// opcode:c.sw; op1:x10; op2:x11; op2val:-0x9; immval:0x28
TEST_STORE(x1,x2,0,x10,x11,-0x9,0x28,112,c.sw,0)
inst_29:
// rs2_val == -5,
// opcode:c.sw; op1:x10; op2:x11; op2val:-0x5; immval:0xc
TEST_STORE(x1,x2,0,x10,x11,-0x5,0xc,116,c.sw,0)
inst_30:
// rs2_val == -3, imm_val == 108
// opcode:c.sw; op1:x10; op2:x11; op2val:-0x3; immval:0x6c
TEST_STORE(x1,x2,0,x10,x11,-0x3,0x6c,120,c.sw,0)
inst_31:
// rs2_val == -2, imm_val == 92
// opcode:c.sw; op1:x10; op2:x11; op2val:-0x2; immval:0x5c
TEST_STORE(x1,x2,0,x10,x11,-0x2,0x5c,124,c.sw,0)
inst_32:
// imm_val == 116, rs2_val == 32768
// opcode:c.sw; op1:x10; op2:x11; op2val:0x8000; immval:0x74
TEST_STORE(x1,x2,0,x10,x11,0x8000,0x74,128,c.sw,0)
inst_33:
// rs2_val == -2147483648, rs2_val == (-2**(xlen-1))
// opcode:c.sw; op1:x10; op2:x11; op2val:-0x80000000; immval:0x7c
TEST_STORE(x1,x2,0,x10,x11,-0x80000000,0x7c,132,c.sw,0)
inst_34:
// rs2_val == 1073741824,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x40000000; immval:0x38
TEST_STORE(x1,x2,0,x10,x11,0x40000000,0x38,136,c.sw,0)
inst_35:
// rs2_val == 536870912,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x20000000; immval:0x7c
TEST_STORE(x1,x2,0,x10,x11,0x20000000,0x7c,140,c.sw,0)
inst_36:
// rs2_val == 268435456,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x10000000; immval:0x1c
TEST_STORE(x1,x2,0,x10,x11,0x10000000,0x1c,144,c.sw,0)
inst_37:
// rs2_val == 134217728,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x8000000; immval:0x5c
TEST_STORE(x1,x2,0,x10,x11,0x8000000,0x5c,148,c.sw,0)
inst_38:
// rs2_val == 32,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x20; immval:0x2c
TEST_STORE(x1,x2,0,x10,x11,0x20,0x2c,152,c.sw,0)
inst_39:
// rs2_val == 16,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x10; immval:0x30
TEST_STORE(x1,x2,0,x10,x11,0x10,0x30,156,c.sw,0)
inst_40:
// rs2_val == 8,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x8; immval:0x24
TEST_STORE(x1,x2,0,x10,x11,0x8,0x24,160,c.sw,0)
inst_41:
// rs2_val == 4,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x4; immval:0x7c
TEST_STORE(x1,x2,0,x10,x11,0x4,0x7c,164,c.sw,0)
inst_42:
// rs2_val == 2,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x2; immval:0x34
TEST_STORE(x1,x2,0,x10,x11,0x2,0x34,168,c.sw,0)
inst_43:
// rs2_val == 1,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x1; immval:0x54
TEST_STORE(x1,x2,0,x10,x11,0x1,0x54,172,c.sw,0)
inst_44:
// imm_val == 16,
// opcode:c.sw; op1:x10; op2:x11; op2val:-0x100001; immval:0x10
TEST_STORE(x1,x2,0,x10,x11,-0x100001,0x10,176,c.sw,0)
inst_45:
// imm_val == 8, rs2_val == 524288
// opcode:c.sw; op1:x10; op2:x11; op2val:0x80000; immval:0x8
TEST_STORE(x1,x2,0,x10,x11,0x80000,0x8,180,c.sw,0)
inst_46:
// rs2_val == -1431655766,
// opcode:c.sw; op1:x10; op2:x11; op2val:-0x55555556; immval:0x3c
TEST_STORE(x1,x2,0,x10,x11,-0x55555556,0x3c,184,c.sw,0)
inst_47:
// rs2_val == 1431655765,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x55555555; immval:0x10
TEST_STORE(x1,x2,0,x10,x11,0x55555555,0x10,188,c.sw,0)
inst_48:
// rs2_val == 0,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x0; immval:0x38
TEST_STORE(x1,x2,0,x10,x11,0x0,0x38,192,c.sw,0)
inst_49:
// rs2_val == 67108864,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x4000000; immval:0xc
TEST_STORE(x1,x2,0,x10,x11,0x4000000,0xc,196,c.sw,0)
inst_50:
// rs2_val == 33554432,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x2000000; immval:0x3c
TEST_STORE(x1,x2,0,x10,x11,0x2000000,0x3c,200,c.sw,0)
inst_51:
// rs2_val == 16777216,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x1000000; immval:0x20
TEST_STORE(x1,x2,0,x10,x11,0x1000000,0x20,204,c.sw,0)
inst_52:
// rs2_val == 8388608,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x800000; immval:0x10
TEST_STORE(x1,x2,0,x10,x11,0x800000,0x10,208,c.sw,0)
inst_53:
// rs2_val == 4194304,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x400000; immval:0x0
TEST_STORE(x1,x2,0,x10,x11,0x400000,0x0,212,c.sw,0)
inst_54:
// rs2_val == 2097152,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x200000; immval:0x24
TEST_STORE(x1,x2,0,x10,x11,0x200000,0x24,216,c.sw,0)
inst_55:
// rs2_val == 1048576,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x100000; immval:0x34
TEST_STORE(x1,x2,0,x10,x11,0x100000,0x34,220,c.sw,0)
inst_56:
// rs2_val == 262144,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x40000; immval:0x14
TEST_STORE(x1,x2,0,x10,x11,0x40000,0x14,224,c.sw,0)
inst_57:
// rs2_val == 131072,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x20000; immval:0x20
TEST_STORE(x1,x2,0,x10,x11,0x20000,0x20,228,c.sw,0)
inst_58:
// rs2_val == 65536,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x10000; immval:0x44
TEST_STORE(x1,x2,0,x10,x11,0x10000,0x44,232,c.sw,0)
inst_59:
// rs2_val == 16384,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x4000; immval:0x20
TEST_STORE(x1,x2,0,x10,x11,0x4000,0x20,236,c.sw,0)
inst_60:
// rs2_val == 8192,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x2000; immval:0x78
TEST_STORE(x1,x2,0,x10,x11,0x2000,0x78,240,c.sw,0)
inst_61:
// rs2_val == 4096,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x1000; immval:0x7c
TEST_STORE(x1,x2,0,x10,x11,0x1000,0x7c,244,c.sw,0)
inst_62:
// rs2_val == 2048,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x800; immval:0x6c
TEST_STORE(x1,x2,0,x10,x11,0x800,0x6c,248,c.sw,0)
inst_63:
// rs2_val == 1024,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x400; immval:0x4c
TEST_STORE(x1,x2,0,x10,x11,0x400,0x4c,252,c.sw,0)
inst_64:
// rs2_val == 512,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x200; immval:0x5c
TEST_STORE(x1,x2,0,x10,x11,0x200,0x5c,256,c.sw,0)
inst_65:
// rs2_val == 256,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x100; immval:0x28
TEST_STORE(x1,x2,0,x10,x11,0x100,0x28,260,c.sw,0)
inst_66:
// rs2_val == 128,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x80; immval:0x78
TEST_STORE(x1,x2,0,x10,x11,0x80,0x78,264,c.sw,0)
inst_67:
// rs2_val == 64,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x40; immval:0x3c
TEST_STORE(x1,x2,0,x10,x11,0x40,0x3c,268,c.sw,0)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
signature_x1_0:
.fill 0*(XLEN/32),4,0xdeadbeef
signature_x1_1:
.fill 68*(XLEN/32),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
RVMODEL_DATA_END

425
tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/cswsp-01.S
View File

@ -1,425 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version : 0.5.1
// timestamp : Mon Sep 13 07:01:20 2021 GMT
// usage : riscv_ctg \
// --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/rv32ec.cgf \
// --base-isa rv32e \
// --randomize
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the c.swsp instruction of the RISC-V C extension for the cswsp covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32EC")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",cswsp)
RVTEST_SIGBASE( x8,signature_x8_1)
inst_0:
// rs2==x12, imm_val == 0,
// opcode:c.swsp; op1:x2; op2:x12; op2val:0x3; immval:0x0
TEST_STORE(x8,x9,0,x2,x12,0x3,0x0,0,c.swsp,0)
inst_1:
// rs2==x1, rs2_val == 2147483647, imm_val > 0, rs2_val == (2**(xlen-1)-1), imm_val == 236
// opcode:c.swsp; op1:x2; op2:x1; op2val:0x7fffffff; immval:0xec
TEST_STORE(x8,x9,0,x2,x1,0x7fffffff,0xec,4,c.swsp,0)
inst_2:
// rs2==x7, rs2_val == -1073741825,
// opcode:c.swsp; op1:x2; op2:x7; op2val:-0x40000001; immval:0x48
TEST_STORE(x8,x9,0,x2,x7,-0x40000001,0x48,8,c.swsp,0)
inst_3:
// rs2==x13, rs2_val == -536870913,
// opcode:c.swsp; op1:x2; op2:x13; op2val:-0x20000001; immval:0x48
TEST_STORE(x8,x9,0,x2,x13,-0x20000001,0x48,12,c.swsp,0)
inst_4:
// rs2==x2, rs2_val == -268435457, imm_val == 8
// opcode:c.swsp; op1:x2; op2:x2; op2val:-0x10000001; immval:0x8
TEST_STORE(x8,x9,0,x2,x2,-0x10000001,0x8,16,c.swsp,0)
inst_5:
// rs2==x4, rs2_val == -134217729,
// opcode:c.swsp; op1:x2; op2:x4; op2val:-0x8000001; immval:0x28
TEST_STORE(x8,x9,0,x2,x4,-0x8000001,0x28,20,c.swsp,0)
inst_6:
// rs2==x10, rs2_val == -67108865,
// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x4000001; immval:0x4c
TEST_STORE(x8,x9,0,x2,x10,-0x4000001,0x4c,24,c.swsp,0)
inst_7:
// rs2==x15, rs2_val == -33554433,
// opcode:c.swsp; op1:x2; op2:x15; op2val:-0x2000001; immval:0x18
TEST_STORE(x8,x9,0,x2,x15,-0x2000001,0x18,28,c.swsp,0)
inst_8:
// rs2==x5, rs2_val == -16777217, imm_val == 244
// opcode:c.swsp; op1:x2; op2:x5; op2val:-0x1000001; immval:0xf4
TEST_STORE(x8,x9,0,x2,x5,-0x1000001,0xf4,32,c.swsp,0)
inst_9:
// rs2==x3, rs2_val == -8388609,
// opcode:c.swsp; op1:x2; op2:x3; op2val:-0x800001; immval:0x4c
TEST_STORE(x8,x9,0,x2,x3,-0x800001,0x4c,36,c.swsp,0)
inst_10:
// rs2==x6, rs2_val == -4194305,
// opcode:c.swsp; op1:x2; op2:x6; op2val:-0x400001; immval:0x30
TEST_STORE(x8,x9,0,x2,x6,-0x400001,0x30,40,c.swsp,0)
inst_11:
// rs2==x9, rs2_val == -2097153, imm_val == 128
// opcode:c.swsp; op1:x2; op2:x9; op2val:-0x200001; immval:0x80
TEST_STORE(x8,x3,0,x2,x9,-0x200001,0x80,44,c.swsp,0)
RVTEST_SIGBASE( x1,signature_x1_0)
inst_12:
// rs2==x11, rs2_val == -1048577, imm_val == 124
// opcode:c.swsp; op1:x2; op2:x11; op2val:-0x100001; immval:0x7c
TEST_STORE(x1,x3,0,x2,x11,-0x100001,0x7c,0,c.swsp,0)
inst_13:
// rs2==x14, rs2_val == -524289,
// opcode:c.swsp; op1:x2; op2:x14; op2val:-0x80001; immval:0x34
TEST_STORE(x1,x3,0,x2,x14,-0x80001,0x34,4,c.swsp,0)
inst_14:
// rs2==x8, rs2_val == -262145, imm_val == 168
// opcode:c.swsp; op1:x2; op2:x8; op2val:-0x40001; immval:0xa8
TEST_STORE(x1,x3,0,x2,x8,-0x40001,0xa8,8,c.swsp,0)
inst_15:
// rs2_val == -131073,
// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x20001; immval:0xf4
TEST_STORE(x1,x3,0,x2,x10,-0x20001,0xf4,12,c.swsp,0)
inst_16:
// rs2_val == -65537,
// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x10001; immval:0x3c
TEST_STORE(x1,x3,0,x2,x10,-0x10001,0x3c,16,c.swsp,0)
inst_17:
// rs2_val == -32769,
// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x8001; immval:0x1c
TEST_STORE(x1,x3,0,x2,x10,-0x8001,0x1c,20,c.swsp,0)
inst_18:
// rs2_val == -16385, imm_val == 4
// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x4001; immval:0x4
TEST_STORE(x1,x3,0,x2,x10,-0x4001,0x4,24,c.swsp,0)
inst_19:
// rs2_val == -8193,
// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x2001; immval:0xa8
TEST_STORE(x1,x3,0,x2,x10,-0x2001,0xa8,28,c.swsp,0)
inst_20:
// rs2_val == -4097, imm_val == 248
// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x1001; immval:0xf8
TEST_STORE(x1,x3,0,x2,x10,-0x1001,0xf8,32,c.swsp,0)
inst_21:
// rs2_val == -2049, imm_val == 64
// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x801; immval:0x40
TEST_STORE(x1,x3,0,x2,x10,-0x801,0x40,36,c.swsp,0)
inst_22:
// rs2_val == -1025,
// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x401; immval:0xc
TEST_STORE(x1,x3,0,x2,x10,-0x401,0xc,40,c.swsp,0)
inst_23:
// rs2_val == -513,
// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x201; immval:0x38
TEST_STORE(x1,x3,0,x2,x10,-0x201,0x38,44,c.swsp,0)
inst_24:
// rs2_val == -257, imm_val == 220
// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x101; immval:0xdc
TEST_STORE(x1,x3,0,x2,x10,-0x101,0xdc,48,c.swsp,0)
inst_25:
// rs2_val == -129, imm_val == 32
// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x81; immval:0x20
TEST_STORE(x1,x3,0,x2,x10,-0x81,0x20,52,c.swsp,0)
inst_26:
// rs2_val == -65,
// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x41; immval:0x34
TEST_STORE(x1,x3,0,x2,x10,-0x41,0x34,56,c.swsp,0)
inst_27:
// rs2_val == -33,
// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x21; immval:0xf8
TEST_STORE(x1,x3,0,x2,x10,-0x21,0xf8,60,c.swsp,0)
inst_28:
// rs2_val == -17,
// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x11; immval:0x4c
TEST_STORE(x1,x3,0,x2,x10,-0x11,0x4c,64,c.swsp,0)
inst_29:
// rs2_val == -9,
// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x9; immval:0x30
TEST_STORE(x1,x3,0,x2,x10,-0x9,0x30,68,c.swsp,0)
inst_30:
// rs2_val == -5,
// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x5; immval:0x3c
TEST_STORE(x1,x3,0,x2,x10,-0x5,0x3c,72,c.swsp,0)
inst_31:
// rs2_val == -3,
// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x3; immval:0x80
TEST_STORE(x1,x3,0,x2,x10,-0x3,0x80,76,c.swsp,0)
inst_32:
// rs2_val == -2,
// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x2; immval:0x24
TEST_STORE(x1,x3,0,x2,x10,-0x2,0x24,80,c.swsp,0)
inst_33:
// imm_val == 188,
// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x8001; immval:0xbc
TEST_STORE(x1,x3,0,x2,x10,-0x8001,0xbc,84,c.swsp,0)
inst_34:
// rs2_val == -2147483648, rs2_val == (-2**(xlen-1))
// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x80000000; immval:0x20
TEST_STORE(x1,x3,0,x2,x10,-0x80000000,0x20,88,c.swsp,0)
inst_35:
// rs2_val == 1073741824,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x40000000; immval:0x38
TEST_STORE(x1,x3,0,x2,x10,0x40000000,0x38,92,c.swsp,0)
inst_36:
// rs2_val == 536870912,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x20000000; immval:0x7c
TEST_STORE(x1,x3,0,x2,x10,0x20000000,0x7c,96,c.swsp,0)
inst_37:
// rs2_val == 268435456,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x10000000; immval:0xfc
TEST_STORE(x1,x3,0,x2,x10,0x10000000,0xfc,100,c.swsp,0)
inst_38:
// rs2_val == 134217728,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x8000000; immval:0x48
TEST_STORE(x1,x3,0,x2,x10,0x8000000,0x48,104,c.swsp,0)
inst_39:
// rs2_val == 67108864, imm_val == 84
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x4000000; immval:0x54
TEST_STORE(x1,x3,0,x2,x10,0x4000000,0x54,108,c.swsp,0)
inst_40:
// rs2_val == 64, imm_val == 16
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x40; immval:0x10
TEST_STORE(x1,x3,0,x2,x10,0x40,0x10,112,c.swsp,0)
inst_41:
// rs2_val == 32,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x20; immval:0x14
TEST_STORE(x1,x3,0,x2,x10,0x20,0x14,116,c.swsp,0)
inst_42:
// rs2_val == 16,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x10; immval:0x4c
TEST_STORE(x1,x3,0,x2,x10,0x10,0x4c,120,c.swsp,0)
inst_43:
// rs2_val == 8,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x8; immval:0x4c
TEST_STORE(x1,x3,0,x2,x10,0x8,0x4c,124,c.swsp,0)
inst_44:
// rs2_val == 4,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x4; immval:0xf8
TEST_STORE(x1,x3,0,x2,x10,0x4,0xf8,128,c.swsp,0)
inst_45:
// rs2_val == 2,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x2; immval:0x2c
TEST_STORE(x1,x3,0,x2,x10,0x2,0x2c,132,c.swsp,0)
inst_46:
// rs2_val == 1,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x1; immval:0xbc
TEST_STORE(x1,x3,0,x2,x10,0x1,0xbc,136,c.swsp,0)
inst_47:
// rs2_val == -1431655766,
// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x55555556; immval:0xdc
TEST_STORE(x1,x3,0,x2,x10,-0x55555556,0xdc,140,c.swsp,0)
inst_48:
// rs2_val == 1431655765,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x55555555; immval:0x4c
TEST_STORE(x1,x3,0,x2,x10,0x55555555,0x4c,144,c.swsp,0)
inst_49:
// rs2_val == 0,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x0; immval:0x40
TEST_STORE(x1,x3,0,x2,x10,0x0,0x40,148,c.swsp,0)
inst_50:
// rs2_val == 33554432,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x2000000; immval:0x4
TEST_STORE(x1,x3,0,x2,x10,0x2000000,0x4,152,c.swsp,0)
inst_51:
// rs2_val == 16777216,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x1000000; immval:0x7c
TEST_STORE(x1,x3,0,x2,x10,0x1000000,0x7c,156,c.swsp,0)
inst_52:
// rs2_val == 8388608,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x800000; immval:0x18
TEST_STORE(x1,x3,0,x2,x10,0x800000,0x18,160,c.swsp,0)
inst_53:
// rs2_val == 4194304,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x400000; immval:0x40
TEST_STORE(x1,x3,0,x2,x10,0x400000,0x40,164,c.swsp,0)
inst_54:
// rs2_val == 2097152,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x200000; immval:0x54
TEST_STORE(x1,x3,0,x2,x10,0x200000,0x54,168,c.swsp,0)
inst_55:
// rs2_val == 1048576,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x100000; immval:0x34
TEST_STORE(x1,x3,0,x2,x10,0x100000,0x34,172,c.swsp,0)
inst_56:
// rs2_val == 524288,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x80000; immval:0x20
TEST_STORE(x1,x3,0,x2,x10,0x80000,0x20,176,c.swsp,0)
inst_57:
// rs2_val == 262144,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x40000; immval:0x44
TEST_STORE(x1,x3,0,x2,x10,0x40000,0x44,180,c.swsp,0)
inst_58:
// rs2_val == 131072,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x20000; immval:0xa8
TEST_STORE(x1,x3,0,x2,x10,0x20000,0xa8,184,c.swsp,0)
inst_59:
// rs2_val == 65536,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x10000; immval:0x3c
TEST_STORE(x1,x3,0,x2,x10,0x10000,0x3c,188,c.swsp,0)
inst_60:
// rs2_val == 32768,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x8000; immval:0x34
TEST_STORE(x1,x3,0,x2,x10,0x8000,0x34,192,c.swsp,0)
inst_61:
// rs2_val == 16384,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x4000; immval:0xc
TEST_STORE(x1,x3,0,x2,x10,0x4000,0xc,196,c.swsp,0)
inst_62:
// rs2_val == 8192,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x2000; immval:0x4
TEST_STORE(x1,x3,0,x2,x10,0x2000,0x4,200,c.swsp,0)
inst_63:
// rs2_val == 4096,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x1000; immval:0x30
TEST_STORE(x1,x3,0,x2,x10,0x1000,0x30,204,c.swsp,0)
inst_64:
// rs2_val == 2048,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x800; immval:0x38
TEST_STORE(x1,x3,0,x2,x10,0x800,0x38,208,c.swsp,0)
inst_65:
// rs2_val == 1024,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x400; immval:0x10
TEST_STORE(x1,x3,0,x2,x10,0x400,0x10,212,c.swsp,0)
inst_66:
// rs2_val == 512,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x200; immval:0x3c
TEST_STORE(x1,x3,0,x2,x10,0x200,0x3c,216,c.swsp,0)
inst_67:
// rs2_val == 256,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x100; immval:0x1c
TEST_STORE(x1,x3,0,x2,x10,0x100,0x1c,220,c.swsp,0)
inst_68:
// rs2_val == 128,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x80; immval:0xf8
TEST_STORE(x1,x3,0,x2,x10,0x80,0xf8,224,c.swsp,0)
inst_69:
// rs2_val == -268435457, imm_val == 8
// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x10000001; immval:0x8
TEST_STORE(x1,x3,0,x2,x10,-0x10000001,0x8,228,c.swsp,0)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
signature_x8_0:
.fill 0*(XLEN/32),4,0xdeadbeef
signature_x8_1:
.fill 12*(XLEN/32),4,0xdeadbeef
signature_x1_0:
.fill 58*(XLEN/32),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
RVMODEL_DATA_END

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include ../../Makefile.include
$(eval $(call compile_template,-march=rv32em -mabi=ilp32e -DXLEN=$(XLEN)))

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# RISC-V Architecture Test RV32EM Makefrag
#
# Copyright (c) 2018, Imperas Software Ltd.
# Copyright (c) 2020, InCore Semiconductors. Pvt. Ltd.
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
# * Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# * Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# * Neither the name of the Imperas Software Ltd. nor the
# names of its contributors may be used to endorse or promote products
# derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY
# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Description: Makefrag for RV32EM architectural tests
rv32em_sc_tests = \
div-01 \
divu-01 \
mul-01 \
mulh-01 \
mulhsu-01 \
mulhu-01 \
rem-01 \
remu-01
rv32em_tests = $(addsuffix .elf, $(rv32em_sc_tests))
target_tests += $(rv32em_tests)

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// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version : 0.5.1
// timestamp : Mon Aug 2 08:58:53 2021 GMT
// usage : riscv_ctg \
// --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/rv32e.cgf \
// --base-isa rv32e \
// --randomize
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the auipc instruction of the RISC-V E extension for the auipc covergroup.
//
#define RVTEST_E
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32E")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",auipc)
RVTEST_SIGBASE( x2,signature_x2_1)
inst_0:
// rd==x9, imm_val == ((2**20)-1), imm_val > 0
// opcode: auipc ; dest:x9; immval:0xfffff
TEST_AUIPC(auipc, x9, -0x1000, 0xfffff, x2, 0, x3)
inst_1:
// rd==x6, imm_val == 524287,
// opcode: auipc ; dest:x6; immval:0x7ffff
TEST_AUIPC(auipc, x6, 0x7ffff000, 0x7ffff, x2, 4, x3)
inst_2:
// rd==x1, imm_val == 786431,
// opcode: auipc ; dest:x1; immval:0xbffff
TEST_AUIPC(auipc, x1, -0x40001000, 0xbffff, x2, 8, x3)
inst_3:
// rd==x5, imm_val == 917503,
// opcode: auipc ; dest:x5; immval:0xdffff
TEST_AUIPC(auipc, x5, -0x20001000, 0xdffff, x2, 12, x3)
inst_4:
// rd==x14, imm_val == 983039,
// opcode: auipc ; dest:x14; immval:0xeffff
TEST_AUIPC(auipc, x14, -0x10001000, 0xeffff, x2, 16, x3)
inst_5:
// rd==x7, imm_val == 1015807,
// opcode: auipc ; dest:x7; immval:0xf7fff
TEST_AUIPC(auipc, x7, -0x8001000, 0xf7fff, x2, 20, x3)
inst_6:
// rd==x15, imm_val == 1032191,
// opcode: auipc ; dest:x15; immval:0xfbfff
TEST_AUIPC(auipc, x15, -0x4001000, 0xfbfff, x2, 24, x3)
inst_7:
// rd==x10, imm_val == 1040383,
// opcode: auipc ; dest:x10; immval:0xfdfff
TEST_AUIPC(auipc, x10, -0x2001000, 0xfdfff, x2, 28, x3)
inst_8:
// rd==x12, imm_val == 1044479,
// opcode: auipc ; dest:x12; immval:0xfefff
TEST_AUIPC(auipc, x12, -0x1001000, 0xfefff, x2, 32, x3)
inst_9:
// rd==x0, imm_val == 1046527,
// opcode: auipc ; dest:x0; immval:0xff7ff
TEST_AUIPC(auipc, x0, 0, 0xff7ff, x2, 36, x3)
inst_10:
// rd==x8, imm_val == 1047551,
// opcode: auipc ; dest:x8; immval:0xffbff
TEST_AUIPC(auipc, x8, -0x401000, 0xffbff, x2, 40, x3)
inst_11:
// rd==x4, imm_val == 1048063,
// opcode: auipc ; dest:x4; immval:0xffdff
TEST_AUIPC(auipc, x4, -0x201000, 0xffdff, x2, 44, x3)
inst_12:
// rd==x13, imm_val == 1048319,
// opcode: auipc ; dest:x13; immval:0xffeff
TEST_AUIPC(auipc, x13, -0x101000, 0xffeff, x2, 48, x4)
RVTEST_SIGBASE( x1,signature_x1_0)
inst_13:
// rd==x3, imm_val == 1048447,
// opcode: auipc ; dest:x3; immval:0xfff7f
TEST_AUIPC(auipc, x3, -0x81000, 0xfff7f, x1, 0, x4)
inst_14:
// rd==x11, imm_val == 1048511,
// opcode: auipc ; dest:x11; immval:0xfffbf
TEST_AUIPC(auipc, x11, -0x41000, 0xfffbf, x1, 4, x4)
inst_15:
// rd==x2, imm_val == 1048543,
// opcode: auipc ; dest:x2; immval:0xfffdf
TEST_AUIPC(auipc, x2, -0x21000, 0xfffdf, x1, 8, x4)
inst_16:
// imm_val == 1048559,
// opcode: auipc ; dest:x10; immval:0xfffef
TEST_AUIPC(auipc, x10, -0x11000, 0xfffef, x1, 12, x4)
inst_17:
// imm_val == 1048567,
// opcode: auipc ; dest:x10; immval:0xffff7
TEST_AUIPC(auipc, x10, -0x9000, 0xffff7, x1, 16, x4)
inst_18:
// imm_val == 1048571,
// opcode: auipc ; dest:x10; immval:0xffffb
TEST_AUIPC(auipc, x10, -0x5000, 0xffffb, x1, 20, x4)
inst_19:
// imm_val == 1048573,
// opcode: auipc ; dest:x10; immval:0xffffd
TEST_AUIPC(auipc, x10, -0x3000, 0xffffd, x1, 24, x4)
inst_20:
// imm_val == 1048574,
// opcode: auipc ; dest:x10; immval:0xffffe
TEST_AUIPC(auipc, x10, -0x2000, 0xffffe, x1, 28, x4)
inst_21:
// imm_val == 524288,
// opcode: auipc ; dest:x10; immval:0x80000
TEST_AUIPC(auipc, x10, -0x80000000, 0x80000, x1, 32, x4)
inst_22:
// imm_val == 262144,
// opcode: auipc ; dest:x10; immval:0x40000
TEST_AUIPC(auipc, x10, 0x40000000, 0x40000, x1, 36, x4)
inst_23:
// imm_val == 131072,
// opcode: auipc ; dest:x10; immval:0x20000
TEST_AUIPC(auipc, x10, 0x20000000, 0x20000, x1, 40, x4)
inst_24:
// imm_val == 65536,
// opcode: auipc ; dest:x10; immval:0x10000
TEST_AUIPC(auipc, x10, 0x10000000, 0x10000, x1, 44, x4)
inst_25:
// imm_val == 32768,
// opcode: auipc ; dest:x10; immval:0x8000
TEST_AUIPC(auipc, x10, 0x8000000, 0x8000, x1, 48, x4)
inst_26:
// imm_val == 16384,
// opcode: auipc ; dest:x10; immval:0x4000
TEST_AUIPC(auipc, x10, 0x4000000, 0x4000, x1, 52, x4)
inst_27:
// imm_val == 8192,
// opcode: auipc ; dest:x10; immval:0x2000
TEST_AUIPC(auipc, x10, 0x2000000, 0x2000, x1, 56, x4)
inst_28:
// imm_val == 4096,
// opcode: auipc ; dest:x10; immval:0x1000
TEST_AUIPC(auipc, x10, 0x1000000, 0x1000, x1, 60, x4)
inst_29:
// imm_val == 2048,
// opcode: auipc ; dest:x10; immval:0x800
TEST_AUIPC(auipc, x10, 0x800000, 0x800, x1, 64, x4)
inst_30:
// imm_val == 1024, imm_val==1024
// opcode: auipc ; dest:x10; immval:0x400
TEST_AUIPC(auipc, x10, 0x400000, 0x400, x1, 68, x4)
inst_31:
// imm_val == 512,
// opcode: auipc ; dest:x10; immval:0x200
TEST_AUIPC(auipc, x10, 0x200000, 0x200, x1, 72, x4)
inst_32:
// imm_val == 256,
// opcode: auipc ; dest:x10; immval:0x100
TEST_AUIPC(auipc, x10, 0x100000, 0x100, x1, 76, x4)
inst_33:
// imm_val == 128,
// opcode: auipc ; dest:x10; immval:0x80
TEST_AUIPC(auipc, x10, 0x80000, 0x80, x1, 80, x4)
inst_34:
// imm_val == 64,
// opcode: auipc ; dest:x10; immval:0x40
TEST_AUIPC(auipc, x10, 0x40000, 0x40, x1, 84, x4)
inst_35:
// imm_val == 32,
// opcode: auipc ; dest:x10; immval:0x20
TEST_AUIPC(auipc, x10, 0x20000, 0x20, x1, 88, x4)
inst_36:
// imm_val == 16,
// opcode: auipc ; dest:x10; immval:0x10
TEST_AUIPC(auipc, x10, 0x10000, 0x10, x1, 92, x4)
inst_37:
// imm_val==349525, imm_val == 349525
// opcode: auipc ; dest:x10; immval:0x55555
TEST_AUIPC(auipc, x10, 0x55555000, 0x55555, x1, 96, x4)
inst_38:
// imm_val==3,
// opcode: auipc ; dest:x10; immval:0x3
TEST_AUIPC(auipc, x10, 0x3000, 0x3, x1, 100, x4)
inst_39:
// imm_val == 699050, imm_val==699050
// opcode: auipc ; dest:x10; immval:0xaaaaa
TEST_AUIPC(auipc, x10, -0x55556000, 0xaaaaa, x1, 104, x4)
inst_40:
// imm_val == 0, imm_val==0
// opcode: auipc ; dest:x10; immval:0x0
TEST_AUIPC(auipc, x10, 0x0, 0x0, x1, 108, x4)
inst_41:
// imm_val == 8,
// opcode: auipc ; dest:x10; immval:0x8
TEST_AUIPC(auipc, x10, 0x8000, 0x8, x1, 112, x4)
inst_42:
// imm_val == 4, imm_val==4
// opcode: auipc ; dest:x10; immval:0x4
TEST_AUIPC(auipc, x10, 0x4000, 0x4, x1, 116, x4)
inst_43:
// imm_val == 2, imm_val==2
// opcode: auipc ; dest:x10; immval:0x2
TEST_AUIPC(auipc, x10, 0x2000, 0x2, x1, 120, x4)
inst_44:
// imm_val == 1, imm_val==1
// opcode: auipc ; dest:x10; immval:0x1
TEST_AUIPC(auipc, x10, 0x1000, 0x1, x1, 124, x4)
inst_45:
// imm_val==725,
// opcode: auipc ; dest:x10; immval:0x2d5
TEST_AUIPC(auipc, x10, 0x2d5000, 0x2d5, x1, 128, x4)
inst_46:
// imm_val==419431,
// opcode: auipc ; dest:x10; immval:0x66667
TEST_AUIPC(auipc, x10, 0x66667000, 0x66667, x1, 132, x4)
inst_47:
// imm_val==209716,
// opcode: auipc ; dest:x10; immval:0x33334
TEST_AUIPC(auipc, x10, 0x33334000, 0x33334, x1, 136, x4)
inst_48:
// imm_val==6,
// opcode: auipc ; dest:x10; immval:0x6
TEST_AUIPC(auipc, x10, 0x6000, 0x6, x1, 140, x4)
inst_49:
// imm_val==699051,
// opcode: auipc ; dest:x10; immval:0xaaaab
TEST_AUIPC(auipc, x10, -0x55555000, 0xaaaab, x1, 144, x4)
inst_50:
// imm_val==349526,
// opcode: auipc ; dest:x10; immval:0x55556
TEST_AUIPC(auipc, x10, 0x55556000, 0x55556, x1, 148, x4)
inst_51:
// imm_val==1022,
// opcode: auipc ; dest:x10; immval:0x3fe
TEST_AUIPC(auipc, x10, 0x3fe000, 0x3fe, x1, 152, x4)
inst_52:
// imm_val==723,
// opcode: auipc ; dest:x10; immval:0x2d3
TEST_AUIPC(auipc, x10, 0x2d3000, 0x2d3, x1, 156, x4)
inst_53:
// imm_val==419429,
// opcode: auipc ; dest:x10; immval:0x66665
TEST_AUIPC(auipc, x10, 0x66665000, 0x66665, x1, 160, x4)
inst_54:
// imm_val==209714,
// opcode: auipc ; dest:x10; immval:0x33332
TEST_AUIPC(auipc, x10, 0x33332000, 0x33332, x1, 164, x4)
inst_55:
// imm_val==699049,
// opcode: auipc ; dest:x10; immval:0xaaaa9
TEST_AUIPC(auipc, x10, -0x55557000, 0xaaaa9, x1, 168, x4)
inst_56:
// imm_val==349524,
// opcode: auipc ; dest:x10; immval:0x55554
TEST_AUIPC(auipc, x10, 0x55554000, 0x55554, x1, 172, x4)
inst_57:
// imm_val==1023,
// opcode: auipc ; dest:x10; immval:0x3ff
TEST_AUIPC(auipc, x10, 0x3ff000, 0x3ff, x1, 176, x4)
inst_58:
// imm_val==724,
// opcode: auipc ; dest:x10; immval:0x2d4
TEST_AUIPC(auipc, x10, 0x2d4000, 0x2d4, x1, 180, x4)
inst_59:
// imm_val==419430,
// opcode: auipc ; dest:x10; immval:0x66666
TEST_AUIPC(auipc, x10, 0x66666000, 0x66666, x1, 184, x4)
inst_60:
// imm_val==209715,
// opcode: auipc ; dest:x10; immval:0x33333
TEST_AUIPC(auipc, x10, 0x33333000, 0x33333, x1, 188, x4)
inst_61:
// imm_val==5,
// opcode: auipc ; dest:x10; immval:0x5
TEST_AUIPC(auipc, x10, 0x5000, 0x5, x1, 192, x4)
inst_62:
// imm_val == 1046527,
// opcode: auipc ; dest:x10; immval:0xff7ff
TEST_AUIPC(auipc, x10, -0x801000, 0xff7ff, x1, 196, x4)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
signature_x2_0:
.fill 0*(XLEN/32),4,0xdeadbeef
signature_x2_1:
.fill 13*(XLEN/32),4,0xdeadbeef
signature_x1_0:
.fill 50*(XLEN/32),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

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// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version : 0.5.1
// timestamp : Mon Aug 2 08:58:53 2021 GMT
// usage : riscv_ctg \
// --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/rv32e.cgf \
// --base-isa rv32e \
// --randomize
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the jal instruction of the RISC-V E extension for the jal covergroup.
//
#define RVTEST_E
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32E")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",jal)
RVTEST_SIGBASE( x7,signature_x7_1)
inst_0:
// rd==x8, imm_val < 0,
// opcode: jal; dest:x8; immval:0x4; align:0
TEST_JAL_OP(x2, x8, 0x4, 1b, x7, 0,0)
inst_1:
// rd==x14, imm_val == ((2**(18))), imm_val > 0
// opcode: jal; dest:x14; immval:0x40000; align:0
TEST_JAL_OP(x2, x14, 0x40000, 3f, x7, 4,0)
inst_2:
// rd==x9, imm_val == (-(2**(18))),
// opcode: jal; dest:x9; immval:0x40000; align:0
TEST_JAL_OP(x2, x9, 0x40000, 1b, x7, 8,0)
inst_3:
// rd==x12,
// opcode: jal; dest:x12; immval:0x80000; align:0
TEST_JAL_OP(x2, x12, 0x80000, 1b, x7, 12,0)
inst_4:
// rd==x0,
// opcode: jal; dest:x0; immval:0x80000; align:0
TEST_JAL_OP(x2, x0, 0x80000, 1b, x7, 16,0)
inst_5:
// rd==x3,
// opcode: jal; dest:x3; immval:0x80000; align:0
TEST_JAL_OP(x2, x3, 0x80000, 1b, x7, 20,0)
inst_6:
// rd==x4,
// opcode: jal; dest:x4; immval:0x80000; align:0
TEST_JAL_OP(x2, x4, 0x80000, 1b, x7, 24,0)
inst_7:
// rd==x5,
// opcode: jal; dest:x5; immval:0x80000; align:0
TEST_JAL_OP(x2, x5, 0x80000, 1b, x7, 28,0)
inst_8:
// rd==x13,
// opcode: jal; dest:x13; immval:0x80000; align:0
TEST_JAL_OP(x2, x13, 0x80000, 1b, x7, 32,0)
inst_9:
// rd==x6,
// opcode: jal; dest:x6; immval:0x80000; align:0
TEST_JAL_OP(x2, x6, 0x80000, 1b, x7, 36,0)
inst_10:
// rd==x15,
// opcode: jal; dest:x15; immval:0x80000; align:0
TEST_JAL_OP(x2, x15, 0x80000, 1b, x7, 40,0)
inst_11:
// rd==x1,
// opcode: jal; dest:x1; immval:0x80000; align:0
TEST_JAL_OP(x2, x1, 0x80000, 1b, x7, 44,0)
inst_12:
// rd==x2,
// opcode: jal; dest:x2; immval:0x80000; align:0
TEST_JAL_OP(x3, x2, 0x80000, 1b, x7, 48,0)
RVTEST_SIGBASE( x1,signature_x1_0)
inst_13:
// rd==x7,
// opcode: jal; dest:x7; immval:0x80000; align:0
TEST_JAL_OP(x3, x7, 0x80000, 1b, x1, 0,0)
inst_14:
// rd==x10,
// opcode: jal; dest:x10; immval:0x80000; align:0
TEST_JAL_OP(x3, x10, 0x80000, 1b, x1, 4,0)
inst_15:
// rd==x11,
// opcode: jal; dest:x11; immval:0x80000; align:0
TEST_JAL_OP(x3, x11, 0x80000, 1b, x1, 8,0)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
signature_x7_0:
.fill 0*(XLEN/32),4,0xdeadbeef
signature_x7_1:
.fill 13*(XLEN/32),4,0xdeadbeef
signature_x1_0:
.fill 3*(XLEN/32),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

219
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-jalr-01.S
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@ -1,219 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version : 0.5.1
// timestamp : Mon Aug 2 08:58:53 2021 GMT
// usage : riscv_ctg \
// --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/rv32e.cgf \
// --base-isa rv32e \
// --randomize
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the jalr instruction of the RISC-V E extension for the jalr covergroup.
//
#define RVTEST_E
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32E")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",jalr)
RVTEST_SIGBASE( x1,signature_x1_1)
inst_0:
// rs1 != rd, rs1==x8, rd==x12, imm_val < 0, imm_val == -129
// opcode: jalr; op1:x8; dest:x12; immval:-0x81; align:0
TEST_JALR_OP(x6, x12, x8, -0x81, x1, 0,0)
inst_1:
// rs1 == rd, rs1==x5, rd==x5, imm_val == 2047, imm_val > 0
// opcode: jalr; op1:x5; dest:x5; immval:0x7ff; align:0
TEST_JALR_OP(x6, x5, x5, 0x7ff, x1, 4,0)
inst_2:
// rs1==x3, rd==x15, imm_val == -1025,
// opcode: jalr; op1:x3; dest:x15; immval:-0x401; align:0
TEST_JALR_OP(x6, x15, x3, -0x401, x1, 8,0)
inst_3:
// rs1==x2, rd==x3, imm_val == -513,
// opcode: jalr; op1:x2; dest:x3; immval:-0x201; align:0
TEST_JALR_OP(x6, x3, x2, -0x201, x1, 12,0)
inst_4:
// rs1==x4, rd==x9, imm_val == -257,
// opcode: jalr; op1:x4; dest:x9; immval:-0x101; align:0
TEST_JALR_OP(x6, x9, x4, -0x101, x1, 16,0)
inst_5:
// rs1==x9, rd==x7, imm_val == -65,
// opcode: jalr; op1:x9; dest:x7; immval:-0x41; align:0
TEST_JALR_OP(x6, x7, x9, -0x41, x1, 20,0)
inst_6:
// rs1==x10, rd==x13, imm_val == -33,
// opcode: jalr; op1:x10; dest:x13; immval:-0x21; align:0
TEST_JALR_OP(x6, x13, x10, -0x21, x1, 24,0)
inst_7:
// rs1==x14, rd==x0, imm_val == -17,
// opcode: jalr; op1:x14; dest:x0; immval:-0x11; align:0
TEST_JALR_OP(x5, x0, x14, -0x11, x1, 28,0)
RVTEST_SIGBASE( x3,signature_x3_0)
inst_8:
// rs1==x15, rd==x4, imm_val == -9,
// opcode: jalr; op1:x15; dest:x4; immval:-0x9; align:0
TEST_JALR_OP(x5, x4, x15, -0x9, x3, 0,0)
inst_9:
// rs1==x7, rd==x14, imm_val == -5,
// opcode: jalr; op1:x7; dest:x14; immval:-0x5; align:0
TEST_JALR_OP(x5, x14, x7, -0x5, x3, 4,0)
inst_10:
// rs1==x11, rd==x2, imm_val == -3,
// opcode: jalr; op1:x11; dest:x2; immval:-0x3; align:0
TEST_JALR_OP(x5, x2, x11, -0x3, x3, 8,0)
inst_11:
// rs1==x6, rd==x11, imm_val == -2,
// opcode: jalr; op1:x6; dest:x11; immval:-0x2; align:0
TEST_JALR_OP(x5, x11, x6, -0x2, x3, 12,0)
inst_12:
// rs1==x12, rd==x8, imm_val == -2048,
// opcode: jalr; op1:x12; dest:x8; immval:-0x800; align:0
TEST_JALR_OP(x5, x8, x12, -0x800, x3, 16,0)
inst_13:
// rs1==x13, rd==x1, imm_val == 1024,
// opcode: jalr; op1:x13; dest:x1; immval:0x400; align:0
TEST_JALR_OP(x5, x1, x13, 0x400, x3, 20,0)
inst_14:
// rs1==x1, rd==x10, imm_val == 512,
// opcode: jalr; op1:x1; dest:x10; immval:0x200; align:0
TEST_JALR_OP(x2, x10, x1, 0x200, x3, 24,0)
RVTEST_SIGBASE( x1,signature_x1_2)
inst_15:
// rd==x6, imm_val == 256,
// opcode: jalr; op1:x13; dest:x6; immval:0x100; align:0
TEST_JALR_OP(x2, x6, x13, 0x100, x1, 0,0)
inst_16:
// imm_val == 128,
// opcode: jalr; op1:x10; dest:x11; immval:0x80; align:0
TEST_JALR_OP(x2, x11, x10, 0x80, x1, 4,0)
inst_17:
// imm_val == 64,
// opcode: jalr; op1:x10; dest:x11; immval:0x40; align:0
TEST_JALR_OP(x2, x11, x10, 0x40, x1, 8,0)
inst_18:
// imm_val == 32,
// opcode: jalr; op1:x10; dest:x11; immval:0x20; align:0
TEST_JALR_OP(x2, x11, x10, 0x20, x1, 12,0)
inst_19:
// imm_val == 16,
// opcode: jalr; op1:x10; dest:x11; immval:0x10; align:0
TEST_JALR_OP(x2, x11, x10, 0x10, x1, 16,0)
inst_20:
// imm_val == 8,
// opcode: jalr; op1:x10; dest:x11; immval:0x8; align:0
TEST_JALR_OP(x2, x11, x10, 0x8, x1, 20,0)
inst_21:
// imm_val == 4,
// opcode: jalr; op1:x10; dest:x11; immval:0x4; align:0
TEST_JALR_OP(x2, x11, x10, 0x4, x1, 24,0)
inst_22:
// imm_val == 1,
// opcode: jalr; op1:x10; dest:x11; immval:0x1; align:0
TEST_JALR_OP(x2, x11, x10, 0x1, x1, 28,0)
inst_23:
// imm_val == -1366,
// opcode: jalr; op1:x10; dest:x11; immval:-0x556; align:0
TEST_JALR_OP(x2, x11, x10, -0x556, x1, 32,0)
inst_24:
// imm_val == 1365,
// opcode: jalr; op1:x10; dest:x11; immval:0x555; align:0
TEST_JALR_OP(x2, x11, x10, 0x555, x1, 36,0)
inst_25:
// imm_val == 2,
// opcode: jalr; op1:x10; dest:x11; immval:0x2; align:0
TEST_JALR_OP(x2, x11, x10, 0x2, x1, 40,0)
inst_26:
// imm_val == -17,
// opcode: jalr; op1:x10; dest:x11; immval:-0x11; align:0
TEST_JALR_OP(x2, x11, x10, -0x11, x1, 44,0)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
signature_x1_0:
.fill 0*(XLEN/32),4,0xdeadbeef
signature_x1_1:
.fill 8*(XLEN/32),4,0xdeadbeef
signature_x3_0:
.fill 7*(XLEN/32),4,0xdeadbeef
signature_x1_2:
.fill 12*(XLEN/32),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

169
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lb-align-01.S
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@ -1,169 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version : 0.5.1
// timestamp : Mon Aug 2 08:58:53 2021 GMT
// usage : riscv_ctg \
// --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/rv32e.cgf \
// --base-isa rv32e \
// --randomize
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the lb instruction of the RISC-V E extension for the lb-align covergroup.
//
#define RVTEST_E
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32E")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",lb-align)
RVTEST_SIGBASE( x1,signature_x1_1)
inst_0:
// rs1 != rd, rs1==x8, rd==x9, ea_align == 0 and (imm_val % 4) == 0, imm_val < 0
// opcode:lb op1:x8; dest:x9; immval:-0x4; align:0
TEST_LOAD(x1,x4,0,x8,x9,-0x4,0,lb,0)
inst_1:
// rs1 == rd, rs1==x15, rd==x15, ea_align == 0 and (imm_val % 4) == 1, imm_val > 0
// opcode:lb op1:x15; dest:x15; immval:0x5; align:0
TEST_LOAD(x1,x4,0,x15,x15,0x5,4,lb,0)
inst_2:
// rs1==x2, rd==x8, ea_align == 0 and (imm_val % 4) == 2,
// opcode:lb op1:x2; dest:x8; immval:0x2; align:0
TEST_LOAD(x1,x4,0,x2,x8,0x2,8,lb,0)
inst_3:
// rs1==x11, rd==x7, ea_align == 0 and (imm_val % 4) == 3,
// opcode:lb op1:x11; dest:x7; immval:-0x101; align:0
TEST_LOAD(x1,x4,0,x11,x7,-0x101,12,lb,0)
inst_4:
// rs1==x6, rd==x5, ea_align == 1 and (imm_val % 4) == 0,
// opcode:lb op1:x6; dest:x5; immval:0x4; align:1
TEST_LOAD(x1,x4,0,x6,x5,0x4,16,lb,1)
inst_5:
// rs1==x12, rd==x10, ea_align == 1 and (imm_val % 4) == 1,
// opcode:lb op1:x12; dest:x10; immval:-0x3; align:1
TEST_LOAD(x1,x4,0,x12,x10,-0x3,20,lb,1)
inst_6:
// rs1==x10, rd==x12, ea_align == 1 and (imm_val % 4) == 2,
// opcode:lb op1:x10; dest:x12; immval:-0x2; align:1
TEST_LOAD(x1,x4,0,x10,x12,-0x2,24,lb,1)
inst_7:
// rs1==x9, rd==x6, ea_align == 1 and (imm_val % 4) == 3,
// opcode:lb op1:x9; dest:x6; immval:-0x401; align:1
TEST_LOAD(x1,x4,0,x9,x6,-0x401,28,lb,1)
inst_8:
// rs1==x13, rd==x3, ea_align == 2 and (imm_val % 4) == 0,
// opcode:lb op1:x13; dest:x3; immval:0x40; align:2
TEST_LOAD(x1,x4,0,x13,x3,0x40,32,lb,2)
RVTEST_SIGBASE( x6,signature_x6_0)
inst_9:
// rs1==x4, rd==x1, ea_align == 2 and (imm_val % 4) == 1,
// opcode:lb op1:x4; dest:x1; immval:0x5; align:2
TEST_LOAD(x6,x8,0,x4,x1,0x5,0,lb,2)
inst_10:
// rs1==x1, rd==x11, imm_val == 0,
// opcode:lb op1:x1; dest:x11; immval:0x0; align:0
TEST_LOAD(x6,x8,0,x1,x11,0x0,4,lb,0)
inst_11:
// rs1==x3, rd==x14, ea_align == 2 and (imm_val % 4) == 2,
// opcode:lb op1:x3; dest:x14; immval:0x2; align:2
TEST_LOAD(x6,x8,0,x3,x14,0x2,8,lb,2)
inst_12:
// rs1==x7, rd==x4, ea_align == 2 and (imm_val % 4) == 3,
// opcode:lb op1:x7; dest:x4; immval:-0x1; align:2
TEST_LOAD(x6,x8,0,x7,x4,-0x1,12,lb,2)
inst_13:
// rs1==x14, rd==x0, ea_align == 3 and (imm_val % 4) == 0,
// opcode:lb op1:x14; dest:x0; immval:-0x8; align:3
TEST_LOAD(x6,x8,0,x14,x0,-0x8,16,lb,3)
inst_14:
// rs1==x5, rd==x13, ea_align == 3 and (imm_val % 4) == 1,
// opcode:lb op1:x5; dest:x13; immval:-0x3; align:3
TEST_LOAD(x6,x8,0,x5,x13,-0x3,20,lb,3)
inst_15:
// rd==x2, ea_align == 3 and (imm_val % 4) == 2,
// opcode:lb op1:x5; dest:x2; immval:-0x556; align:3
TEST_LOAD(x6,x8,0,x5,x2,-0x556,24,lb,3)
inst_16:
// ea_align == 3 and (imm_val % 4) == 3,
// opcode:lb op1:x10; dest:x11; immval:-0x401; align:3
TEST_LOAD(x6,x8,0,x10,x11,-0x401,28,lb,3)
inst_17:
// ea_align == 3 and (imm_val % 4) == 0,
// opcode:lb op1:x10; dest:x11; immval:-0x8; align:3
TEST_LOAD(x6,x8,0,x10,x11,-0x8,32,lb,3)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
signature_x1_0:
.fill 0*(XLEN/32),4,0xdeadbeef
signature_x1_1:
.fill 9*(XLEN/32),4,0xdeadbeef
signature_x6_0:
.fill 9*(XLEN/32),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

169
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lbu-align-01.S
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@ -1,169 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version : 0.5.1
// timestamp : Mon Aug 2 08:58:53 2021 GMT
// usage : riscv_ctg \
// --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/rv32e.cgf \
// --base-isa rv32e \
// --randomize
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the lbu instruction of the RISC-V E extension for the lbu-align covergroup.
//
#define RVTEST_E
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32E")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",lbu-align)
RVTEST_SIGBASE( x1,signature_x1_1)
inst_0:
// rs1 != rd, rs1==x14, rd==x0, ea_align == 0 and (imm_val % 4) == 0, imm_val > 0
// opcode:lbu op1:x14; dest:x0; immval:0x100; align:0
TEST_LOAD(x1,x8,0,x14,x0,0x100,0,lbu,0)
inst_1:
// rs1 == rd, rs1==x13, rd==x13, ea_align == 0 and (imm_val % 4) == 1, imm_val < 0
// opcode:lbu op1:x13; dest:x13; immval:-0x7; align:0
TEST_LOAD(x1,x8,0,x13,x13,-0x7,4,lbu,0)
inst_2:
// rs1==x2, rd==x3, ea_align == 0 and (imm_val % 4) == 2,
// opcode:lbu op1:x2; dest:x3; immval:0x6; align:0
TEST_LOAD(x1,x8,0,x2,x3,0x6,8,lbu,0)
inst_3:
// rs1==x5, rd==x11, ea_align == 0 and (imm_val % 4) == 3,
// opcode:lbu op1:x5; dest:x11; immval:-0x9; align:0
TEST_LOAD(x1,x8,0,x5,x11,-0x9,12,lbu,0)
inst_4:
// rs1==x4, rd==x15, ea_align == 1 and (imm_val % 4) == 0,
// opcode:lbu op1:x4; dest:x15; immval:-0x4; align:1
TEST_LOAD(x1,x8,0,x4,x15,-0x4,16,lbu,1)
inst_5:
// rs1==x6, rd==x9, ea_align == 1 and (imm_val % 4) == 1,
// opcode:lbu op1:x6; dest:x9; immval:0x1; align:1
TEST_LOAD(x1,x8,0,x6,x9,0x1,20,lbu,1)
inst_6:
// rs1==x9, rd==x7, ea_align == 1 and (imm_val % 4) == 2,
// opcode:lbu op1:x9; dest:x7; immval:0x6; align:1
TEST_LOAD(x1,x8,0,x9,x7,0x6,24,lbu,1)
inst_7:
// rs1==x10, rd==x8, ea_align == 1 and (imm_val % 4) == 3,
// opcode:lbu op1:x10; dest:x8; immval:-0x201; align:1
TEST_LOAD(x1,x13,0,x10,x8,-0x201,28,lbu,1)
RVTEST_SIGBASE( x9,signature_x9_0)
inst_8:
// rs1==x11, rd==x1, ea_align == 2 and (imm_val % 4) == 0,
// opcode:lbu op1:x11; dest:x1; immval:0x4; align:2
TEST_LOAD(x9,x13,0,x11,x1,0x4,0,lbu,2)
inst_9:
// rs1==x3, rd==x4, ea_align == 2 and (imm_val % 4) == 1,
// opcode:lbu op1:x3; dest:x4; immval:-0x7; align:2
TEST_LOAD(x9,x13,0,x3,x4,-0x7,4,lbu,2)
inst_10:
// rs1==x1, rd==x6, imm_val == 0,
// opcode:lbu op1:x1; dest:x6; immval:0x0; align:0
TEST_LOAD(x9,x13,0,x1,x6,0x0,8,lbu,0)
inst_11:
// rs1==x8, rd==x10, ea_align == 2 and (imm_val % 4) == 2,
// opcode:lbu op1:x8; dest:x10; immval:-0x2; align:2
TEST_LOAD(x9,x13,0,x8,x10,-0x2,12,lbu,2)
inst_12:
// rs1==x12, rd==x2, ea_align == 2 and (imm_val % 4) == 3,
// opcode:lbu op1:x12; dest:x2; immval:-0x401; align:2
TEST_LOAD(x9,x13,0,x12,x2,-0x401,16,lbu,2)
inst_13:
// rs1==x7, rd==x5, ea_align == 3 and (imm_val % 4) == 0,
// opcode:lbu op1:x7; dest:x5; immval:0x4; align:3
TEST_LOAD(x9,x13,0,x7,x5,0x4,20,lbu,3)
inst_14:
// rs1==x15, rd==x14, ea_align == 3 and (imm_val % 4) == 1,
// opcode:lbu op1:x15; dest:x14; immval:0x9; align:3
TEST_LOAD(x9,x2,0,x15,x14,0x9,24,lbu,3)
RVTEST_SIGBASE( x1,signature_x1_2)
inst_15:
// rd==x12, ea_align == 3 and (imm_val % 4) == 2,
// opcode:lbu op1:x14; dest:x12; immval:-0x2; align:3
TEST_LOAD(x1,x2,0,x14,x12,-0x2,0,lbu,3)
inst_16:
// ea_align == 3 and (imm_val % 4) == 3,
// opcode:lbu op1:x10; dest:x11; immval:-0x5; align:3
TEST_LOAD(x1,x2,0,x10,x11,-0x5,4,lbu,3)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
signature_x1_0:
.fill 0*(XLEN/32),4,0xdeadbeef
signature_x1_1:
.fill 8*(XLEN/32),4,0xdeadbeef
signature_x9_0:
.fill 7*(XLEN/32),4,0xdeadbeef
signature_x1_2:
.fill 2*(XLEN/32),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

159
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lh-align-01.S
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@ -1,159 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version : 0.5.1
// timestamp : Mon Aug 2 08:58:53 2021 GMT
// usage : riscv_ctg \
// --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/rv32e.cgf \
// --base-isa rv32e \
// --randomize
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the lh instruction of the RISC-V E extension for the lh-align covergroup.
//
#define RVTEST_E
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32E")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",lh-align)
RVTEST_SIGBASE( x4,signature_x4_1)
inst_0:
// rs1 != rd, rs1==x3, rd==x2, ea_align == 0 and (imm_val % 4) == 0, imm_val == 0
// opcode:lh op1:x3; dest:x2; immval:0x0; align:0
TEST_LOAD(x4,x5,0,x3,x2,0x0,0,lh,0)
inst_1:
// rs1 == rd, rs1==x15, rd==x15, ea_align == 0 and (imm_val % 4) == 1, imm_val > 0
// opcode:lh op1:x15; dest:x15; immval:0x5; align:0
TEST_LOAD(x4,x5,0,x15,x15,0x5,4,lh,0)
inst_2:
// rs1==x12, rd==x14, ea_align == 0 and (imm_val % 4) == 2, imm_val < 0
// opcode:lh op1:x12; dest:x14; immval:-0x556; align:0
TEST_LOAD(x4,x5,0,x12,x14,-0x556,8,lh,0)
inst_3:
// rs1==x14, rd==x8, ea_align == 0 and (imm_val % 4) == 3,
// opcode:lh op1:x14; dest:x8; immval:0x3ff; align:0
TEST_LOAD(x4,x5,0,x14,x8,0x3ff,12,lh,0)
inst_4:
// rs1==x10, rd==x3, ea_align == 2 and (imm_val % 4) == 0,
// opcode:lh op1:x10; dest:x3; immval:-0x8; align:2
TEST_LOAD(x4,x5,0,x10,x3,-0x8,16,lh,2)
inst_5:
// rs1==x6, rd==x1, ea_align == 2 and (imm_val % 4) == 1,
// opcode:lh op1:x6; dest:x1; immval:0x555; align:2
TEST_LOAD(x4,x5,0,x6,x1,0x555,20,lh,2)
inst_6:
// rs1==x13, rd==x6, ea_align == 2 and (imm_val % 4) == 2,
// opcode:lh op1:x13; dest:x6; immval:-0x6; align:2
TEST_LOAD(x4,x5,0,x13,x6,-0x6,24,lh,2)
inst_7:
// rs1==x1, rd==x9, ea_align == 2 and (imm_val % 4) == 3,
// opcode:lh op1:x1; dest:x9; immval:0x7ff; align:2
TEST_LOAD(x4,x5,0,x1,x9,0x7ff,28,lh,2)
inst_8:
// rs1==x9, rd==x0,
// opcode:lh op1:x9; dest:x0; immval:-0x800; align:0
TEST_LOAD(x4,x3,0,x9,x0,-0x800,32,lh,0)
inst_9:
// rs1==x5, rd==x12,
// opcode:lh op1:x5; dest:x12; immval:-0x800; align:0
TEST_LOAD(x4,x3,0,x5,x12,-0x800,36,lh,0)
RVTEST_SIGBASE( x1,signature_x1_0)
inst_10:
// rs1==x8, rd==x11,
// opcode:lh op1:x8; dest:x11; immval:-0x800; align:0
TEST_LOAD(x1,x3,0,x8,x11,-0x800,0,lh,0)
inst_11:
// rs1==x11, rd==x4,
// opcode:lh op1:x11; dest:x4; immval:-0x800; align:0
TEST_LOAD(x1,x3,0,x11,x4,-0x800,4,lh,0)
inst_12:
// rs1==x2, rd==x7,
// opcode:lh op1:x2; dest:x7; immval:-0x800; align:0
TEST_LOAD(x1,x3,0,x2,x7,-0x800,8,lh,0)
inst_13:
// rs1==x4, rd==x10,
// opcode:lh op1:x4; dest:x10; immval:-0x800; align:0
TEST_LOAD(x1,x3,0,x4,x10,-0x800,12,lh,0)
inst_14:
// rs1==x7, rd==x5,
// opcode:lh op1:x7; dest:x5; immval:-0x800; align:0
TEST_LOAD(x1,x3,0,x7,x5,-0x800,16,lh,0)
inst_15:
// rd==x13,
// opcode:lh op1:x12; dest:x13; immval:-0x800; align:0
TEST_LOAD(x1,x3,0,x12,x13,-0x800,20,lh,0)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
signature_x4_0:
.fill 0*(XLEN/32),4,0xdeadbeef
signature_x4_1:
.fill 10*(XLEN/32),4,0xdeadbeef
signature_x1_0:
.fill 6*(XLEN/32),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

164
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lhu-align-01.S
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@ -1,164 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version : 0.5.1
// timestamp : Mon Aug 2 08:58:53 2021 GMT
// usage : riscv_ctg \
// --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/rv32e.cgf \
// --base-isa rv32e \
// --randomize
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the lhu instruction of the RISC-V E extension for the lhu-align covergroup.
//
#define RVTEST_E
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32E")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",lhu-align)
RVTEST_SIGBASE( x7,signature_x7_1)
inst_0:
// rs1 != rd, rs1==x15, rd==x9, ea_align == 0 and (imm_val % 4) == 0, imm_val < 0
// opcode:lhu op1:x15; dest:x9; immval:-0x4; align:0
TEST_LOAD(x7,x1,0,x15,x9,-0x4,0,lhu,0)
inst_1:
// rs1 == rd, rs1==x3, rd==x3, ea_align == 0 and (imm_val % 4) == 1, imm_val > 0
// opcode:lhu op1:x3; dest:x3; immval:0x5; align:0
TEST_LOAD(x7,x1,0,x3,x3,0x5,4,lhu,0)
inst_2:
// rs1==x13, rd==x2, ea_align == 0 and (imm_val % 4) == 2,
// opcode:lhu op1:x13; dest:x2; immval:-0x556; align:0
TEST_LOAD(x7,x1,0,x13,x2,-0x556,8,lhu,0)
inst_3:
// rs1==x4, rd==x11, ea_align == 0 and (imm_val % 4) == 3,
// opcode:lhu op1:x4; dest:x11; immval:-0x5; align:0
TEST_LOAD(x7,x1,0,x4,x11,-0x5,12,lhu,0)
inst_4:
// rs1==x8, rd==x5, ea_align == 2 and (imm_val % 4) == 0,
// opcode:lhu op1:x8; dest:x5; immval:0x80; align:2
TEST_LOAD(x7,x1,0,x8,x5,0x80,16,lhu,2)
inst_5:
// rs1==x6, rd==x10, imm_val == 0,
// opcode:lhu op1:x6; dest:x10; immval:0x0; align:0
TEST_LOAD(x7,x1,0,x6,x10,0x0,20,lhu,0)
inst_6:
// rs1==x10, rd==x1, ea_align == 2 and (imm_val % 4) == 1,
// opcode:lhu op1:x10; dest:x1; immval:0x9; align:2
TEST_LOAD(x7,x2,0,x10,x1,0x9,24,lhu,2)
RVTEST_SIGBASE( x3,signature_x3_0)
inst_7:
// rs1==x1, rd==x13, ea_align == 2 and (imm_val % 4) == 2,
// opcode:lhu op1:x1; dest:x13; immval:-0xa; align:2
TEST_LOAD(x3,x2,0,x1,x13,-0xa,0,lhu,2)
inst_8:
// rs1==x14, rd==x4, ea_align == 2 and (imm_val % 4) == 3,
// opcode:lhu op1:x14; dest:x4; immval:-0x11; align:2
TEST_LOAD(x3,x2,0,x14,x4,-0x11,4,lhu,2)
inst_9:
// rs1==x11, rd==x8,
// opcode:lhu op1:x11; dest:x8; immval:-0x800; align:0
TEST_LOAD(x3,x2,0,x11,x8,-0x800,8,lhu,0)
inst_10:
// rs1==x5, rd==x12,
// opcode:lhu op1:x5; dest:x12; immval:-0x800; align:0
TEST_LOAD(x3,x2,0,x5,x12,-0x800,12,lhu,0)
inst_11:
// rs1==x9, rd==x7,
// opcode:lhu op1:x9; dest:x7; immval:-0x800; align:0
TEST_LOAD(x3,x2,0,x9,x7,-0x800,16,lhu,0)
inst_12:
// rs1==x12, rd==x15,
// opcode:lhu op1:x12; dest:x15; immval:-0x800; align:0
TEST_LOAD(x3,x4,0,x12,x15,-0x800,20,lhu,0)
inst_13:
// rs1==x7, rd==x0,
// opcode:lhu op1:x7; dest:x0; immval:-0x800; align:0
TEST_LOAD(x3,x4,0,x7,x0,-0x800,24,lhu,0)
inst_14:
// rs1==x2, rd==x14,
// opcode:lhu op1:x2; dest:x14; immval:-0x800; align:0
TEST_LOAD(x3,x4,0,x2,x14,-0x800,28,lhu,0)
RVTEST_SIGBASE( x1,signature_x1_0)
inst_15:
// rd==x6,
// opcode:lhu op1:x14; dest:x6; immval:-0x800; align:0
TEST_LOAD(x1,x4,0,x14,x6,-0x800,0,lhu,0)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
signature_x7_0:
.fill 0*(XLEN/32),4,0xdeadbeef
signature_x7_1:
.fill 7*(XLEN/32),4,0xdeadbeef
signature_x3_0:
.fill 8*(XLEN/32),4,0xdeadbeef
signature_x1_0:
.fill 1*(XLEN/32),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

394
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lui-01.S
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@ -1,394 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version : 0.5.1
// timestamp : Mon Aug 2 08:58:53 2021 GMT
// usage : riscv_ctg \
// --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/rv32e.cgf \
// --base-isa rv32e \
// --randomize
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the lui instruction of the RISC-V E extension for the lui covergroup.
//
#define RVTEST_E
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32E")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",lui)
RVTEST_SIGBASE( x4,signature_x4_1)
inst_0:
// rd==x3, imm_val == ((2**20)-1), imm_val > 0
// opcode: lui ; dest:x3; immval:0xfffff
TEST_CASE(x5, x3, -0x1000, x4, 0, lui x3,0xfffff)
inst_1:
// rd==x2, imm_val == 524287,
// opcode: lui ; dest:x2; immval:0x7ffff
TEST_CASE(x5, x2, 0x7ffff000, x4, 4, lui x2,0x7ffff)
inst_2:
// rd==x1, imm_val == 786431,
// opcode: lui ; dest:x1; immval:0xbffff
TEST_CASE(x5, x1, -0x40001000, x4, 8, lui x1,0xbffff)
inst_3:
// rd==x8, imm_val == 917503,
// opcode: lui ; dest:x8; immval:0xdffff
TEST_CASE(x5, x8, -0x20001000, x4, 12, lui x8,0xdffff)
inst_4:
// rd==x14, imm_val == 983039,
// opcode: lui ; dest:x14; immval:0xeffff
TEST_CASE(x5, x14, -0x10001000, x4, 16, lui x14,0xeffff)
inst_5:
// rd==x7, imm_val == 1015807,
// opcode: lui ; dest:x7; immval:0xf7fff
TEST_CASE(x5, x7, -0x8001000, x4, 20, lui x7,0xf7fff)
inst_6:
// rd==x13, imm_val == 1032191,
// opcode: lui ; dest:x13; immval:0xfbfff
TEST_CASE(x5, x13, -0x4001000, x4, 24, lui x13,0xfbfff)
inst_7:
// rd==x12, imm_val == 1040383,
// opcode: lui ; dest:x12; immval:0xfdfff
TEST_CASE(x5, x12, -0x2001000, x4, 28, lui x12,0xfdfff)
inst_8:
// rd==x15, imm_val == 1044479,
// opcode: lui ; dest:x15; immval:0xfefff
TEST_CASE(x5, x15, -0x1001000, x4, 32, lui x15,0xfefff)
inst_9:
// rd==x10, imm_val == 1046527,
// opcode: lui ; dest:x10; immval:0xff7ff
TEST_CASE(x5, x10, -0x801000, x4, 36, lui x10,0xff7ff)
inst_10:
// rd==x6, imm_val == 1047551,
// opcode: lui ; dest:x6; immval:0xffbff
TEST_CASE(x5, x6, -0x401000, x4, 40, lui x6,0xffbff)
inst_11:
// rd==x9, imm_val == 1048063,
// opcode: lui ; dest:x9; immval:0xffdff
TEST_CASE(x2, x9, -0x201000, x4, 44, lui x9,0xffdff)
RVTEST_SIGBASE( x1,signature_x1_0)
inst_12:
// rd==x4, imm_val == 1048319,
// opcode: lui ; dest:x4; immval:0xffeff
TEST_CASE(x2, x4, -0x101000, x1, 0, lui x4,0xffeff)
inst_13:
// rd==x0, imm_val == 1048447,
// opcode: lui ; dest:x0; immval:0xfff7f
TEST_CASE(x2, x0, 0, x1, 4, lui x0,0xfff7f)
inst_14:
// rd==x5, imm_val == 1048511,
// opcode: lui ; dest:x5; immval:0xfffbf
TEST_CASE(x2, x5, -0x41000, x1, 8, lui x5,0xfffbf)
inst_15:
// rd==x11, imm_val == 1048543,
// opcode: lui ; dest:x11; immval:0xfffdf
TEST_CASE(x2, x11, -0x21000, x1, 12, lui x11,0xfffdf)
inst_16:
// imm_val == 1048559,
// opcode: lui ; dest:x10; immval:0xfffef
TEST_CASE(x2, x10, -0x11000, x1, 16, lui x10,0xfffef)
inst_17:
// imm_val == 1048567,
// opcode: lui ; dest:x10; immval:0xffff7
TEST_CASE(x2, x10, -0x9000, x1, 20, lui x10,0xffff7)
inst_18:
// imm_val == 1048571,
// opcode: lui ; dest:x10; immval:0xffffb
TEST_CASE(x2, x10, -0x5000, x1, 24, lui x10,0xffffb)
inst_19:
// imm_val == 1048573,
// opcode: lui ; dest:x10; immval:0xffffd
TEST_CASE(x2, x10, -0x3000, x1, 28, lui x10,0xffffd)
inst_20:
// imm_val == 1048574,
// opcode: lui ; dest:x10; immval:0xffffe
TEST_CASE(x2, x10, -0x2000, x1, 32, lui x10,0xffffe)
inst_21:
// imm_val == 524288,
// opcode: lui ; dest:x10; immval:0x80000
TEST_CASE(x2, x10, -0x80000000, x1, 36, lui x10,0x80000)
inst_22:
// imm_val == 262144,
// opcode: lui ; dest:x10; immval:0x40000
TEST_CASE(x2, x10, 0x40000000, x1, 40, lui x10,0x40000)
inst_23:
// imm_val == 131072,
// opcode: lui ; dest:x10; immval:0x20000
TEST_CASE(x2, x10, 0x20000000, x1, 44, lui x10,0x20000)
inst_24:
// imm_val == 65536,
// opcode: lui ; dest:x10; immval:0x10000
TEST_CASE(x2, x10, 0x10000000, x1, 48, lui x10,0x10000)
inst_25:
// imm_val == 32768,
// opcode: lui ; dest:x10; immval:0x8000
TEST_CASE(x2, x10, 0x8000000, x1, 52, lui x10,0x8000)
inst_26:
// imm_val == 16384,
// opcode: lui ; dest:x10; immval:0x4000
TEST_CASE(x2, x10, 0x4000000, x1, 56, lui x10,0x4000)
inst_27:
// imm_val == 8192,
// opcode: lui ; dest:x10; immval:0x2000
TEST_CASE(x2, x10, 0x2000000, x1, 60, lui x10,0x2000)
inst_28:
// imm_val == 4096,
// opcode: lui ; dest:x10; immval:0x1000
TEST_CASE(x2, x10, 0x1000000, x1, 64, lui x10,0x1000)
inst_29:
// imm_val == 2048,
// opcode: lui ; dest:x10; immval:0x800
TEST_CASE(x2, x10, 0x800000, x1, 68, lui x10,0x800)
inst_30:
// imm_val == 1024, imm_val==1024
// opcode: lui ; dest:x10; immval:0x400
TEST_CASE(x2, x10, 0x400000, x1, 72, lui x10,0x400)
inst_31:
// imm_val == 512,
// opcode: lui ; dest:x10; immval:0x200
TEST_CASE(x2, x10, 0x200000, x1, 76, lui x10,0x200)
inst_32:
// imm_val == 256,
// opcode: lui ; dest:x10; immval:0x100
TEST_CASE(x2, x10, 0x100000, x1, 80, lui x10,0x100)
inst_33:
// imm_val == 128,
// opcode: lui ; dest:x10; immval:0x80
TEST_CASE(x2, x10, 0x80000, x1, 84, lui x10,0x80)
inst_34:
// imm_val == 64,
// opcode: lui ; dest:x10; immval:0x40
TEST_CASE(x2, x10, 0x40000, x1, 88, lui x10,0x40)
inst_35:
// imm_val == 32,
// opcode: lui ; dest:x10; immval:0x20
TEST_CASE(x2, x10, 0x20000, x1, 92, lui x10,0x20)
inst_36:
// imm_val == 16,
// opcode: lui ; dest:x10; immval:0x10
TEST_CASE(x2, x10, 0x10000, x1, 96, lui x10,0x10)
inst_37:
// imm_val==349525, imm_val == 349525
// opcode: lui ; dest:x10; immval:0x55555
TEST_CASE(x2, x10, 0x55555000, x1, 100, lui x10,0x55555)
inst_38:
// imm_val==3,
// opcode: lui ; dest:x10; immval:0x3
TEST_CASE(x2, x10, 0x3000, x1, 104, lui x10,0x3)
inst_39:
// imm_val == 699050, imm_val==699050
// opcode: lui ; dest:x10; immval:0xaaaaa
TEST_CASE(x2, x10, -0x55556000, x1, 108, lui x10,0xaaaaa)
inst_40:
// imm_val == 0, imm_val==0
// opcode: lui ; dest:x10; immval:0x0
TEST_CASE(x2, x10, 0x0, x1, 112, lui x10,0x0)
inst_41:
// imm_val == 8,
// opcode: lui ; dest:x10; immval:0x8
TEST_CASE(x2, x10, 0x8000, x1, 116, lui x10,0x8)
inst_42:
// imm_val == 4, imm_val==4
// opcode: lui ; dest:x10; immval:0x4
TEST_CASE(x2, x10, 0x4000, x1, 120, lui x10,0x4)
inst_43:
// imm_val == 2, imm_val==2
// opcode: lui ; dest:x10; immval:0x2
TEST_CASE(x2, x10, 0x2000, x1, 124, lui x10,0x2)
inst_44:
// imm_val == 1, imm_val==1
// opcode: lui ; dest:x10; immval:0x1
TEST_CASE(x2, x10, 0x1000, x1, 128, lui x10,0x1)
inst_45:
// imm_val==725,
// opcode: lui ; dest:x10; immval:0x2d5
TEST_CASE(x2, x10, 0x2d5000, x1, 132, lui x10,0x2d5)
inst_46:
// imm_val==419431,
// opcode: lui ; dest:x10; immval:0x66667
TEST_CASE(x2, x10, 0x66667000, x1, 136, lui x10,0x66667)
inst_47:
// imm_val==209716,
// opcode: lui ; dest:x10; immval:0x33334
TEST_CASE(x2, x10, 0x33334000, x1, 140, lui x10,0x33334)
inst_48:
// imm_val==6,
// opcode: lui ; dest:x10; immval:0x6
TEST_CASE(x2, x10, 0x6000, x1, 144, lui x10,0x6)
inst_49:
// imm_val==699051,
// opcode: lui ; dest:x10; immval:0xaaaab
TEST_CASE(x2, x10, -0x55555000, x1, 148, lui x10,0xaaaab)
inst_50:
// imm_val==349526,
// opcode: lui ; dest:x10; immval:0x55556
TEST_CASE(x2, x10, 0x55556000, x1, 152, lui x10,0x55556)
inst_51:
// imm_val==1022,
// opcode: lui ; dest:x10; immval:0x3fe
TEST_CASE(x2, x10, 0x3fe000, x1, 156, lui x10,0x3fe)
inst_52:
// imm_val==723,
// opcode: lui ; dest:x10; immval:0x2d3
TEST_CASE(x2, x10, 0x2d3000, x1, 160, lui x10,0x2d3)
inst_53:
// imm_val==419429,
// opcode: lui ; dest:x10; immval:0x66665
TEST_CASE(x2, x10, 0x66665000, x1, 164, lui x10,0x66665)
inst_54:
// imm_val==209714,
// opcode: lui ; dest:x10; immval:0x33332
TEST_CASE(x2, x10, 0x33332000, x1, 168, lui x10,0x33332)
inst_55:
// imm_val==699049,
// opcode: lui ; dest:x10; immval:0xaaaa9
TEST_CASE(x2, x10, -0x55557000, x1, 172, lui x10,0xaaaa9)
inst_56:
// imm_val==349524,
// opcode: lui ; dest:x10; immval:0x55554
TEST_CASE(x2, x10, 0x55554000, x1, 176, lui x10,0x55554)
inst_57:
// imm_val==1023,
// opcode: lui ; dest:x10; immval:0x3ff
TEST_CASE(x2, x10, 0x3ff000, x1, 180, lui x10,0x3ff)
inst_58:
// imm_val==724,
// opcode: lui ; dest:x10; immval:0x2d4
TEST_CASE(x2, x10, 0x2d4000, x1, 184, lui x10,0x2d4)
inst_59:
// imm_val==419430,
// opcode: lui ; dest:x10; immval:0x66666
TEST_CASE(x2, x10, 0x66666000, x1, 188, lui x10,0x66666)
inst_60:
// imm_val==209715,
// opcode: lui ; dest:x10; immval:0x33333
TEST_CASE(x2, x10, 0x33333000, x1, 192, lui x10,0x33333)
inst_61:
// imm_val==5,
// opcode: lui ; dest:x10; immval:0x5
TEST_CASE(x2, x10, 0x5000, x1, 196, lui x10,0x5)
inst_62:
// imm_val == 1048447,
// opcode: lui ; dest:x10; immval:0xfff7f
TEST_CASE(x2, x10, -0x81000, x1, 200, lui x10,0xfff7f)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
signature_x4_0:
.fill 0*(XLEN/32),4,0xdeadbeef
signature_x4_1:
.fill 12*(XLEN/32),4,0xdeadbeef
signature_x1_0:
.fill 51*(XLEN/32),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

164
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lw-align-01.S
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@ -1,164 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version : 0.5.1
// timestamp : Mon Aug 2 08:58:53 2021 GMT
// usage : riscv_ctg \
// --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/rv32e.cgf \
// --base-isa rv32e \
// --randomize
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the lw instruction of the RISC-V E extension for the lw-align covergroup.
//
#define RVTEST_E
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32E")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",lw-align)
RVTEST_SIGBASE( x2,signature_x2_1)
inst_0:
// rs1 != rd, rs1==x11, rd==x1, ea_align == 0 and (imm_val % 4) == 0, imm_val < 0
// opcode:lw op1:x11; dest:x1; immval:-0x400; align:0
TEST_LOAD(x2,x6,0,x11,x1,-0x400,0,lw,0)
inst_1:
// rs1 == rd, rs1==x14, rd==x14, ea_align == 0 and (imm_val % 4) == 1,
// opcode:lw op1:x14; dest:x14; immval:-0x3; align:0
TEST_LOAD(x2,x6,0,x14,x14,-0x3,4,lw,0)
inst_2:
// rs1==x4, rd==x8, ea_align == 0 and (imm_val % 4) == 2,
// opcode:lw op1:x4; dest:x8; immval:-0x556; align:0
TEST_LOAD(x2,x6,0,x4,x8,-0x556,8,lw,0)
inst_3:
// rs1==x1, rd==x10, ea_align == 0 and (imm_val % 4) == 3,
// opcode:lw op1:x1; dest:x10; immval:-0x5; align:0
TEST_LOAD(x2,x6,0,x1,x10,-0x5,12,lw,0)
inst_4:
// rs1==x12, rd==x15, imm_val == 0,
// opcode:lw op1:x12; dest:x15; immval:0x0; align:0
TEST_LOAD(x2,x6,0,x12,x15,0x0,16,lw,0)
inst_5:
// rs1==x7, rd==x13, imm_val > 0,
// opcode:lw op1:x7; dest:x13; immval:0x20; align:0
TEST_LOAD(x2,x6,0,x7,x13,0x20,20,lw,0)
inst_6:
// rs1==x5, rd==x3,
// opcode:lw op1:x5; dest:x3; immval:-0x800; align:0
TEST_LOAD(x2,x6,0,x5,x3,-0x800,24,lw,0)
RVTEST_SIGBASE( x1,signature_x1_0)
inst_7:
// rs1==x8, rd==x0,
// opcode:lw op1:x8; dest:x0; immval:-0x800; align:0
TEST_LOAD(x1,x11,0,x8,x0,-0x800,0,lw,0)
inst_8:
// rs1==x3, rd==x12,
// opcode:lw op1:x3; dest:x12; immval:-0x800; align:0
TEST_LOAD(x1,x11,0,x3,x12,-0x800,4,lw,0)
inst_9:
// rs1==x13, rd==x4,
// opcode:lw op1:x13; dest:x4; immval:-0x800; align:0
TEST_LOAD(x1,x11,0,x13,x4,-0x800,8,lw,0)
inst_10:
// rs1==x15, rd==x7,
// opcode:lw op1:x15; dest:x7; immval:-0x800; align:0
TEST_LOAD(x1,x11,0,x15,x7,-0x800,12,lw,0)
inst_11:
// rs1==x9, rd==x5,
// opcode:lw op1:x9; dest:x5; immval:-0x800; align:0
TEST_LOAD(x1,x11,0,x9,x5,-0x800,16,lw,0)
inst_12:
// rs1==x6, rd==x9,
// opcode:lw op1:x6; dest:x9; immval:-0x800; align:0
TEST_LOAD(x1,x11,0,x6,x9,-0x800,20,lw,0)
inst_13:
// rs1==x10, rd==x2,
// opcode:lw op1:x10; dest:x2; immval:-0x800; align:0
TEST_LOAD(x1,x11,0,x10,x2,-0x800,24,lw,0)
RVTEST_SIGBASE( x1,signature_x1_1)
inst_14:
// rs1==x2, rd==x6,
// opcode:lw op1:x2; dest:x6; immval:-0x800; align:0
TEST_LOAD(x1,x3,0,x2,x6,-0x800,0,lw,0)
inst_15:
// rd==x11,
// opcode:lw op1:x5; dest:x11; immval:-0x800; align:0
TEST_LOAD(x1,x3,0,x5,x11,-0x800,4,lw,0)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
signature_x2_0:
.fill 0*(XLEN/32),4,0xdeadbeef
signature_x2_1:
.fill 7*(XLEN/32),4,0xdeadbeef
signature_x1_0:
.fill 7*(XLEN/32),4,0xdeadbeef
signature_x1_1:
.fill 2*(XLEN/32),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3039
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-or-01.S
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tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-ori-01.S
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469
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sb-align-01.S
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@ -1,469 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version : 0.5.1
// timestamp : Mon Aug 2 08:58:53 2021 GMT
// usage : riscv_ctg \
// --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/rv32e.cgf \
// --base-isa rv32e \
// --randomize
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the sb instruction of the RISC-V E extension for the sb-align covergroup.
//
#define RVTEST_E
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32E")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",sb-align)
RVTEST_SIGBASE( x3,signature_x3_1)
inst_0:
// rs1 != rs2, rs1==x4, rs2==x0, ea_align == 0 and (imm_val % 4) == 0, imm_val > 0
// opcode: sb; op1:x4; op2:x0; op2val:0x0; immval:0x8; align:0
TEST_STORE(x3,x5,0,x4,x0,0x0,0x8,0,sb,0)
inst_1:
// rs1==x8, rs2==x11, rs2_val == 2147483647, imm_val < 0, ea_align == 0 and (imm_val % 4) == 3, rs2_val == (2**(xlen-1)-1)
// opcode: sb; op1:x8; op2:x11; op2val:0x7fffffff; immval:-0x41; align:0
TEST_STORE(x3,x5,0,x8,x11,0x7fffffff,-0x41,4,sb,0)
inst_2:
// rs1==x1, rs2==x15, rs2_val == -1073741825,
// opcode: sb; op1:x1; op2:x15; op2val:-0x40000001; immval:-0x11; align:0
TEST_STORE(x3,x5,0,x1,x15,-0x40000001,-0x11,8,sb,0)
inst_3:
// rs1==x14, rs2==x2, rs2_val == -536870913,
// opcode: sb; op1:x14; op2:x2; op2val:-0x20000001; immval:-0x101; align:0
TEST_STORE(x3,x5,0,x14,x2,-0x20000001,-0x101,12,sb,0)
inst_4:
// rs1==x15, rs2==x8, rs2_val == -268435457, ea_align == 0 and (imm_val % 4) == 1
// opcode: sb; op1:x15; op2:x8; op2val:-0x10000001; immval:-0x3; align:0
TEST_STORE(x3,x5,0,x15,x8,-0x10000001,-0x3,16,sb,0)
inst_5:
// rs1==x6, rs2==x7, rs2_val == -134217729,
// opcode: sb; op1:x6; op2:x7; op2val:-0x8000001; immval:-0x8; align:0
TEST_STORE(x3,x5,0,x6,x7,-0x8000001,-0x8,20,sb,0)
inst_6:
// rs1==x2, rs2==x10, rs2_val == -67108865,
// opcode: sb; op1:x2; op2:x10; op2val:-0x4000001; immval:0x7ff; align:0
TEST_STORE(x3,x5,0,x2,x10,-0x4000001,0x7ff,24,sb,0)
inst_7:
// rs1==x13, rs2==x6, rs2_val == -33554433,
// opcode: sb; op1:x13; op2:x6; op2val:-0x2000001; immval:0x555; align:0
TEST_STORE(x3,x5,0,x13,x6,-0x2000001,0x555,28,sb,0)
inst_8:
// rs1==x7, rs2==x4, rs2_val == -16777217,
// opcode: sb; op1:x7; op2:x4; op2val:-0x1000001; immval:0x100; align:0
TEST_STORE(x3,x2,0,x7,x4,-0x1000001,0x100,32,sb,0)
inst_9:
// rs1==x9, rs2==x1, rs2_val == -8388609,
// opcode: sb; op1:x9; op2:x1; op2val:-0x800001; immval:-0x3; align:0
TEST_STORE(x3,x2,0,x9,x1,-0x800001,-0x3,36,sb,0)
RVTEST_SIGBASE( x1,signature_x1_0)
inst_10:
// rs1==x10, rs2==x12, rs2_val == -4194305,
// opcode: sb; op1:x10; op2:x12; op2val:-0x400001; immval:0x1; align:0
TEST_STORE(x1,x2,0,x10,x12,-0x400001,0x1,0,sb,0)
inst_11:
// rs1==x3, rs2==x13, rs2_val == -2097153,
// opcode: sb; op1:x3; op2:x13; op2val:-0x200001; immval:0x80; align:0
TEST_STORE(x1,x2,0,x3,x13,-0x200001,0x80,4,sb,0)
inst_12:
// rs1==x11, rs2==x5, rs2_val == -1048577,
// opcode: sb; op1:x11; op2:x5; op2val:-0x100001; immval:-0x401; align:0
TEST_STORE(x1,x2,0,x11,x5,-0x100001,-0x401,8,sb,0)
inst_13:
// rs1==x5, rs2==x9, rs2_val == -524289,
// opcode: sb; op1:x5; op2:x9; op2val:-0x80001; immval:-0x800; align:0
TEST_STORE(x1,x2,0,x5,x9,-0x80001,-0x800,12,sb,0)
inst_14:
// rs1==x12, rs2==x3, rs2_val == -262145,
// opcode: sb; op1:x12; op2:x3; op2val:-0x40001; immval:-0x9; align:0
TEST_STORE(x1,x2,0,x12,x3,-0x40001,-0x9,16,sb,0)
inst_15:
// rs2==x14, rs2_val == -131073,
// opcode: sb; op1:x4; op2:x14; op2val:-0x20001; immval:0x8; align:0
TEST_STORE(x1,x2,0,x4,x14,-0x20001,0x8,20,sb,0)
inst_16:
// rs2_val == -65537,
// opcode: sb; op1:x10; op2:x11; op2val:-0x10001; immval:-0x800; align:0
TEST_STORE(x1,x2,0,x10,x11,-0x10001,-0x800,24,sb,0)
inst_17:
// rs2_val == -32769,
// opcode: sb; op1:x10; op2:x11; op2val:-0x8001; immval:0x9; align:0
TEST_STORE(x1,x2,0,x10,x11,-0x8001,0x9,28,sb,0)
inst_18:
// rs2_val == -16385, ea_align == 0 and (imm_val % 4) == 2
// opcode: sb; op1:x10; op2:x11; op2val:-0x4001; immval:-0x556; align:0
TEST_STORE(x1,x2,0,x10,x11,-0x4001,-0x556,32,sb,0)
inst_19:
// rs2_val == -8193,
// opcode: sb; op1:x10; op2:x11; op2val:-0x2001; immval:0x7ff; align:0
TEST_STORE(x1,x2,0,x10,x11,-0x2001,0x7ff,36,sb,0)
inst_20:
// rs2_val == -4097,
// opcode: sb; op1:x10; op2:x11; op2val:-0x1001; immval:0x7; align:0
TEST_STORE(x1,x2,0,x10,x11,-0x1001,0x7,40,sb,0)
inst_21:
// rs2_val == -2049,
// opcode: sb; op1:x10; op2:x11; op2val:-0x801; immval:-0x800; align:0
TEST_STORE(x1,x2,0,x10,x11,-0x801,-0x800,44,sb,0)
inst_22:
// rs2_val == -1025,
// opcode: sb; op1:x10; op2:x11; op2val:-0x401; immval:0x9; align:0
TEST_STORE(x1,x2,0,x10,x11,-0x401,0x9,48,sb,0)
inst_23:
// rs2_val == -513,
// opcode: sb; op1:x10; op2:x11; op2val:-0x201; immval:-0x3; align:0
TEST_STORE(x1,x2,0,x10,x11,-0x201,-0x3,52,sb,0)
inst_24:
// rs2_val == -257,
// opcode: sb; op1:x10; op2:x11; op2val:-0x101; immval:-0x41; align:0
TEST_STORE(x1,x2,0,x10,x11,-0x101,-0x41,56,sb,0)
inst_25:
// rs2_val == -129,
// opcode: sb; op1:x10; op2:x11; op2val:-0x81; immval:0x2; align:0
TEST_STORE(x1,x2,0,x10,x11,-0x81,0x2,60,sb,0)
inst_26:
// rs2_val == -65,
// opcode: sb; op1:x10; op2:x11; op2val:-0x41; immval:-0xa; align:0
TEST_STORE(x1,x2,0,x10,x11,-0x41,-0xa,64,sb,0)
inst_27:
// rs2_val == -33,
// opcode: sb; op1:x10; op2:x11; op2val:-0x21; immval:-0x41; align:0
TEST_STORE(x1,x2,0,x10,x11,-0x21,-0x41,68,sb,0)
inst_28:
// rs2_val == -17,
// opcode: sb; op1:x10; op2:x11; op2val:-0x11; immval:0x3; align:0
TEST_STORE(x1,x2,0,x10,x11,-0x11,0x3,72,sb,0)
inst_29:
// rs2_val == -9,
// opcode: sb; op1:x10; op2:x11; op2val:-0x9; immval:0x10; align:0
TEST_STORE(x1,x2,0,x10,x11,-0x9,0x10,76,sb,0)
inst_30:
// rs2_val == -5,
// opcode: sb; op1:x10; op2:x11; op2val:-0x5; immval:-0x7; align:0
TEST_STORE(x1,x2,0,x10,x11,-0x5,-0x7,80,sb,0)
inst_31:
// rs2_val == -3,
// opcode: sb; op1:x10; op2:x11; op2val:-0x3; immval:0x555; align:0
TEST_STORE(x1,x2,0,x10,x11,-0x3,0x555,84,sb,0)
inst_32:
// rs2_val == -2,
// opcode: sb; op1:x10; op2:x11; op2val:-0x2; immval:-0xa; align:0
TEST_STORE(x1,x2,0,x10,x11,-0x2,-0xa,88,sb,0)
inst_33:
// rs2_val == -2147483648, rs2_val == (-2**(xlen-1))
// opcode: sb; op1:x10; op2:x11; op2val:-0x80000000; immval:-0x8; align:0
TEST_STORE(x1,x2,0,x10,x11,-0x80000000,-0x8,92,sb,0)
inst_34:
// rs2_val == 1073741824,
// opcode: sb; op1:x10; op2:x11; op2val:0x40000000; immval:-0x5; align:0
TEST_STORE(x1,x2,0,x10,x11,0x40000000,-0x5,96,sb,0)
inst_35:
// rs2_val == 536870912,
// opcode: sb; op1:x10; op2:x11; op2val:0x20000000; immval:-0x41; align:0
TEST_STORE(x1,x2,0,x10,x11,0x20000000,-0x41,100,sb,0)
inst_36:
// rs2_val == 268435456,
// opcode: sb; op1:x10; op2:x11; op2val:0x10000000; immval:-0xa; align:0
TEST_STORE(x1,x2,0,x10,x11,0x10000000,-0xa,104,sb,0)
inst_37:
// rs2_val == 134217728,
// opcode: sb; op1:x10; op2:x11; op2val:0x8000000; immval:0x555; align:0
TEST_STORE(x1,x2,0,x10,x11,0x8000000,0x555,108,sb,0)
inst_38:
// rs2_val == 67108864,
// opcode: sb; op1:x10; op2:x11; op2val:0x4000000; immval:-0x81; align:0
TEST_STORE(x1,x2,0,x10,x11,0x4000000,-0x81,112,sb,0)
inst_39:
// rs2_val == 33554432,
// opcode: sb; op1:x10; op2:x11; op2val:0x2000000; immval:-0x400; align:0
TEST_STORE(x1,x2,0,x10,x11,0x2000000,-0x400,116,sb,0)
inst_40:
// rs2_val == 16777216,
// opcode: sb; op1:x10; op2:x11; op2val:0x1000000; immval:-0x41; align:0
TEST_STORE(x1,x2,0,x10,x11,0x1000000,-0x41,120,sb,0)
inst_41:
// rs2_val == 8388608,
// opcode: sb; op1:x10; op2:x11; op2val:0x800000; immval:-0x5; align:0
TEST_STORE(x1,x2,0,x10,x11,0x800000,-0x5,124,sb,0)
inst_42:
// rs2_val == 4194304,
// opcode: sb; op1:x10; op2:x11; op2val:0x400000; immval:-0x9; align:0
TEST_STORE(x1,x2,0,x10,x11,0x400000,-0x9,128,sb,0)
inst_43:
// rs2_val == 2097152,
// opcode: sb; op1:x10; op2:x11; op2val:0x200000; immval:0x7ff; align:0
TEST_STORE(x1,x2,0,x10,x11,0x200000,0x7ff,132,sb,0)
inst_44:
// rs2_val == 1048576,
// opcode: sb; op1:x10; op2:x11; op2val:0x100000; immval:-0x41; align:0
TEST_STORE(x1,x2,0,x10,x11,0x100000,-0x41,136,sb,0)
inst_45:
// rs2_val == 524288,
// opcode: sb; op1:x10; op2:x11; op2val:0x80000; immval:-0x3; align:0
TEST_STORE(x1,x2,0,x10,x11,0x80000,-0x3,140,sb,0)
inst_46:
// rs2_val == 262144,
// opcode: sb; op1:x10; op2:x11; op2val:0x40000; immval:0x6; align:0
TEST_STORE(x1,x2,0,x10,x11,0x40000,0x6,144,sb,0)
inst_47:
// rs2_val == 131072,
// opcode: sb; op1:x10; op2:x11; op2val:0x20000; immval:0x80; align:0
TEST_STORE(x1,x2,0,x10,x11,0x20000,0x80,148,sb,0)
inst_48:
// rs2_val == 65536,
// opcode: sb; op1:x10; op2:x11; op2val:0x10000; immval:0x555; align:0
TEST_STORE(x1,x2,0,x10,x11,0x10000,0x555,152,sb,0)
inst_49:
// rs2_val == 32768,
// opcode: sb; op1:x10; op2:x11; op2val:0x8000; immval:0x5; align:0
TEST_STORE(x1,x2,0,x10,x11,0x8000,0x5,156,sb,0)
inst_50:
// rs2_val == 1,
// opcode: sb; op1:x10; op2:x11; op2val:0x1; immval:0x400; align:0
TEST_STORE(x1,x2,0,x10,x11,0x1,0x400,160,sb,0)
inst_51:
// rs2_val == -1431655766,
// opcode: sb; op1:x10; op2:x11; op2val:-0x55555556; immval:-0x6; align:0
TEST_STORE(x1,x2,0,x10,x11,-0x55555556,-0x6,164,sb,0)
inst_52:
// rs2_val == 1431655765,
// opcode: sb; op1:x10; op2:x11; op2val:0x55555555; immval:0x555; align:0
TEST_STORE(x1,x2,0,x10,x11,0x55555555,0x555,168,sb,0)
inst_53:
// ea_align == 1 and (imm_val % 4) == 0,
// opcode: sb; op1:x10; op2:x11; op2val:-0x5; immval:0x20; align:1
TEST_STORE(x1,x2,0,x10,x11,-0x5,0x20,172,sb,1)
inst_54:
// ea_align == 1 and (imm_val % 4) == 1,
// opcode: sb; op1:x10; op2:x11; op2val:-0x101; immval:0x5; align:1
TEST_STORE(x1,x2,0,x10,x11,-0x101,0x5,176,sb,1)
inst_55:
// ea_align == 1 and (imm_val % 4) == 2, rs2_val == 8
// opcode: sb; op1:x10; op2:x11; op2val:0x8; immval:-0x2; align:1
TEST_STORE(x1,x2,0,x10,x11,0x8,-0x2,180,sb,1)
inst_56:
// ea_align == 1 and (imm_val % 4) == 3,
// opcode: sb; op1:x10; op2:x11; op2val:-0x8; immval:-0x201; align:1
TEST_STORE(x1,x2,0,x10,x11,-0x8,-0x201,184,sb,1)
inst_57:
// ea_align == 2 and (imm_val % 4) == 0,
// opcode: sb; op1:x10; op2:x11; op2val:0x2000000; immval:-0x400; align:2
TEST_STORE(x1,x2,0,x10,x11,0x2000000,-0x400,188,sb,2)
inst_58:
// ea_align == 2 and (imm_val % 4) == 1,
// opcode: sb; op1:x10; op2:x11; op2val:-0x41; immval:0x9; align:2
TEST_STORE(x1,x2,0,x10,x11,-0x41,0x9,192,sb,2)
inst_59:
// ea_align == 2 and (imm_val % 4) == 2,
// opcode: sb; op1:x10; op2:x11; op2val:-0x8; immval:0x2; align:2
TEST_STORE(x1,x2,0,x10,x11,-0x8,0x2,196,sb,2)
inst_60:
// ea_align == 2 and (imm_val % 4) == 3,
// opcode: sb; op1:x10; op2:x11; op2val:0x9; immval:-0x5; align:2
TEST_STORE(x1,x2,0,x10,x11,0x9,-0x5,200,sb,2)
inst_61:
// ea_align == 3 and (imm_val % 4) == 0, rs2_val == 16
// opcode: sb; op1:x10; op2:x11; op2val:0x10; immval:0x400; align:3
TEST_STORE(x1,x2,0,x10,x11,0x10,0x400,204,sb,3)
inst_62:
// ea_align == 3 and (imm_val % 4) == 1,
// opcode: sb; op1:x10; op2:x11; op2val:-0x200001; immval:0x555; align:3
TEST_STORE(x1,x2,0,x10,x11,-0x200001,0x555,208,sb,3)
inst_63:
// ea_align == 3 and (imm_val % 4) == 2,
// opcode: sb; op1:x10; op2:x11; op2val:0x10000000; immval:-0x556; align:3
TEST_STORE(x1,x2,0,x10,x11,0x10000000,-0x556,212,sb,3)
inst_64:
// rs2_val == 64,
// opcode: sb; op1:x10; op2:x11; op2val:0x40; immval:0x20; align:0
TEST_STORE(x1,x2,0,x10,x11,0x40,0x20,216,sb,0)
inst_65:
// ea_align == 3 and (imm_val % 4) == 3,
// opcode: sb; op1:x10; op2:x11; op2val:0x8000; immval:0x3ff; align:3
TEST_STORE(x1,x2,0,x10,x11,0x8000,0x3ff,220,sb,3)
inst_66:
// rs2_val == 16384, imm_val == 0
// opcode: sb; op1:x10; op2:x11; op2val:0x4000; immval:0x0; align:0
TEST_STORE(x1,x2,0,x10,x11,0x4000,0x0,224,sb,0)
inst_67:
// rs2_val == 8192,
// opcode: sb; op1:x10; op2:x11; op2val:0x2000; immval:0x40; align:0
TEST_STORE(x1,x2,0,x10,x11,0x2000,0x40,228,sb,0)
inst_68:
// rs2_val == 4096,
// opcode: sb; op1:x10; op2:x11; op2val:0x1000; immval:0x9; align:0
TEST_STORE(x1,x2,0,x10,x11,0x1000,0x9,232,sb,0)
inst_69:
// rs2_val == 2048,
// opcode: sb; op1:x10; op2:x11; op2val:0x800; immval:-0x556; align:0
TEST_STORE(x1,x2,0,x10,x11,0x800,-0x556,236,sb,0)
inst_70:
// rs2_val == 512,
// opcode: sb; op1:x10; op2:x11; op2val:0x200; immval:0x5; align:0
TEST_STORE(x1,x2,0,x10,x11,0x200,0x5,240,sb,0)
inst_71:
// rs2_val == 1024,
// opcode: sb; op1:x10; op2:x11; op2val:0x400; immval:-0x11; align:0
TEST_STORE(x1,x2,0,x10,x11,0x400,-0x11,244,sb,0)
inst_72:
// rs2_val == 0,
// opcode: sb; op1:x10; op2:x11; op2val:0x0; immval:-0x11; align:0
TEST_STORE(x1,x2,0,x10,x11,0x0,-0x11,248,sb,0)
inst_73:
// rs2_val == 256,
// opcode: sb; op1:x10; op2:x11; op2val:0x100; immval:0x80; align:0
TEST_STORE(x1,x2,0,x10,x11,0x100,0x80,252,sb,0)
inst_74:
// rs2_val == 128,
// opcode: sb; op1:x10; op2:x11; op2val:0x80; immval:0x7; align:0
TEST_STORE(x1,x2,0,x10,x11,0x80,0x7,256,sb,0)
inst_75:
// rs2_val == 32,
// opcode: sb; op1:x10; op2:x11; op2val:0x20; immval:0x200; align:0
TEST_STORE(x1,x2,0,x10,x11,0x20,0x200,260,sb,0)
inst_76:
// rs2_val == 4,
// opcode: sb; op1:x10; op2:x11; op2val:0x4; immval:0x3; align:0
TEST_STORE(x1,x2,0,x10,x11,0x4,0x3,264,sb,0)
inst_77:
// rs2_val == 2,
// opcode: sb; op1:x10; op2:x11; op2val:0x2; immval:0x400; align:0
TEST_STORE(x1,x2,0,x10,x11,0x2,0x400,268,sb,0)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
signature_x3_0:
.fill 0*(XLEN/32),4,0xdeadbeef
signature_x3_1:
.fill 10*(XLEN/32),4,0xdeadbeef
signature_x1_0:
.fill 68*(XLEN/32),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

439
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sh-align-01.S
View File

@ -1,439 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version : 0.5.1
// timestamp : Mon Aug 2 08:58:53 2021 GMT
// usage : riscv_ctg \
// --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/rv32e.cgf \
// --base-isa rv32e \
// --randomize
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the sh instruction of the RISC-V E extension for the sh-align covergroup.
//
#define RVTEST_E
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32E")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",sh-align)
RVTEST_SIGBASE( x8,signature_x8_1)
inst_0:
// rs1 != rs2, rs1==x6, rs2==x4, ea_align == 0 and (imm_val % 4) == 0, rs2_val == 1, imm_val > 0
// opcode: sh; op1:x6; op2:x4; op2val:0x1; immval:0x4; align:0
TEST_STORE(x8,x12,0,x6,x4,0x1,0x4,0,sh,0)
inst_1:
// rs1==x10, rs2==x5, rs2_val == 2147483647, imm_val == 0, rs2_val == (2**(xlen-1)-1)
// opcode: sh; op1:x10; op2:x5; op2val:0x7fffffff; immval:0x0; align:0
TEST_STORE(x8,x12,0,x10,x5,0x7fffffff,0x0,4,sh,0)
inst_2:
// rs1==x9, rs2==x10, rs2_val == -1073741825, ea_align == 0 and (imm_val % 4) == 2
// opcode: sh; op1:x9; op2:x10; op2val:-0x40000001; immval:0x2; align:0
TEST_STORE(x8,x12,0,x9,x10,-0x40000001,0x2,8,sh,0)
inst_3:
// rs1==x2, rs2==x11, rs2_val == -536870913, imm_val < 0
// opcode: sh; op1:x2; op2:x11; op2val:-0x20000001; immval:-0x8; align:0
TEST_STORE(x8,x12,0,x2,x11,-0x20000001,-0x8,12,sh,0)
inst_4:
// rs1==x13, rs2==x1, rs2_val == -268435457,
// opcode: sh; op1:x13; op2:x1; op2val:-0x10000001; immval:0x8; align:0
TEST_STORE(x8,x12,0,x13,x1,-0x10000001,0x8,16,sh,0)
inst_5:
// rs1==x7, rs2==x3, rs2_val == -134217729,
// opcode: sh; op1:x7; op2:x3; op2val:-0x8000001; immval:0x80; align:0
TEST_STORE(x8,x12,0,x7,x3,-0x8000001,0x80,20,sh,0)
inst_6:
// rs1==x3, rs2==x6, rs2_val == -67108865,
// opcode: sh; op1:x3; op2:x6; op2val:-0x4000001; immval:0x6; align:0
TEST_STORE(x8,x9,0,x3,x6,-0x4000001,0x6,24,sh,0)
inst_7:
// rs1==x12, rs2==x2, rs2_val == -33554433, ea_align == 0 and (imm_val % 4) == 3
// opcode: sh; op1:x12; op2:x2; op2val:-0x2000001; immval:0x7; align:0
TEST_STORE(x8,x9,0,x12,x2,-0x2000001,0x7,28,sh,0)
RVTEST_SIGBASE( x2,signature_x2_0)
inst_8:
// rs1==x5, rs2==x13, rs2_val == -16777217,
// opcode: sh; op1:x5; op2:x13; op2val:-0x1000001; immval:-0x800; align:0
TEST_STORE(x2,x9,0,x5,x13,-0x1000001,-0x800,0,sh,0)
inst_9:
// rs1==x1, rs2==x15, rs2_val == -8388609,
// opcode: sh; op1:x1; op2:x15; op2val:-0x800001; immval:0x3; align:0
TEST_STORE(x2,x9,0,x1,x15,-0x800001,0x3,4,sh,0)
inst_10:
// rs1==x15, rs2==x7, rs2_val == -4194305,
// opcode: sh; op1:x15; op2:x7; op2val:-0x400001; immval:0x40; align:0
TEST_STORE(x2,x9,0,x15,x7,-0x400001,0x40,8,sh,0)
inst_11:
// rs1==x14, rs2==x12, rs2_val == -2097153, ea_align == 0 and (imm_val % 4) == 1
// opcode: sh; op1:x14; op2:x12; op2val:-0x200001; immval:0x5; align:0
TEST_STORE(x2,x9,0,x14,x12,-0x200001,0x5,12,sh,0)
inst_12:
// rs1==x4, rs2==x14, rs2_val == -1048577,
// opcode: sh; op1:x4; op2:x14; op2val:-0x100001; immval:-0x41; align:0
TEST_STORE(x2,x9,0,x4,x14,-0x100001,-0x41,16,sh,0)
inst_13:
// rs1==x11, rs2==x0, rs2_val == -524289,
// opcode: sh; op1:x11; op2:x0; op2val:0x0; immval:-0x5; align:0
TEST_STORE(x2,x3,0,x11,x0,0x0,-0x5,20,sh,0)
inst_14:
// rs1==x8, rs2==x9, rs2_val == -262145,
// opcode: sh; op1:x8; op2:x9; op2val:-0x40001; immval:-0x400; align:0
TEST_STORE(x2,x3,0,x8,x9,-0x40001,-0x400,24,sh,0)
inst_15:
// rs2==x8, rs2_val == -131073,
// opcode: sh; op1:x11; op2:x8; op2val:-0x20001; immval:0x20; align:0
TEST_STORE(x2,x3,0,x11,x8,-0x20001,0x20,28,sh,0)
inst_16:
// rs2_val == -65537,
// opcode: sh; op1:x10; op2:x11; op2val:-0x10001; immval:-0x9; align:0
TEST_STORE(x2,x3,0,x10,x11,-0x10001,-0x9,32,sh,0)
RVTEST_SIGBASE( x1,signature_x1_0)
inst_17:
// rs2_val == -32769,
// opcode: sh; op1:x10; op2:x11; op2val:-0x8001; immval:-0x9; align:0
TEST_STORE(x1,x3,0,x10,x11,-0x8001,-0x9,0,sh,0)
inst_18:
// rs2_val == -16385,
// opcode: sh; op1:x10; op2:x11; op2val:-0x4001; immval:0x0; align:0
TEST_STORE(x1,x3,0,x10,x11,-0x4001,0x0,4,sh,0)
inst_19:
// rs2_val == -8193,
// opcode: sh; op1:x10; op2:x11; op2val:-0x2001; immval:-0x2; align:0
TEST_STORE(x1,x3,0,x10,x11,-0x2001,-0x2,8,sh,0)
inst_20:
// rs2_val == -4097,
// opcode: sh; op1:x10; op2:x11; op2val:-0x1001; immval:0x10; align:0
TEST_STORE(x1,x3,0,x10,x11,-0x1001,0x10,12,sh,0)
inst_21:
// rs2_val == -2049,
// opcode: sh; op1:x10; op2:x11; op2val:-0x801; immval:-0x556; align:0
TEST_STORE(x1,x3,0,x10,x11,-0x801,-0x556,16,sh,0)
inst_22:
// rs2_val == -1025,
// opcode: sh; op1:x10; op2:x11; op2val:-0x401; immval:-0x8; align:0
TEST_STORE(x1,x3,0,x10,x11,-0x401,-0x8,20,sh,0)
inst_23:
// rs2_val == -513,
// opcode: sh; op1:x10; op2:x11; op2val:-0x201; immval:-0x800; align:0
TEST_STORE(x1,x3,0,x10,x11,-0x201,-0x800,24,sh,0)
inst_24:
// rs2_val == -257,
// opcode: sh; op1:x10; op2:x11; op2val:-0x101; immval:-0x2; align:0
TEST_STORE(x1,x3,0,x10,x11,-0x101,-0x2,28,sh,0)
inst_25:
// rs2_val == -129,
// opcode: sh; op1:x10; op2:x11; op2val:-0x81; immval:0x40; align:0
TEST_STORE(x1,x3,0,x10,x11,-0x81,0x40,32,sh,0)
inst_26:
// rs2_val == -65,
// opcode: sh; op1:x10; op2:x11; op2val:-0x41; immval:0x100; align:0
TEST_STORE(x1,x3,0,x10,x11,-0x41,0x100,36,sh,0)
inst_27:
// rs2_val == -33,
// opcode: sh; op1:x10; op2:x11; op2val:-0x21; immval:-0x81; align:0
TEST_STORE(x1,x3,0,x10,x11,-0x21,-0x81,40,sh,0)
inst_28:
// rs2_val == -17,
// opcode: sh; op1:x10; op2:x11; op2val:-0x11; immval:-0x401; align:0
TEST_STORE(x1,x3,0,x10,x11,-0x11,-0x401,44,sh,0)
inst_29:
// rs2_val == -9,
// opcode: sh; op1:x10; op2:x11; op2val:-0x9; immval:-0x800; align:0
TEST_STORE(x1,x3,0,x10,x11,-0x9,-0x800,48,sh,0)
inst_30:
// rs2_val == -5,
// opcode: sh; op1:x10; op2:x11; op2val:-0x5; immval:-0x800; align:0
TEST_STORE(x1,x3,0,x10,x11,-0x5,-0x800,52,sh,0)
inst_31:
// rs2_val == -3,
// opcode: sh; op1:x10; op2:x11; op2val:-0x3; immval:0x200; align:0
TEST_STORE(x1,x3,0,x10,x11,-0x3,0x200,56,sh,0)
inst_32:
// rs2_val == -2,
// opcode: sh; op1:x10; op2:x11; op2val:-0x2; immval:-0x21; align:0
TEST_STORE(x1,x3,0,x10,x11,-0x2,-0x21,60,sh,0)
inst_33:
// rs2_val == -2147483648, rs2_val == (-2**(xlen-1))
// opcode: sh; op1:x10; op2:x11; op2val:-0x80000000; immval:0x40; align:0
TEST_STORE(x1,x3,0,x10,x11,-0x80000000,0x40,64,sh,0)
inst_34:
// rs2_val == 1073741824,
// opcode: sh; op1:x10; op2:x11; op2val:0x40000000; immval:-0x101; align:0
TEST_STORE(x1,x3,0,x10,x11,0x40000000,-0x101,68,sh,0)
inst_35:
// rs2_val == 536870912,
// opcode: sh; op1:x10; op2:x11; op2val:0x20000000; immval:0x2; align:0
TEST_STORE(x1,x3,0,x10,x11,0x20000000,0x2,72,sh,0)
inst_36:
// rs2_val == 268435456,
// opcode: sh; op1:x10; op2:x11; op2val:0x10000000; immval:-0x401; align:0
TEST_STORE(x1,x3,0,x10,x11,0x10000000,-0x401,76,sh,0)
inst_37:
// rs2_val == 134217728,
// opcode: sh; op1:x10; op2:x11; op2val:0x8000000; immval:-0xa; align:0
TEST_STORE(x1,x3,0,x10,x11,0x8000000,-0xa,80,sh,0)
inst_38:
// rs2_val == 67108864,
// opcode: sh; op1:x10; op2:x11; op2val:0x4000000; immval:0x200; align:0
TEST_STORE(x1,x3,0,x10,x11,0x4000000,0x200,84,sh,0)
inst_39:
// rs2_val == 33554432,
// opcode: sh; op1:x10; op2:x11; op2val:0x2000000; immval:-0x81; align:0
TEST_STORE(x1,x3,0,x10,x11,0x2000000,-0x81,88,sh,0)
inst_40:
// rs2_val == -1431655766,
// opcode: sh; op1:x10; op2:x11; op2val:-0x55555556; immval:-0x556; align:0
TEST_STORE(x1,x3,0,x10,x11,-0x55555556,-0x556,92,sh,0)
inst_41:
// rs2_val == 1431655765,
// opcode: sh; op1:x10; op2:x11; op2val:0x55555555; immval:-0x9; align:0
TEST_STORE(x1,x3,0,x10,x11,0x55555555,-0x9,96,sh,0)
inst_42:
// ea_align == 2 and (imm_val % 4) == 0,
// opcode: sh; op1:x10; op2:x11; op2val:-0x1000001; immval:-0x400; align:2
TEST_STORE(x1,x3,0,x10,x11,-0x1000001,-0x400,100,sh,2)
inst_43:
// ea_align == 2 and (imm_val % 4) == 1, rs2_val == 2048
// opcode: sh; op1:x10; op2:x11; op2val:0x800; immval:-0x7; align:2
TEST_STORE(x1,x3,0,x10,x11,0x800,-0x7,104,sh,2)
inst_44:
// ea_align == 2 and (imm_val % 4) == 2,
// opcode: sh; op1:x10; op2:x11; op2val:0x3; immval:-0x556; align:2
TEST_STORE(x1,x3,0,x10,x11,0x3,-0x556,108,sh,2)
inst_45:
// ea_align == 2 and (imm_val % 4) == 3,
// opcode: sh; op1:x10; op2:x11; op2val:-0x6; immval:-0x1; align:2
TEST_STORE(x1,x3,0,x10,x11,-0x6,-0x1,112,sh,2)
inst_46:
// rs2_val == 0,
// opcode: sh; op1:x10; op2:x11; op2val:0x0; immval:-0x81; align:0
TEST_STORE(x1,x3,0,x10,x11,0x0,-0x81,116,sh,0)
inst_47:
// rs2_val == 16777216,
// opcode: sh; op1:x10; op2:x11; op2val:0x1000000; immval:-0x9; align:0
TEST_STORE(x1,x3,0,x10,x11,0x1000000,-0x9,120,sh,0)
inst_48:
// rs2_val == 8388608,
// opcode: sh; op1:x10; op2:x11; op2val:0x800000; immval:-0x2; align:0
TEST_STORE(x1,x3,0,x10,x11,0x800000,-0x2,124,sh,0)
inst_49:
// rs2_val == 4194304,
// opcode: sh; op1:x10; op2:x11; op2val:0x400000; immval:-0x11; align:0
TEST_STORE(x1,x3,0,x10,x11,0x400000,-0x11,128,sh,0)
inst_50:
// rs2_val == 2097152,
// opcode: sh; op1:x10; op2:x11; op2val:0x200000; immval:0x9; align:0
TEST_STORE(x1,x3,0,x10,x11,0x200000,0x9,132,sh,0)
inst_51:
// rs2_val == 1048576,
// opcode: sh; op1:x10; op2:x11; op2val:0x100000; immval:0x4; align:0
TEST_STORE(x1,x3,0,x10,x11,0x100000,0x4,136,sh,0)
inst_52:
// rs2_val == 524288,
// opcode: sh; op1:x10; op2:x11; op2val:0x80000; immval:-0x3; align:0
TEST_STORE(x1,x3,0,x10,x11,0x80000,-0x3,140,sh,0)
inst_53:
// rs2_val == 262144,
// opcode: sh; op1:x10; op2:x11; op2val:0x40000; immval:0x100; align:0
TEST_STORE(x1,x3,0,x10,x11,0x40000,0x100,144,sh,0)
inst_54:
// rs2_val == 131072,
// opcode: sh; op1:x10; op2:x11; op2val:0x20000; immval:-0x201; align:0
TEST_STORE(x1,x3,0,x10,x11,0x20000,-0x201,148,sh,0)
inst_55:
// rs2_val == 65536,
// opcode: sh; op1:x10; op2:x11; op2val:0x10000; immval:-0x6; align:0
TEST_STORE(x1,x3,0,x10,x11,0x10000,-0x6,152,sh,0)
inst_56:
// rs2_val == 32768,
// opcode: sh; op1:x10; op2:x11; op2val:0x8000; immval:0x100; align:0
TEST_STORE(x1,x3,0,x10,x11,0x8000,0x100,156,sh,0)
inst_57:
// rs2_val == 16384,
// opcode: sh; op1:x10; op2:x11; op2val:0x4000; immval:-0x400; align:0
TEST_STORE(x1,x3,0,x10,x11,0x4000,-0x400,160,sh,0)
inst_58:
// rs2_val == 8192,
// opcode: sh; op1:x10; op2:x11; op2val:0x2000; immval:-0x201; align:0
TEST_STORE(x1,x3,0,x10,x11,0x2000,-0x201,164,sh,0)
inst_59:
// rs2_val == 4096,
// opcode: sh; op1:x10; op2:x11; op2val:0x1000; immval:-0x3; align:0
TEST_STORE(x1,x3,0,x10,x11,0x1000,-0x3,168,sh,0)
inst_60:
// rs2_val == 1024,
// opcode: sh; op1:x10; op2:x11; op2val:0x400; immval:-0x81; align:0
TEST_STORE(x1,x3,0,x10,x11,0x400,-0x81,172,sh,0)
inst_61:
// rs2_val == 512,
// opcode: sh; op1:x10; op2:x11; op2val:0x200; immval:0x40; align:0
TEST_STORE(x1,x3,0,x10,x11,0x200,0x40,176,sh,0)
inst_62:
// rs2_val == 256,
// opcode: sh; op1:x10; op2:x11; op2val:0x100; immval:-0x800; align:0
TEST_STORE(x1,x3,0,x10,x11,0x100,-0x800,180,sh,0)
inst_63:
// rs2_val == 128,
// opcode: sh; op1:x10; op2:x11; op2val:0x80; immval:-0x6; align:0
TEST_STORE(x1,x3,0,x10,x11,0x80,-0x6,184,sh,0)
inst_64:
// rs2_val == 64,
// opcode: sh; op1:x10; op2:x11; op2val:0x40; immval:-0x11; align:0
TEST_STORE(x1,x3,0,x10,x11,0x40,-0x11,188,sh,0)
inst_65:
// rs2_val == 32,
// opcode: sh; op1:x10; op2:x11; op2val:0x20; immval:0x9; align:0
TEST_STORE(x1,x3,0,x10,x11,0x20,0x9,192,sh,0)
inst_66:
// rs2_val == 16,
// opcode: sh; op1:x10; op2:x11; op2val:0x10; immval:-0x7; align:0
TEST_STORE(x1,x3,0,x10,x11,0x10,-0x7,196,sh,0)
inst_67:
// rs2_val == 8,
// opcode: sh; op1:x10; op2:x11; op2val:0x8; immval:-0x3; align:0
TEST_STORE(x1,x3,0,x10,x11,0x8,-0x3,200,sh,0)
inst_68:
// rs2_val == 4,
// opcode: sh; op1:x10; op2:x11; op2val:0x4; immval:-0x4; align:0
TEST_STORE(x1,x3,0,x10,x11,0x4,-0x4,204,sh,0)
inst_69:
// rs2_val == 2,
// opcode: sh; op1:x10; op2:x11; op2val:0x2; immval:0x400; align:0
TEST_STORE(x1,x3,0,x10,x11,0x2,0x400,208,sh,0)
inst_70:
// rs2_val == -524289,
// opcode: sh; op1:x10; op2:x11; op2val:-0x80001; immval:-0x5; align:0
TEST_STORE(x1,x3,0,x10,x11,-0x80001,-0x5,212,sh,0)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
signature_x8_0:
.fill 0*(XLEN/32),4,0xdeadbeef
signature_x8_1:
.fill 8*(XLEN/32),4,0xdeadbeef
signature_x2_0:
.fill 9*(XLEN/32),4,0xdeadbeef
signature_x1_0:
.fill 54*(XLEN/32),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

524
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sll-01.S
View File

@ -1,524 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version : 0.5.1
// timestamp : Mon Aug 2 08:58:53 2021 GMT
// usage : riscv_ctg \
// --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/rv32e.cgf \
// --base-isa rv32e \
// --randomize
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the sll instruction of the RISC-V E extension for the sll covergroup.
//
#define RVTEST_E
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32E")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",sll)
RVTEST_SIGBASE( x2,signature_x2_1)
inst_0:
// rs1 != rs2 and rs1 != rd and rs2 != rd, rs1==x6, rs2==x13, rd==x1, rs1_val < 0 and rs2_val == 0,
// opcode: sll ; op1:x6; op2:x13; dest:x1; op1val:-0x40000000; op2val:0x0
TEST_RR_OP(sll, x1, x6, x13, 0xc0000000, -0x40000000, 0x0, x2, 0, x7)
inst_1:
// rs1 == rd != rs2, rs1==x4, rs2==x1, rd==x4, rs2_val == 15, rs1_val == -17, rs1_val < 0 and rs2_val > 0 and rs2_val < xlen
// opcode: sll ; op1:x4; op2:x1; dest:x4; op1val:-0x11; op2val:0xf
TEST_RR_OP(sll, x4, x4, x1, 0xfff78000, -0x11, 0xf, x2, 4, x7)
inst_2:
// rs2 == rd != rs1, rs1==x9, rs2==x11, rd==x11, rs2_val == 23, rs1_val == -257
// opcode: sll ; op1:x9; op2:x11; dest:x11; op1val:-0x101; op2val:0x17
TEST_RR_OP(sll, x11, x9, x11, 0x7f800000, -0x101, 0x17, x2, 8, x7)
inst_3:
// rs1 == rs2 != rd, rs1==x12, rs2==x12, rd==x9, rs2_val == 27, rs1_val==-46340
// opcode: sll ; op1:x12; op2:x12; dest:x9; op1val:-0xb504; op2val:-0xb504
TEST_RR_OP(sll, x9, x12, x12, 0xc0000000, -0xb504, -0xb504, x2, 12, x7)
inst_4:
// rs1 == rs2 == rd, rs1==x0, rs2==x0, rd==x0, rs2_val == 29, rs1_val == 4, rs1_val==4, rs1_val > 0 and rs2_val > 0 and rs2_val < xlen
// opcode: sll ; op1:x0; op2:x0; dest:x0; op1val:0x0; op2val:0x0
TEST_RR_OP(sll, x0, x0, x0, 0, 0x0, 0x0, x2, 16, x7)
inst_5:
// rs1==x5, rs2==x4, rd==x15, rs2_val == 30, rs1_val == -65
// opcode: sll ; op1:x5; op2:x4; dest:x15; op1val:-0x41; op2val:0x1e
TEST_RR_OP(sll, x15, x5, x4, 0xc0000000, -0x41, 0x1e, x2, 20, x7)
inst_6:
// rs1==x1, rs2==x10, rd==x3, rs1_val == 2147483647, rs1_val == (2**(xlen-1)-1) and rs2_val >= 0 and rs2_val < xlen
// opcode: sll ; op1:x1; op2:x10; dest:x3; op1val:0x7fffffff; op2val:0x9
TEST_RR_OP(sll, x3, x1, x10, 0xfffffe00, 0x7fffffff, 0x9, x2, 24, x7)
inst_7:
// rs1==x8, rs2==x15, rd==x10, rs1_val == -1073741825,
// opcode: sll ; op1:x8; op2:x15; dest:x10; op1val:-0x40000001; op2val:0x11
TEST_RR_OP(sll, x10, x8, x15, 0xfffe0000, -0x40000001, 0x11, x2, 28, x4)
RVTEST_SIGBASE( x1,signature_x1_0)
inst_8:
// rs1==x13, rs2==x6, rd==x12, rs1_val == -536870913, rs2_val == 1
// opcode: sll ; op1:x13; op2:x6; dest:x12; op1val:-0x20000001; op2val:0x1
TEST_RR_OP(sll, x12, x13, x6, 0xbffffffe, -0x20000001, 0x1, x1, 0, x4)
inst_9:
// rs1==x3, rs2==x9, rd==x5, rs1_val == -268435457,
// opcode: sll ; op1:x3; op2:x9; dest:x5; op1val:-0x10000001; op2val:0xe
TEST_RR_OP(sll, x5, x3, x9, 0xffffc000, -0x10000001, 0xe, x1, 4, x4)
inst_10:
// rs1==x7, rs2==x2, rd==x13, rs1_val == -134217729,
// opcode: sll ; op1:x7; op2:x2; dest:x13; op1val:-0x8000001; op2val:0x1e
TEST_RR_OP(sll, x13, x7, x2, 0xc0000000, -0x8000001, 0x1e, x1, 8, x4)
inst_11:
// rs1==x11, rs2==x7, rd==x8, rs1_val == -67108865,
// opcode: sll ; op1:x11; op2:x7; dest:x8; op1val:-0x4000001; op2val:0x17
TEST_RR_OP(sll, x8, x11, x7, 0xff800000, -0x4000001, 0x17, x1, 12, x4)
inst_12:
// rs1==x10, rs2==x14, rd==x7, rs1_val == -33554433, rs2_val == 8
// opcode: sll ; op1:x10; op2:x14; dest:x7; op1val:-0x2000001; op2val:0x8
TEST_RR_OP(sll, x7, x10, x14, 0xffffff00, -0x2000001, 0x8, x1, 16, x4)
RVTEST_SIGBASE( x1,signature_x1_1)
inst_13:
// rs1==x14, rs2==x8, rd==x6, rs1_val == -16777217,
// opcode: sll ; op1:x14; op2:x8; dest:x6; op1val:-0x1000001; op2val:0xd
TEST_RR_OP(sll, x6, x14, x8, 0xffffe000, -0x1000001, 0xd, x1, 0, x4)
inst_14:
// rs1==x15, rs2==x3, rd==x2, rs1_val == -8388609, rs2_val == 21
// opcode: sll ; op1:x15; op2:x3; dest:x2; op1val:-0x800001; op2val:0x15
TEST_RR_OP(sll, x2, x15, x3, 0xffe00000, -0x800001, 0x15, x1, 4, x4)
inst_15:
// rs1==x2, rs2==x5, rd==x14, rs1_val == -4194305,
// opcode: sll ; op1:x2; op2:x5; dest:x14; op1val:-0x400001; op2val:0xb
TEST_RR_OP(sll, x14, x2, x5, 0xfffff800, -0x400001, 0xb, x1, 8, x4)
inst_16:
// rs1_val == -2097153,
// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:-0x200001; op2val:0xb
TEST_RR_OP(sll, x12, x10, x11, 0xfffff800, -0x200001, 0xb, x1, 12, x4)
inst_17:
// rs1_val == -1048577, rs2_val == 2
// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:-0x100001; op2val:0x2
TEST_RR_OP(sll, x12, x10, x11, 0xffbffffc, -0x100001, 0x2, x1, 16, x2)
inst_18:
// rs1_val == -524289,
// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:-0x80001; op2val:0x9
TEST_RR_OP(sll, x12, x10, x11, 0xeffffe00, -0x80001, 0x9, x1, 20, x2)
inst_19:
// rs1_val == -262145,
// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:-0x40001; op2val:0xf
TEST_RR_OP(sll, x12, x10, x11, 0xffff8000, -0x40001, 0xf, x1, 24, x2)
inst_20:
// rs1_val == -131073, rs2_val == 10
// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:-0x20001; op2val:0xa
TEST_RR_OP(sll, x12, x10, x11, 0xf7fffc00, -0x20001, 0xa, x1, 28, x2)
inst_21:
// rs1_val == -65537,
// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:-0x10001; op2val:0x2
TEST_RR_OP(sll, x12, x10, x11, 0xfffbfffc, -0x10001, 0x2, x1, 32, x2)
inst_22:
// rs1_val == -32769, rs2_val == 4
// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:-0x8001; op2val:0x4
TEST_RR_OP(sll, x12, x10, x11, 0xfff7fff0, -0x8001, 0x4, x1, 36, x2)
inst_23:
// rs1_val == -16385,
// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:-0x4001; op2val:0x0
TEST_RR_OP(sll, x12, x10, x11, 0xffffbfff, -0x4001, 0x0, x1, 40, x2)
inst_24:
// rs1_val == -8193,
// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:-0x2001; op2val:0xd
TEST_RR_OP(sll, x12, x10, x11, 0xfbffe000, -0x2001, 0xd, x1, 44, x2)
inst_25:
// rs1_val == -4097,
// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:-0x1001; op2val:0x1e
TEST_RR_OP(sll, x12, x10, x11, 0xc0000000, -0x1001, 0x1e, x1, 48, x2)
inst_26:
// rs1_val == -2049, rs2_val == 16
// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:-0x801; op2val:0x10
TEST_RR_OP(sll, x12, x10, x11, 0xf7ff0000, -0x801, 0x10, x1, 52, x2)
inst_27:
// rs1_val == -1025,
// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:-0x401; op2val:0x5
TEST_RR_OP(sll, x12, x10, x11, 0xffff7fe0, -0x401, 0x5, x1, 56, x2)
inst_28:
// rs1_val == -513,
// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:-0x201; op2val:0x5
TEST_RR_OP(sll, x12, x10, x11, 0xffffbfe0, -0x201, 0x5, x1, 60, x2)
inst_29:
// rs1_val == -129,
// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:-0x81; op2val:0x10
TEST_RR_OP(sll, x12, x10, x11, 0xff7f0000, -0x81, 0x10, x1, 64, x2)
inst_30:
// rs1_val == -33,
// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:-0x21; op2val:0x10
TEST_RR_OP(sll, x12, x10, x11, 0xffdf0000, -0x21, 0x10, x1, 68, x2)
inst_31:
// rs1_val == -9,
// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:-0x9; op2val:0x10
TEST_RR_OP(sll, x12, x10, x11, 0xfff70000, -0x9, 0x10, x1, 72, x2)
inst_32:
// rs1_val == -5,
// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:-0x5; op2val:0xf
TEST_RR_OP(sll, x12, x10, x11, 0xfffd8000, -0x5, 0xf, x1, 76, x2)
inst_33:
// rs1_val == -3,
// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:-0x3; op2val:0x4
TEST_RR_OP(sll, x12, x10, x11, 0xffffffd0, -0x3, 0x4, x1, 80, x2)
inst_34:
// rs1_val == -2,
// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:-0x2; op2val:0x2
TEST_RR_OP(sll, x12, x10, x11, 0xfffffff8, -0x2, 0x2, x1, 84, x2)
inst_35:
// rs1_val == -2147483648, rs1_val == (-2**(xlen-1)) and rs2_val >= 0 and rs2_val < xlen
// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:-0x80000000; op2val:0x1f
TEST_RR_OP(sll, x12, x10, x11, 0x0, -0x80000000, 0x1f, x1, 88, x2)
inst_36:
// rs1_val == 1073741824,
// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0x40000000; op2val:0x17
TEST_RR_OP(sll, x12, x10, x11, 0x0, 0x40000000, 0x17, x1, 92, x2)
inst_37:
// rs1_val == 536870912,
// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0x20000000; op2val:0xb
TEST_RR_OP(sll, x12, x10, x11, 0x0, 0x20000000, 0xb, x1, 96, x2)
inst_38:
// rs1_val == 268435456,
// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0x10000000; op2val:0x1
TEST_RR_OP(sll, x12, x10, x11, 0x20000000, 0x10000000, 0x1, x1, 100, x2)
inst_39:
// rs1_val == 134217728,
// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0x8000000; op2val:0x13
TEST_RR_OP(sll, x12, x10, x11, 0x0, 0x8000000, 0x13, x1, 104, x2)
inst_40:
// rs1_val == 67108864,
// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0x4000000; op2val:0x5
TEST_RR_OP(sll, x12, x10, x11, 0x80000000, 0x4000000, 0x5, x1, 108, x2)
inst_41:
// rs1_val == 33554432,
// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0x2000000; op2val:0x3
TEST_RR_OP(sll, x12, x10, x11, 0x10000000, 0x2000000, 0x3, x1, 112, x2)
inst_42:
// rs1_val == 16777216,
// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0x1000000; op2val:0xa
TEST_RR_OP(sll, x12, x10, x11, 0x0, 0x1000000, 0xa, x1, 116, x2)
inst_43:
// rs1_val == 8388608,
// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0x800000; op2val:0x4
TEST_RR_OP(sll, x12, x10, x11, 0x8000000, 0x800000, 0x4, x1, 120, x2)
inst_44:
// rs1_val == 4194304, rs1_val > 0 and rs2_val == 0
// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0x400000; op2val:0x0
TEST_RR_OP(sll, x12, x10, x11, 0x400000, 0x400000, 0x0, x1, 124, x2)
inst_45:
// rs1_val == 2097152,
// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0x200000; op2val:0x12
TEST_RR_OP(sll, x12, x10, x11, 0x0, 0x200000, 0x12, x1, 128, x2)
inst_46:
// rs1_val == 1048576,
// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0x100000; op2val:0x1f
TEST_RR_OP(sll, x12, x10, x11, 0x0, 0x100000, 0x1f, x1, 132, x2)
inst_47:
// rs1_val == 524288,
// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0x80000; op2val:0x7
TEST_RR_OP(sll, x12, x10, x11, 0x4000000, 0x80000, 0x7, x1, 136, x2)
inst_48:
// rs1_val == 262144,
// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0x40000; op2val:0x1b
TEST_RR_OP(sll, x12, x10, x11, 0x0, 0x40000, 0x1b, x1, 140, x2)
inst_49:
// rs1_val == 131072,
// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0x20000; op2val:0x10
TEST_RR_OP(sll, x12, x10, x11, 0x0, 0x20000, 0x10, x1, 144, x2)
inst_50:
// rs1_val == 65536,
// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0x10000; op2val:0x11
TEST_RR_OP(sll, x12, x10, x11, 0x0, 0x10000, 0x11, x1, 148, x2)
inst_51:
// rs1_val == 32768,
// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0x8000; op2val:0xc
TEST_RR_OP(sll, x12, x10, x11, 0x8000000, 0x8000, 0xc, x1, 152, x2)
inst_52:
// rs1_val == 16384,
// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0x4000; op2val:0x12
TEST_RR_OP(sll, x12, x10, x11, 0x0, 0x4000, 0x12, x1, 156, x2)
inst_53:
// rs1_val == 8192,
// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0x2000; op2val:0x8
TEST_RR_OP(sll, x12, x10, x11, 0x200000, 0x2000, 0x8, x1, 160, x2)
inst_54:
// rs1_val == 4096,
// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0x1000; op2val:0xa
TEST_RR_OP(sll, x12, x10, x11, 0x400000, 0x1000, 0xa, x1, 164, x2)
inst_55:
// rs1_val == 2048,
// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0x800; op2val:0xa
TEST_RR_OP(sll, x12, x10, x11, 0x200000, 0x800, 0xa, x1, 168, x2)
inst_56:
// rs1_val == 1024,
// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0x400; op2val:0x11
TEST_RR_OP(sll, x12, x10, x11, 0x8000000, 0x400, 0x11, x1, 172, x2)
inst_57:
// rs1_val == 512,
// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0x200; op2val:0x17
TEST_RR_OP(sll, x12, x10, x11, 0x0, 0x200, 0x17, x1, 176, x2)
inst_58:
// rs1_val == 256,
// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0x100; op2val:0x7
TEST_RR_OP(sll, x12, x10, x11, 0x8000, 0x100, 0x7, x1, 180, x2)
inst_59:
// rs1_val == 128,
// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0x80; op2val:0x1f
TEST_RR_OP(sll, x12, x10, x11, 0x0, 0x80, 0x1f, x1, 184, x2)
inst_60:
// rs1_val == 64,
// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0x40; op2val:0xa
TEST_RR_OP(sll, x12, x10, x11, 0x10000, 0x40, 0xa, x1, 188, x2)
inst_61:
// rs1_val == 32,
// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0x20; op2val:0xa
TEST_RR_OP(sll, x12, x10, x11, 0x8000, 0x20, 0xa, x1, 192, x2)
inst_62:
// rs1_val == 16,
// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0x10; op2val:0x17
TEST_RR_OP(sll, x12, x10, x11, 0x8000000, 0x10, 0x17, x1, 196, x2)
inst_63:
// rs1_val == 8,
// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0x8; op2val:0x1d
TEST_RR_OP(sll, x12, x10, x11, 0x0, 0x8, 0x1d, x1, 200, x2)
inst_64:
// rs1_val == 2, rs1_val==2
// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0x2; op2val:0x1b
TEST_RR_OP(sll, x12, x10, x11, 0x10000000, 0x2, 0x1b, x1, 204, x2)
inst_65:
// rs1_val == 1, rs1_val == 1 and rs2_val >= 0 and rs2_val < xlen
// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0x1; op2val:0x1f
TEST_RR_OP(sll, x12, x10, x11, 0x80000000, 0x1, 0x1f, x1, 208, x2)
inst_66:
// rs1_val==46341,
// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0xb505; op2val:0x13
TEST_RR_OP(sll, x12, x10, x11, 0xa8280000, 0xb505, 0x13, x1, 212, x2)
inst_67:
// rs1_val==-46339,
// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:-0xb503; op2val:0x8
TEST_RR_OP(sll, x12, x10, x11, 0xff4afd00, -0xb503, 0x8, x1, 216, x2)
inst_68:
// rs1_val==1717986919,
// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0x66666667; op2val:0x2
TEST_RR_OP(sll, x12, x10, x11, 0x9999999c, 0x66666667, 0x2, x1, 220, x2)
inst_69:
// rs1_val==858993460,
// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0x33333334; op2val:0x5
TEST_RR_OP(sll, x12, x10, x11, 0x66666680, 0x33333334, 0x5, x1, 224, x2)
inst_70:
// rs1_val==6,
// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0x6; op2val:0x11
TEST_RR_OP(sll, x12, x10, x11, 0xc0000, 0x6, 0x11, x1, 228, x2)
inst_71:
// rs1_val==-1431655765,
// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555; op2val:0x11
TEST_RR_OP(sll, x12, x10, x11, 0x55560000, -0x55555555, 0x11, x1, 232, x2)
inst_72:
// rs1_val==1431655766,
// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0x55555556; op2val:0x13
TEST_RR_OP(sll, x12, x10, x11, 0xaab00000, 0x55555556, 0x13, x1, 236, x2)
inst_73:
// rs1_val==46339,
// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0xb503; op2val:0x0
TEST_RR_OP(sll, x12, x10, x11, 0xb503, 0xb503, 0x0, x1, 240, x2)
inst_74:
// rs1_val==3,
// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0x3; op2val:0x11
TEST_RR_OP(sll, x12, x10, x11, 0x60000, 0x3, 0x11, x1, 244, x2)
inst_75:
// rs1_val == -1431655766, rs1_val==-1431655766
// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556; op2val:0x10
TEST_RR_OP(sll, x12, x10, x11, 0xaaaa0000, -0x55555556, 0x10, x1, 248, x2)
inst_76:
// rs1_val == 1431655765, rs1_val==1431655765
// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0x55555555; op2val:0x12
TEST_RR_OP(sll, x12, x10, x11, 0x55540000, 0x55555555, 0x12, x1, 252, x2)
inst_77:
// rs1_val == 0 and rs2_val >= 0 and rs2_val < xlen, rs1_val==0
// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0x0; op2val:0xc
TEST_RR_OP(sll, x12, x10, x11, 0x0, 0x0, 0xc, x1, 256, x2)
inst_78:
// rs1_val == rs2_val and rs2_val > 0 and rs2_val < xlen,
// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0x2; op2val:0x2
TEST_RR_OP(sll, x12, x10, x11, 0x8, 0x2, 0x2, x1, 260, x2)
inst_79:
// rs1_val==1717986917,
// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0x66666665; op2val:0x8
TEST_RR_OP(sll, x12, x10, x11, 0x66666500, 0x66666665, 0x8, x1, 264, x2)
inst_80:
// rs1_val==858993458,
// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0x33333332; op2val:0xe
TEST_RR_OP(sll, x12, x10, x11, 0xcccc8000, 0x33333332, 0xe, x1, 268, x2)
inst_81:
// rs1_val==1431655764,
// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0x55555554; op2val:0x0
TEST_RR_OP(sll, x12, x10, x11, 0x55555554, 0x55555554, 0x0, x1, 272, x2)
inst_82:
// rs1_val==46340,
// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0xb504; op2val:0x12
TEST_RR_OP(sll, x12, x10, x11, 0xd4100000, 0xb504, 0x12, x1, 276, x2)
inst_83:
// rs1_val==1717986918,
// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0x66666666; op2val:0x15
TEST_RR_OP(sll, x12, x10, x11, 0xccc00000, 0x66666666, 0x15, x1, 280, x2)
inst_84:
// rs1_val==858993459,
// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0x33333333; op2val:0x6
TEST_RR_OP(sll, x12, x10, x11, 0xccccccc0, 0x33333333, 0x6, x1, 284, x2)
inst_85:
// rs1_val==5,
// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0x5; op2val:0xa
TEST_RR_OP(sll, x12, x10, x11, 0x1400, 0x5, 0xa, x1, 288, x2)
inst_86:
// rs2_val == 27, rs1_val==-46340
// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:-0xb504; op2val:0x1b
TEST_RR_OP(sll, x12, x10, x11, 0xe0000000, -0xb504, 0x1b, x1, 292, x2)
inst_87:
// rs2_val == 29, rs1_val == 4, rs1_val==4, rs1_val > 0 and rs2_val > 0 and rs2_val < xlen
// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0x4; op2val:0x1d
TEST_RR_OP(sll, x12, x10, x11, 0x80000000, 0x4, 0x1d, x1, 296, x2)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
signature_x2_0:
.fill 0*(XLEN/32),4,0xdeadbeef
signature_x2_1:
.fill 8*(XLEN/32),4,0xdeadbeef
signature_x1_0:
.fill 5*(XLEN/32),4,0xdeadbeef
signature_x1_1:
.fill 75*(XLEN/32),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

529
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-slli-01.S
View File

@ -1,529 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version : 0.5.1
// timestamp : Mon Aug 2 08:58:53 2021 GMT
// usage : riscv_ctg \
// --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/rv32e.cgf \
// --base-isa rv32e \
// --randomize
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the slli instruction of the RISC-V E extension for the slli covergroup.
//
#define RVTEST_E
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32E")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",slli)
RVTEST_SIGBASE( x5,signature_x5_1)
inst_0:
// rs1 != rd, rs1==x2, rd==x10, rs1_val < 0 and imm_val == (xlen-1), rs1_val < 0 and imm_val > 0 and imm_val < xlen
// opcode: slli ; op1:x2; dest:x10; op1val:-0x1; immval:0x1f
TEST_IMM_OP( slli, x10, x2, 0x80000000, -0x1, 0x1f, x5, 0, x12)
inst_1:
// rs1 == rd, rs1==x3, rd==x3, rs1_val == 2147483647, rs1_val == (2**(xlen-1)-1) and imm_val >= 0 and imm_val < xlen, imm_val == 27, rs1_val > 0 and imm_val > 0 and imm_val < xlen
// opcode: slli ; op1:x3; dest:x3; op1val:0x7fffffff; immval:0x1b
TEST_IMM_OP( slli, x3, x3, 0xf8000000, 0x7fffffff, 0x1b, x5, 4, x12)
inst_2:
// rs1==x9, rd==x14, rs1_val == -1073741825,
// opcode: slli ; op1:x9; dest:x14; op1val:-0x40000001; immval:0x7
TEST_IMM_OP( slli, x14, x9, 0xffffff80, -0x40000001, 0x7, x5, 8, x12)
inst_3:
// rs1==x7, rd==x8, rs1_val == -536870913, imm_val == 1
// opcode: slli ; op1:x7; dest:x8; op1val:-0x20000001; immval:0x1
TEST_IMM_OP( slli, x8, x7, 0xbffffffe, -0x20000001, 0x1, x5, 12, x12)
inst_4:
// rs1==x4, rd==x6, rs1_val == -268435457,
// opcode: slli ; op1:x4; dest:x6; op1val:-0x10000001; immval:0x12
TEST_IMM_OP( slli, x6, x4, 0xfffc0000, -0x10000001, 0x12, x5, 16, x12)
inst_5:
// rs1==x11, rd==x7, rs1_val == -134217729, rs1_val < 0 and imm_val == 0
// opcode: slli ; op1:x11; dest:x7; op1val:-0x8000001; immval:0x0
TEST_IMM_OP( slli, x7, x11, 0xf7ffffff, -0x8000001, 0x0, x5, 20, x12)
inst_6:
// rs1==x0, rd==x1, rs1_val == -67108865,
// opcode: slli ; op1:x0; dest:x1; op1val:0x0; immval:0x7
TEST_IMM_OP( slli, x1, x0, 0x0, 0x0, 0x7, x5, 24, x12)
inst_7:
// rs1==x1, rd==x11, rs1_val == -33554433, imm_val == 15
// opcode: slli ; op1:x1; dest:x11; op1val:-0x2000001; immval:0xf
TEST_IMM_OP( slli, x11, x1, 0xffff8000, -0x2000001, 0xf, x5, 28, x3)
inst_8:
// rs1==x10, rd==x12, rs1_val == -16777217,
// opcode: slli ; op1:x10; dest:x12; op1val:-0x1000001; immval:0x13
TEST_IMM_OP( slli, x12, x10, 0xfff80000, -0x1000001, 0x13, x5, 32, x3)
RVTEST_SIGBASE( x1,signature_x1_0)
inst_9:
// rs1==x13, rd==x9, rs1_val == -8388609, imm_val == 16
// opcode: slli ; op1:x13; dest:x9; op1val:-0x800001; immval:0x10
TEST_IMM_OP( slli, x9, x13, 0xffff0000, -0x800001, 0x10, x1, 0, x3)
inst_10:
// rs1==x5, rd==x13, rs1_val == -4194305,
// opcode: slli ; op1:x5; dest:x13; op1val:-0x400001; immval:0x1f
TEST_IMM_OP( slli, x13, x5, 0x80000000, -0x400001, 0x1f, x1, 4, x3)
inst_11:
// rs1==x8, rd==x15, rs1_val == -2097153,
// opcode: slli ; op1:x8; dest:x15; op1val:-0x200001; immval:0x1b
TEST_IMM_OP( slli, x15, x8, 0xf8000000, -0x200001, 0x1b, x1, 8, x3)
inst_12:
// rs1==x15, rd==x4, rs1_val == -1048577,
// opcode: slli ; op1:x15; dest:x4; op1val:-0x100001; immval:0xc
TEST_IMM_OP( slli, x4, x15, 0xfffff000, -0x100001, 0xc, x1, 12, x3)
inst_13:
// rs1==x14, rd==x5, rs1_val == -524289,
// opcode: slli ; op1:x14; dest:x5; op1val:-0x80001; immval:0x9
TEST_IMM_OP( slli, x5, x14, 0xeffffe00, -0x80001, 0x9, x1, 16, x3)
inst_14:
// rs1==x6, rd==x2, rs1_val == -262145,
// opcode: slli ; op1:x6; dest:x2; op1val:-0x40001; immval:0x0
TEST_IMM_OP( slli, x2, x6, 0xfffbffff, -0x40001, 0x0, x1, 20, x3)
inst_15:
// rs1==x12, rd==x0, rs1_val == -131073,
// opcode: slli ; op1:x12; dest:x0; op1val:-0x20001; immval:0x10
TEST_IMM_OP( slli, x0, x12, 0, -0x20001, 0x10, x1, 24, x2)
inst_16:
// rs1_val == -65537,
// opcode: slli ; op1:x10; dest:x11; op1val:-0x10001; immval:0xb
TEST_IMM_OP( slli, x11, x10, 0xf7fff800, -0x10001, 0xb, x1, 28, x2)
RVTEST_SIGBASE( x1,signature_x1_1)
inst_17:
// rs1_val == -32769,
// opcode: slli ; op1:x10; dest:x11; op1val:-0x8001; immval:0x11
TEST_IMM_OP( slli, x11, x10, 0xfffe0000, -0x8001, 0x11, x1, 0, x2)
inst_18:
// rs1_val == -16385,
// opcode: slli ; op1:x10; dest:x11; op1val:-0x4001; immval:0x1b
TEST_IMM_OP( slli, x11, x10, 0xf8000000, -0x4001, 0x1b, x1, 4, x2)
inst_19:
// rs1_val == -8193,
// opcode: slli ; op1:x10; dest:x11; op1val:-0x2001; immval:0x11
TEST_IMM_OP( slli, x11, x10, 0xbffe0000, -0x2001, 0x11, x1, 8, x2)
inst_20:
// rs1_val == -4097, imm_val == 29
// opcode: slli ; op1:x10; dest:x11; op1val:-0x1001; immval:0x1d
TEST_IMM_OP( slli, x11, x10, 0xe0000000, -0x1001, 0x1d, x1, 12, x2)
inst_21:
// rs1_val == -2049,
// opcode: slli ; op1:x10; dest:x11; op1val:-0x801; immval:0xe
TEST_IMM_OP( slli, x11, x10, 0xfdffc000, -0x801, 0xe, x1, 16, x2)
inst_22:
// rs1_val == -1025, imm_val == 23
// opcode: slli ; op1:x10; dest:x11; op1val:-0x401; immval:0x17
TEST_IMM_OP( slli, x11, x10, 0xff800000, -0x401, 0x17, x1, 20, x2)
inst_23:
// rs1_val == -513,
// opcode: slli ; op1:x10; dest:x11; op1val:-0x201; immval:0xe
TEST_IMM_OP( slli, x11, x10, 0xff7fc000, -0x201, 0xe, x1, 24, x2)
inst_24:
// rs1_val == -257,
// opcode: slli ; op1:x10; dest:x11; op1val:-0x101; immval:0x11
TEST_IMM_OP( slli, x11, x10, 0xfdfe0000, -0x101, 0x11, x1, 28, x2)
inst_25:
// rs1_val == -129,
// opcode: slli ; op1:x10; dest:x11; op1val:-0x81; immval:0xe
TEST_IMM_OP( slli, x11, x10, 0xffdfc000, -0x81, 0xe, x1, 32, x2)
inst_26:
// rs1_val == -65,
// opcode: slli ; op1:x10; dest:x11; op1val:-0x41; immval:0xe
TEST_IMM_OP( slli, x11, x10, 0xffefc000, -0x41, 0xe, x1, 36, x2)
inst_27:
// rs1_val == -33, imm_val == 8
// opcode: slli ; op1:x10; dest:x11; op1val:-0x21; immval:0x8
TEST_IMM_OP( slli, x11, x10, 0xffffdf00, -0x21, 0x8, x1, 40, x2)
inst_28:
// rs1_val == -17,
// opcode: slli ; op1:x10; dest:x11; op1val:-0x11; immval:0x6
TEST_IMM_OP( slli, x11, x10, 0xfffffbc0, -0x11, 0x6, x1, 44, x2)
inst_29:
// rs1_val == -9, imm_val == 4
// opcode: slli ; op1:x10; dest:x11; op1val:-0x9; immval:0x4
TEST_IMM_OP( slli, x11, x10, 0xffffff70, -0x9, 0x4, x1, 48, x2)
inst_30:
// rs1_val == -5,
// opcode: slli ; op1:x10; dest:x11; op1val:-0x5; immval:0x10
TEST_IMM_OP( slli, x11, x10, 0xfffb0000, -0x5, 0x10, x1, 52, x2)
inst_31:
// rs1_val == -3,
// opcode: slli ; op1:x10; dest:x11; op1val:-0x3; immval:0x9
TEST_IMM_OP( slli, x11, x10, 0xfffffa00, -0x3, 0x9, x1, 56, x2)
inst_32:
// rs1_val == -2,
// opcode: slli ; op1:x10; dest:x11; op1val:-0x2; immval:0x7
TEST_IMM_OP( slli, x11, x10, 0xffffff00, -0x2, 0x7, x1, 60, x2)
inst_33:
// imm_val == 30, rs1_val == 0 and imm_val >= 0 and imm_val < xlen, rs1_val==0
// opcode: slli ; op1:x10; dest:x11; op1val:0x0; immval:0x1e
TEST_IMM_OP( slli, x11, x10, 0x0, 0x0, 0x1e, x1, 64, x2)
inst_34:
// rs1_val == -2147483648, rs1_val == (-2**(xlen-1)) and imm_val >= 0 and imm_val < xlen
// opcode: slli ; op1:x10; dest:x11; op1val:-0x80000000; immval:0x17
TEST_IMM_OP( slli, x11, x10, 0x0, -0x80000000, 0x17, x1, 68, x2)
inst_35:
// rs1_val == 1073741824, imm_val == 21
// opcode: slli ; op1:x10; dest:x11; op1val:0x40000000; immval:0x15
TEST_IMM_OP( slli, x11, x10, 0x0, 0x40000000, 0x15, x1, 72, x2)
inst_36:
// rs1_val == 536870912,
// opcode: slli ; op1:x10; dest:x11; op1val:0x20000000; immval:0x10
TEST_IMM_OP( slli, x11, x10, 0x0, 0x20000000, 0x10, x1, 76, x2)
inst_37:
// rs1_val == 268435456,
// opcode: slli ; op1:x10; dest:x11; op1val:0x10000000; immval:0x7
TEST_IMM_OP( slli, x11, x10, 0x0, 0x10000000, 0x7, x1, 80, x2)
inst_38:
// rs1_val == 134217728,
// opcode: slli ; op1:x10; dest:x11; op1val:0x8000000; immval:0x1e
TEST_IMM_OP( slli, x11, x10, 0x0, 0x8000000, 0x1e, x1, 84, x2)
inst_39:
// rs1_val == 67108864,
// opcode: slli ; op1:x10; dest:x11; op1val:0x4000000; immval:0xf
TEST_IMM_OP( slli, x11, x10, 0x0, 0x4000000, 0xf, x1, 88, x2)
inst_40:
// rs1_val == 33554432,
// opcode: slli ; op1:x10; dest:x11; op1val:0x2000000; immval:0x1e
TEST_IMM_OP( slli, x11, x10, 0x0, 0x2000000, 0x1e, x1, 92, x2)
inst_41:
// rs1_val == 16777216, rs1_val > 0 and imm_val == (xlen-1)
// opcode: slli ; op1:x10; dest:x11; op1val:0x1000000; immval:0x1f
TEST_IMM_OP( slli, x11, x10, 0x0, 0x1000000, 0x1f, x1, 96, x2)
inst_42:
// rs1_val == 8388608,
// opcode: slli ; op1:x10; dest:x11; op1val:0x800000; immval:0x15
TEST_IMM_OP( slli, x11, x10, 0x0, 0x800000, 0x15, x1, 100, x2)
inst_43:
// rs1_val == 4194304, rs1_val > 0 and imm_val == 0
// opcode: slli ; op1:x10; dest:x11; op1val:0x400000; immval:0x0
TEST_IMM_OP( slli, x11, x10, 0x400000, 0x400000, 0x0, x1, 104, x2)
inst_44:
// rs1_val == 2097152,
// opcode: slli ; op1:x10; dest:x11; op1val:0x200000; immval:0x6
TEST_IMM_OP( slli, x11, x10, 0x8000000, 0x200000, 0x6, x1, 108, x2)
inst_45:
// rs1_val == 1048576,
// opcode: slli ; op1:x10; dest:x11; op1val:0x100000; immval:0x11
TEST_IMM_OP( slli, x11, x10, 0x0, 0x100000, 0x11, x1, 112, x2)
inst_46:
// rs1_val == 524288,
// opcode: slli ; op1:x10; dest:x11; op1val:0x80000; immval:0x1e
TEST_IMM_OP( slli, x11, x10, 0x0, 0x80000, 0x1e, x1, 116, x2)
inst_47:
// rs1_val == 262144,
// opcode: slli ; op1:x10; dest:x11; op1val:0x40000; immval:0x13
TEST_IMM_OP( slli, x11, x10, 0x0, 0x40000, 0x13, x1, 120, x2)
inst_48:
// rs1_val == 131072,
// opcode: slli ; op1:x10; dest:x11; op1val:0x20000; immval:0xf
TEST_IMM_OP( slli, x11, x10, 0x0, 0x20000, 0xf, x1, 124, x2)
inst_49:
// rs1_val == 65536,
// opcode: slli ; op1:x10; dest:x11; op1val:0x10000; immval:0xe
TEST_IMM_OP( slli, x11, x10, 0x40000000, 0x10000, 0xe, x1, 128, x2)
inst_50:
// rs1_val == 32768,
// opcode: slli ; op1:x10; dest:x11; op1val:0x8000; immval:0xc
TEST_IMM_OP( slli, x11, x10, 0x8000000, 0x8000, 0xc, x1, 132, x2)
inst_51:
// rs1_val == 16384,
// opcode: slli ; op1:x10; dest:x11; op1val:0x4000; immval:0x0
TEST_IMM_OP( slli, x11, x10, 0x4000, 0x4000, 0x0, x1, 136, x2)
inst_52:
// rs1_val == 8192,
// opcode: slli ; op1:x10; dest:x11; op1val:0x2000; immval:0x0
TEST_IMM_OP( slli, x11, x10, 0x2000, 0x2000, 0x0, x1, 140, x2)
inst_53:
// rs1_val == 4096,
// opcode: slli ; op1:x10; dest:x11; op1val:0x1000; immval:0x1
TEST_IMM_OP( slli, x11, x10, 0x2000, 0x1000, 0x1, x1, 144, x2)
inst_54:
// rs1_val == 2048,
// opcode: slli ; op1:x10; dest:x11; op1val:0x800; immval:0x15
TEST_IMM_OP( slli, x11, x10, 0x0, 0x800, 0x15, x1, 148, x2)
inst_55:
// rs1_val == 1024,
// opcode: slli ; op1:x10; dest:x11; op1val:0x400; immval:0xc
TEST_IMM_OP( slli, x11, x10, 0x400000, 0x400, 0xc, x1, 152, x2)
inst_56:
// rs1_val == 512,
// opcode: slli ; op1:x10; dest:x11; op1val:0x200; immval:0x3
TEST_IMM_OP( slli, x11, x10, 0x1000, 0x200, 0x3, x1, 156, x2)
inst_57:
// rs1_val == 256,
// opcode: slli ; op1:x10; dest:x11; op1val:0x100; immval:0x15
TEST_IMM_OP( slli, x11, x10, 0x20000000, 0x100, 0x15, x1, 160, x2)
inst_58:
// rs1_val == 128,
// opcode: slli ; op1:x10; dest:x11; op1val:0x80; immval:0x1d
TEST_IMM_OP( slli, x11, x10, 0x0, 0x80, 0x1d, x1, 164, x2)
inst_59:
// rs1_val == 64,
// opcode: slli ; op1:x10; dest:x11; op1val:0x40; immval:0x6
TEST_IMM_OP( slli, x11, x10, 0x1000, 0x40, 0x6, x1, 168, x2)
inst_60:
// rs1_val == 32,
// opcode: slli ; op1:x10; dest:x11; op1val:0x20; immval:0xb
TEST_IMM_OP( slli, x11, x10, 0x10000, 0x20, 0xb, x1, 172, x2)
inst_61:
// rs1_val == 16,
// opcode: slli ; op1:x10; dest:x11; op1val:0x10; immval:0x0
TEST_IMM_OP( slli, x11, x10, 0x10, 0x10, 0x0, x1, 176, x2)
inst_62:
// rs1_val == 8,
// opcode: slli ; op1:x10; dest:x11; op1val:0x8; immval:0x13
TEST_IMM_OP( slli, x11, x10, 0x400000, 0x8, 0x13, x1, 180, x2)
inst_63:
// rs1_val == 4, rs1_val==4, rs1_val == imm_val and imm_val > 0 and imm_val < xlen
// opcode: slli ; op1:x10; dest:x11; op1val:0x4; immval:0x4
TEST_IMM_OP( slli, x11, x10, 0x40, 0x4, 0x4, x1, 184, x2)
inst_64:
// rs1_val == 2, rs1_val==2
// opcode: slli ; op1:x10; dest:x11; op1val:0x2; immval:0xb
TEST_IMM_OP( slli, x11, x10, 0x1000, 0x2, 0xb, x1, 188, x2)
inst_65:
// rs1_val == 1, rs1_val == 1 and imm_val >= 0 and imm_val < xlen
// opcode: slli ; op1:x10; dest:x11; op1val:0x1; immval:0xe
TEST_IMM_OP( slli, x11, x10, 0x4000, 0x1, 0xe, x1, 192, x2)
inst_66:
// imm_val == 2,
// opcode: slli ; op1:x10; dest:x11; op1val:-0x81; immval:0x2
TEST_IMM_OP( slli, x11, x10, 0xfffffdfc, -0x81, 0x2, x1, 196, x2)
inst_67:
// rs1_val==46341,
// opcode: slli ; op1:x10; dest:x11; op1val:0xb505; immval:0xf
TEST_IMM_OP( slli, x11, x10, 0x5a828000, 0xb505, 0xf, x1, 200, x2)
inst_68:
// rs1_val==-46339,
// opcode: slli ; op1:x10; dest:x11; op1val:-0xb503; immval:0x17
TEST_IMM_OP( slli, x11, x10, 0x7e800000, -0xb503, 0x17, x1, 204, x2)
inst_69:
// rs1_val==1717986919,
// opcode: slli ; op1:x10; dest:x11; op1val:0x66666667; immval:0x1b
TEST_IMM_OP( slli, x11, x10, 0x38000000, 0x66666667, 0x1b, x1, 208, x2)
inst_70:
// rs1_val==858993460,
// opcode: slli ; op1:x10; dest:x11; op1val:0x33333334; immval:0x13
TEST_IMM_OP( slli, x11, x10, 0x99a00000, 0x33333334, 0x13, x1, 212, x2)
inst_71:
// rs1_val==6,
// opcode: slli ; op1:x10; dest:x11; op1val:0x6; immval:0xb
TEST_IMM_OP( slli, x11, x10, 0x3000, 0x6, 0xb, x1, 216, x2)
inst_72:
// rs1_val==-1431655765,
// opcode: slli ; op1:x10; dest:x11; op1val:-0x55555555; immval:0x12
TEST_IMM_OP( slli, x11, x10, 0xaaac0000, -0x55555555, 0x12, x1, 220, x2)
inst_73:
// rs1_val==1431655766,
// opcode: slli ; op1:x10; dest:x11; op1val:0x55555556; immval:0x1e
TEST_IMM_OP( slli, x11, x10, 0x80000000, 0x55555556, 0x1e, x1, 224, x2)
inst_74:
// rs1_val==3,
// opcode: slli ; op1:x10; dest:x11; op1val:0x3; immval:0x12
TEST_IMM_OP( slli, x11, x10, 0xc0000, 0x3, 0x12, x1, 228, x2)
inst_75:
// rs1_val == -1431655766, rs1_val==-1431655766
// opcode: slli ; op1:x10; dest:x11; op1val:-0x55555556; immval:0x10
TEST_IMM_OP( slli, x11, x10, 0xaaaa0000, -0x55555556, 0x10, x1, 232, x2)
inst_76:
// rs1_val == 1431655765, rs1_val==1431655765
// opcode: slli ; op1:x10; dest:x11; op1val:0x55555555; immval:0x7
TEST_IMM_OP( slli, x11, x10, 0xaaaaaa80, 0x55555555, 0x7, x1, 236, x2)
inst_77:
// imm_val == 10,
// opcode: slli ; op1:x10; dest:x11; op1val:-0x1001; immval:0xa
TEST_IMM_OP( slli, x11, x10, 0xffbffc00, -0x1001, 0xa, x1, 240, x2)
inst_78:
// rs1_val==46339,
// opcode: slli ; op1:x10; dest:x11; op1val:0xb503; immval:0x6
TEST_IMM_OP( slli, x11, x10, 0x2d40c0, 0xb503, 0x6, x1, 244, x2)
inst_79:
// rs1_val==1717986917,
// opcode: slli ; op1:x10; dest:x11; op1val:0x66666665; immval:0xd
TEST_IMM_OP( slli, x11, x10, 0xcccca000, 0x66666665, 0xd, x1, 248, x2)
inst_80:
// rs1_val==858993458,
// opcode: slli ; op1:x10; dest:x11; op1val:0x33333332; immval:0x1
TEST_IMM_OP( slli, x11, x10, 0x66666664, 0x33333332, 0x1, x1, 252, x2)
inst_81:
// rs1_val==1431655764,
// opcode: slli ; op1:x10; dest:x11; op1val:0x55555554; immval:0x1d
TEST_IMM_OP( slli, x11, x10, 0x80000000, 0x55555554, 0x1d, x1, 256, x2)
inst_82:
// rs1_val==46340,
// opcode: slli ; op1:x10; dest:x11; op1val:0xb504; immval:0x11
TEST_IMM_OP( slli, x11, x10, 0x6a080000, 0xb504, 0x11, x1, 260, x2)
inst_83:
// rs1_val==-46340,
// opcode: slli ; op1:x10; dest:x11; op1val:-0xb504; immval:0x13
TEST_IMM_OP( slli, x11, x10, 0x57e00000, -0xb504, 0x13, x1, 264, x2)
inst_84:
// rs1_val==1717986918,
// opcode: slli ; op1:x10; dest:x11; op1val:0x66666666; immval:0x1d
TEST_IMM_OP( slli, x11, x10, 0xc0000000, 0x66666666, 0x1d, x1, 268, x2)
inst_85:
// rs1_val==858993459,
// opcode: slli ; op1:x10; dest:x11; op1val:0x33333333; immval:0xa
TEST_IMM_OP( slli, x11, x10, 0xcccccc00, 0x33333333, 0xa, x1, 272, x2)
inst_86:
// rs1_val==5,
// opcode: slli ; op1:x10; dest:x11; op1val:0x5; immval:0x1b
TEST_IMM_OP( slli, x11, x10, 0x28000000, 0x5, 0x1b, x1, 276, x2)
inst_87:
// rs1_val == -67108865,
// opcode: slli ; op1:x10; dest:x11; op1val:-0x4000001; immval:0x7
TEST_IMM_OP( slli, x11, x10, 0xffffff80, -0x4000001, 0x7, x1, 280, x2)
inst_88:
// rs1_val == -131073,
// opcode: slli ; op1:x10; dest:x11; op1val:-0x20001; immval:0x10
TEST_IMM_OP( slli, x11, x10, 0xffff0000, -0x20001, 0x10, x1, 284, x2)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
signature_x5_0:
.fill 0*(XLEN/32),4,0xdeadbeef
signature_x5_1:
.fill 9*(XLEN/32),4,0xdeadbeef
signature_x1_0:
.fill 8*(XLEN/32),4,0xdeadbeef
signature_x1_1:
.fill 72*(XLEN/32),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

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@ -1,534 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version : 0.5.1
// timestamp : Mon Aug 2 08:58:53 2021 GMT
// usage : riscv_ctg \
// --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/rv32e.cgf \
// --base-isa rv32e \
// --randomize
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the sra instruction of the RISC-V E extension for the sra covergroup.
//
#define RVTEST_E
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32E")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",sra)
RVTEST_SIGBASE( x3,signature_x3_1)
inst_0:
// rs1 != rs2 and rs1 != rd and rs2 != rd, rs1==x11, rs2==x9, rd==x12, rs1_val < 0 and rs2_val == 0, rs1_val == -1431655766, rs1_val==-1431655766
// opcode: sra ; op1:x11; op2:x9; dest:x12; op1val:-0x55555556; op2val:0x0
TEST_RR_OP(sra, x12, x11, x9, -0x55555556, -0x55555556, 0x0, x3, 0, x5)
inst_1:
// rs1 == rd != rs2, rs1==x8, rs2==x12, rd==x8, rs2_val == 15, rs1_val == -524289, rs1_val < 0 and rs2_val > 0 and rs2_val < xlen
// opcode: sra ; op1:x8; op2:x12; dest:x8; op1val:-0x80001; op2val:0xf
TEST_RR_OP(sra, x8, x8, x12, -0x11, -0x80001, 0xf, x3, 4, x5)
inst_2:
// rs2 == rd != rs1, rs1==x10, rs2==x2, rd==x2, rs2_val == 23, rs1_val==3, rs1_val > 0 and rs2_val > 0 and rs2_val < xlen
// opcode: sra ; op1:x10; op2:x2; dest:x2; op1val:0x3; op2val:0x17
TEST_RR_OP(sra, x2, x10, x2, 0x0, 0x3, 0x17, x3, 8, x5)
inst_3:
// rs1 == rs2 != rd, rs1==x6, rs2==x6, rd==x4, rs2_val == 27,
// opcode: sra ; op1:x6; op2:x6; dest:x4; op1val:-0x8; op2val:-0x8
TEST_RR_OP(sra, x4, x6, x6, -0x1, -0x8, -0x8, x3, 12, x5)
inst_4:
// rs1 == rs2 == rd, rs1==x13, rs2==x13, rd==x13, rs2_val == 29, rs1_val==-1431655765
// opcode: sra ; op1:x13; op2:x13; dest:x13; op1val:-0x55555555; op2val:-0x55555555
TEST_RR_OP(sra, x13, x13, x13, -0xaaaab, -0x55555555, -0x55555555, x3, 16, x5)
inst_5:
// rs1==x0, rs2==x10, rd==x7, rs2_val == 30, rs1_val == 16384
// opcode: sra ; op1:x0; op2:x10; dest:x7; op1val:0x0; op2val:0x1e
TEST_RR_OP(sra, x7, x0, x10, 0x0, 0x0, 0x1e, x3, 20, x5)
inst_6:
// rs1==x1, rs2==x15, rd==x14, rs1_val == 2147483647, rs2_val == 21, rs1_val == (2**(xlen-1)-1) and rs2_val >= 0 and rs2_val < xlen
// opcode: sra ; op1:x1; op2:x15; dest:x14; op1val:0x7fffffff; op2val:0x15
TEST_RR_OP(sra, x14, x1, x15, 0x3ff, 0x7fffffff, 0x15, x3, 24, x5)
RVTEST_SIGBASE( x4,signature_x4_0)
inst_7:
// rs1==x3, rs2==x7, rd==x5, rs1_val == -1073741825, rs2_val == 1
// opcode: sra ; op1:x3; op2:x7; dest:x5; op1val:-0x40000001; op2val:0x1
TEST_RR_OP(sra, x5, x3, x7, -0x20000001, -0x40000001, 0x1, x4, 0, x6)
inst_8:
// rs1==x2, rs2==x8, rd==x15, rs1_val == -536870913,
// opcode: sra ; op1:x2; op2:x8; dest:x15; op1val:-0x20000001; op2val:0x7
TEST_RR_OP(sra, x15, x2, x8, -0x400001, -0x20000001, 0x7, x4, 4, x6)
inst_9:
// rs1==x7, rs2==x11, rd==x1, rs1_val == -268435457,
// opcode: sra ; op1:x7; op2:x11; dest:x1; op1val:-0x10000001; op2val:0x9
TEST_RR_OP(sra, x1, x7, x11, -0x80001, -0x10000001, 0x9, x4, 8, x6)
inst_10:
// rs1==x12, rs2==x0, rd==x9, rs1_val == -134217729,
// opcode: sra ; op1:x12; op2:x0; dest:x9; op1val:-0x8000001; op2val:0x0
TEST_RR_OP(sra, x9, x12, x0, -0x8000001, -0x8000001, 0x0, x4, 12, x6)
inst_11:
// rs1==x5, rs2==x14, rd==x10, rs1_val == -67108865,
// opcode: sra ; op1:x5; op2:x14; dest:x10; op1val:-0x4000001; op2val:0x17
TEST_RR_OP(sra, x10, x5, x14, -0x9, -0x4000001, 0x17, x4, 16, x6)
RVTEST_SIGBASE( x2,signature_x2_0)
inst_12:
// rs1==x4, rs2==x5, rd==x0, rs1_val == -33554433,
// opcode: sra ; op1:x4; op2:x5; dest:x0; op1val:-0x2000001; op2val:0x9
TEST_RR_OP(sra, x0, x4, x5, 0, -0x2000001, 0x9, x2, 0, x7)
inst_13:
// rs1==x15, rs2==x4, rd==x3, rs1_val == -16777217,
// opcode: sra ; op1:x15; op2:x4; dest:x3; op1val:-0x1000001; op2val:0xe
TEST_RR_OP(sra, x3, x15, x4, -0x401, -0x1000001, 0xe, x2, 4, x7)
inst_14:
// rs1==x9, rs2==x3, rd==x11, rs1_val == -8388609,
// opcode: sra ; op1:x9; op2:x3; dest:x11; op1val:-0x800001; op2val:0x11
TEST_RR_OP(sra, x11, x9, x3, -0x41, -0x800001, 0x11, x2, 8, x7)
inst_15:
// rs1==x14, rs2==x1, rd==x6, rs1_val == -4194305,
// opcode: sra ; op1:x14; op2:x1; dest:x6; op1val:-0x400001; op2val:0x1b
TEST_RR_OP(sra, x6, x14, x1, -0x1, -0x400001, 0x1b, x2, 12, x7)
inst_16:
// rs1_val == -2097153,
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x200001; op2val:0xf
TEST_RR_OP(sra, x12, x10, x11, -0x41, -0x200001, 0xf, x2, 16, x7)
inst_17:
// rs1_val == -1048577, rs2_val == 2
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x100001; op2val:0x2
TEST_RR_OP(sra, x12, x10, x11, -0x40001, -0x100001, 0x2, x2, 20, x1)
inst_18:
// rs1_val == -262145,
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x40001; op2val:0x9
TEST_RR_OP(sra, x12, x10, x11, -0x201, -0x40001, 0x9, x2, 24, x1)
inst_19:
// rs1_val == -131073,
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x20001; op2val:0x1e
TEST_RR_OP(sra, x12, x10, x11, -0x1, -0x20001, 0x1e, x2, 28, x1)
inst_20:
// rs1_val == -65537, rs2_val == 16
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x10001; op2val:0x10
TEST_RR_OP(sra, x12, x10, x11, -0x2, -0x10001, 0x10, x2, 32, x1)
inst_21:
// rs1_val == -32769,
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x8001; op2val:0x1b
TEST_RR_OP(sra, x12, x10, x11, -0x1, -0x8001, 0x1b, x2, 36, x1)
inst_22:
// rs1_val == -16385,
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x4001; op2val:0x2
TEST_RR_OP(sra, x12, x10, x11, -0x1001, -0x4001, 0x2, x2, 40, x1)
inst_23:
// rs1_val == -8193,
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x2001; op2val:0x1e
TEST_RR_OP(sra, x12, x10, x11, -0x1, -0x2001, 0x1e, x2, 44, x1)
inst_24:
// rs1_val == -4097,
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x1001; op2val:0xf
TEST_RR_OP(sra, x12, x10, x11, -0x1, -0x1001, 0xf, x2, 48, x1)
inst_25:
// rs1_val == -2049,
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x801; op2val:0x12
TEST_RR_OP(sra, x12, x10, x11, -0x1, -0x801, 0x12, x2, 52, x1)
inst_26:
// rs1_val == -1025,
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x401; op2val:0x12
TEST_RR_OP(sra, x12, x10, x11, -0x1, -0x401, 0x12, x2, 56, x1)
inst_27:
// rs1_val == -513,
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x201; op2val:0x1b
TEST_RR_OP(sra, x12, x10, x11, -0x1, -0x201, 0x1b, x2, 60, x1)
inst_28:
// rs1_val == -257,
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x101; op2val:0x9
TEST_RR_OP(sra, x12, x10, x11, -0x1, -0x101, 0x9, x2, 64, x1)
inst_29:
// rs1_val == -129,
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x81; op2val:0x6
TEST_RR_OP(sra, x12, x10, x11, -0x3, -0x81, 0x6, x2, 68, x1)
inst_30:
// rs1_val == -65,
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x41; op2val:0x1d
TEST_RR_OP(sra, x12, x10, x11, -0x1, -0x41, 0x1d, x2, 72, x1)
inst_31:
// rs1_val == -33, rs2_val == 8
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x21; op2val:0x8
TEST_RR_OP(sra, x12, x10, x11, -0x1, -0x21, 0x8, x2, 76, x1)
inst_32:
// rs1_val == -17,
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x11; op2val:0xe
TEST_RR_OP(sra, x12, x10, x11, -0x1, -0x11, 0xe, x2, 80, x1)
inst_33:
// rs1_val == -9,
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x9; op2val:0x9
TEST_RR_OP(sra, x12, x10, x11, -0x1, -0x9, 0x9, x2, 84, x1)
inst_34:
// rs1_val == -5,
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x5; op2val:0xe
TEST_RR_OP(sra, x12, x10, x11, -0x1, -0x5, 0xe, x2, 88, x1)
inst_35:
// rs1_val == -3,
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x3; op2val:0x15
TEST_RR_OP(sra, x12, x10, x11, -0x1, -0x3, 0x15, x2, 92, x1)
inst_36:
// rs1_val == -2,
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x2; op2val:0x10
TEST_RR_OP(sra, x12, x10, x11, -0x1, -0x2, 0x10, x2, 96, x1)
inst_37:
// rs2_val == 4, rs1_val==2, rs1_val == 2
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x2; op2val:0x4
TEST_RR_OP(sra, x12, x10, x11, 0x0, 0x2, 0x4, x2, 100, x1)
inst_38:
// rs1_val == -2147483648, rs1_val == (-2**(xlen-1)) and rs2_val >= 0 and rs2_val < xlen
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x80000000; op2val:0x13
TEST_RR_OP(sra, x12, x10, x11, -0x1000, -0x80000000, 0x13, x2, 104, x1)
inst_39:
// rs1_val == 1073741824,
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x40000000; op2val:0x1b
TEST_RR_OP(sra, x12, x10, x11, 0x8, 0x40000000, 0x1b, x2, 108, x1)
inst_40:
// rs1_val == 536870912,
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x20000000; op2val:0x9
TEST_RR_OP(sra, x12, x10, x11, 0x100000, 0x20000000, 0x9, x2, 112, x1)
inst_41:
// rs1_val == 268435456,
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x10000000; op2val:0xb
TEST_RR_OP(sra, x12, x10, x11, 0x20000, 0x10000000, 0xb, x2, 116, x1)
inst_42:
// rs1_val == 134217728,
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x8000000; op2val:0x17
TEST_RR_OP(sra, x12, x10, x11, 0x10, 0x8000000, 0x17, x2, 120, x1)
inst_43:
// rs1_val == 67108864,
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x4000000; op2val:0xc
TEST_RR_OP(sra, x12, x10, x11, 0x4000, 0x4000000, 0xc, x2, 124, x1)
inst_44:
// rs1_val == 33554432,
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x2000000; op2val:0x11
TEST_RR_OP(sra, x12, x10, x11, 0x100, 0x2000000, 0x11, x2, 128, x1)
inst_45:
// rs1_val == 16777216,
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x1000000; op2val:0x11
TEST_RR_OP(sra, x12, x10, x11, 0x80, 0x1000000, 0x11, x2, 132, x1)
inst_46:
// rs1_val == 8388608, rs1_val > 0 and rs2_val == 0
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x800000; op2val:0x0
TEST_RR_OP(sra, x12, x10, x11, 0x800000, 0x800000, 0x0, x2, 136, x1)
inst_47:
// rs1_val == 4194304,
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x400000; op2val:0xb
TEST_RR_OP(sra, x12, x10, x11, 0x800, 0x400000, 0xb, x2, 140, x1)
inst_48:
// rs1_val == 2097152,
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x200000; op2val:0x9
TEST_RR_OP(sra, x12, x10, x11, 0x1000, 0x200000, 0x9, x2, 144, x1)
inst_49:
// rs1_val == 1048576,
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x100000; op2val:0x1
TEST_RR_OP(sra, x12, x10, x11, 0x80000, 0x100000, 0x1, x2, 148, x1)
inst_50:
// rs1_val == 524288, rs2_val == 10
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x80000; op2val:0xa
TEST_RR_OP(sra, x12, x10, x11, 0x200, 0x80000, 0xa, x2, 152, x1)
inst_51:
// rs1_val == 262144,
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x40000; op2val:0x1f
TEST_RR_OP(sra, x12, x10, x11, 0x0, 0x40000, 0x1f, x2, 156, x1)
inst_52:
// rs1_val == 131072,
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x20000; op2val:0xb
TEST_RR_OP(sra, x12, x10, x11, 0x40, 0x20000, 0xb, x2, 160, x1)
inst_53:
// rs1_val == 65536,
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x10000; op2val:0xa
TEST_RR_OP(sra, x12, x10, x11, 0x40, 0x10000, 0xa, x2, 164, x1)
inst_54:
// rs1_val == 32768,
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x8000; op2val:0x10
TEST_RR_OP(sra, x12, x10, x11, 0x0, 0x8000, 0x10, x2, 168, x1)
inst_55:
// rs1_val == 8192,
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x2000; op2val:0xf
TEST_RR_OP(sra, x12, x10, x11, 0x0, 0x2000, 0xf, x2, 172, x1)
inst_56:
// rs1_val == 4096,
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x1000; op2val:0x1d
TEST_RR_OP(sra, x12, x10, x11, 0x0, 0x1000, 0x1d, x2, 176, x1)
inst_57:
// rs1_val == 2048,
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x800; op2val:0x8
TEST_RR_OP(sra, x12, x10, x11, 0x8, 0x800, 0x8, x2, 180, x1)
inst_58:
// rs1_val == 1024,
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x400; op2val:0x5
TEST_RR_OP(sra, x12, x10, x11, 0x20, 0x400, 0x5, x2, 184, x1)
inst_59:
// rs1_val == 512,
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x200; op2val:0x1b
TEST_RR_OP(sra, x12, x10, x11, 0x0, 0x200, 0x1b, x2, 188, x1)
inst_60:
// rs1_val == 256,
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x100; op2val:0xd
TEST_RR_OP(sra, x12, x10, x11, 0x0, 0x100, 0xd, x2, 192, x1)
inst_61:
// rs1_val == 128,
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x80; op2val:0x3
TEST_RR_OP(sra, x12, x10, x11, 0x10, 0x80, 0x3, x2, 196, x1)
inst_62:
// rs1_val == 64,
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x40; op2val:0x5
TEST_RR_OP(sra, x12, x10, x11, 0x2, 0x40, 0x5, x2, 200, x1)
inst_63:
// rs1_val == 32,
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x20; op2val:0x5
TEST_RR_OP(sra, x12, x10, x11, 0x1, 0x20, 0x5, x2, 204, x1)
inst_64:
// rs1_val == 16,
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x10; op2val:0x8
TEST_RR_OP(sra, x12, x10, x11, 0x0, 0x10, 0x8, x2, 208, x1)
inst_65:
// rs1_val == 8,
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x8; op2val:0x3
TEST_RR_OP(sra, x12, x10, x11, 0x1, 0x8, 0x3, x2, 212, x1)
inst_66:
// rs1_val == 4, rs1_val==4
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x4; op2val:0xb
TEST_RR_OP(sra, x12, x10, x11, 0x0, 0x4, 0xb, x2, 216, x1)
inst_67:
// rs1_val == 1, rs1_val == 1 and rs2_val >= 0 and rs2_val < xlen
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x1; op2val:0x8
TEST_RR_OP(sra, x12, x10, x11, 0x0, 0x1, 0x8, x2, 220, x1)
inst_68:
// rs1_val==46341,
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0xb505; op2val:0x1e
TEST_RR_OP(sra, x12, x10, x11, 0x0, 0xb505, 0x1e, x2, 224, x1)
inst_69:
// rs1_val==-46339,
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0xb503; op2val:0x8
TEST_RR_OP(sra, x12, x10, x11, -0xb6, -0xb503, 0x8, x2, 228, x1)
inst_70:
// rs1_val==1717986919,
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x66666667; op2val:0x10
TEST_RR_OP(sra, x12, x10, x11, 0x6666, 0x66666667, 0x10, x2, 232, x1)
inst_71:
// rs1_val==858993460,
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x33333334; op2val:0xa
TEST_RR_OP(sra, x12, x10, x11, 0xccccc, 0x33333334, 0xa, x2, 236, x1)
inst_72:
// rs1_val==6,
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x6; op2val:0x13
TEST_RR_OP(sra, x12, x10, x11, 0x0, 0x6, 0x13, x2, 240, x1)
inst_73:
// rs1_val == 1431655765, rs1_val==1431655765
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x55555555; op2val:0x15
TEST_RR_OP(sra, x12, x10, x11, 0x2aa, 0x55555555, 0x15, x2, 244, x1)
inst_74:
// rs1_val == 0 and rs2_val >= 0 and rs2_val < xlen, rs1_val==0
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x0; op2val:0xa
TEST_RR_OP(sra, x12, x10, x11, 0x0, 0x0, 0xa, x2, 248, x1)
inst_75:
// rs1_val == rs2_val and rs2_val > 0 and rs2_val < xlen,
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x7; op2val:0x7
TEST_RR_OP(sra, x12, x10, x11, 0x0, 0x7, 0x7, x2, 252, x1)
inst_76:
// rs1_val==1431655766,
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x55555556; op2val:0x13
TEST_RR_OP(sra, x12, x10, x11, 0xaaa, 0x55555556, 0x13, x2, 256, x1)
inst_77:
// rs1_val==46339,
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0xb503; op2val:0x7
TEST_RR_OP(sra, x12, x10, x11, 0x16a, 0xb503, 0x7, x2, 260, x1)
inst_78:
// rs1_val==1717986917,
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x66666665; op2val:0x1b
TEST_RR_OP(sra, x12, x10, x11, 0xc, 0x66666665, 0x1b, x2, 264, x1)
inst_79:
// rs1_val==858993458,
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x33333332; op2val:0x15
TEST_RR_OP(sra, x12, x10, x11, 0x199, 0x33333332, 0x15, x2, 268, x1)
inst_80:
// rs1_val==1431655764,
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x55555554; op2val:0x7
TEST_RR_OP(sra, x12, x10, x11, 0xaaaaaa, 0x55555554, 0x7, x2, 272, x1)
inst_81:
// rs1_val==46340,
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0xb504; op2val:0xf
TEST_RR_OP(sra, x12, x10, x11, 0x1, 0xb504, 0xf, x2, 276, x1)
inst_82:
// rs1_val==-46340,
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0xb504; op2val:0x15
TEST_RR_OP(sra, x12, x10, x11, -0x1, -0xb504, 0x15, x2, 280, x1)
inst_83:
// rs1_val==1717986918,
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x66666666; op2val:0x1e
TEST_RR_OP(sra, x12, x10, x11, 0x1, 0x66666666, 0x1e, x2, 284, x1)
inst_84:
// rs1_val==858993459,
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x33333333; op2val:0x1d
TEST_RR_OP(sra, x12, x10, x11, 0x1, 0x33333333, 0x1d, x2, 288, x1)
inst_85:
// rs1_val==5,
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x5; op2val:0x1d
TEST_RR_OP(sra, x12, x10, x11, 0x0, 0x5, 0x1d, x2, 292, x1)
inst_86:
// rs2_val == 29, rs1_val==-1431655765
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555; op2val:0x1d
TEST_RR_OP(sra, x12, x10, x11, -0x3, -0x55555555, 0x1d, x2, 296, x1)
inst_87:
// rs2_val == 30, rs1_val == 16384
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x4000; op2val:0x1e
TEST_RR_OP(sra, x12, x10, x11, 0x0, 0x4000, 0x1e, x2, 300, x1)
inst_88:
// rs1_val == -134217729,
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x8000001; op2val:0xb
TEST_RR_OP(sra, x12, x10, x11, -0x10001, -0x8000001, 0xb, x2, 304, x1)
inst_89:
// rs1_val == -33554433,
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x2000001; op2val:0x9
TEST_RR_OP(sra, x12, x10, x11, -0x10001, -0x2000001, 0x9, x2, 308, x1)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
signature_x3_0:
.fill 0*(XLEN/32),4,0xdeadbeef
signature_x3_1:
.fill 7*(XLEN/32),4,0xdeadbeef
signature_x4_0:
.fill 5*(XLEN/32),4,0xdeadbeef
signature_x2_0:
.fill 78*(XLEN/32),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

519
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-srai-01.S
View File

@ -1,519 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version : 0.5.1
// timestamp : Mon Aug 2 08:58:53 2021 GMT
// usage : riscv_ctg \
// --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/rv32e.cgf \
// --base-isa rv32e \
// --randomize
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the srai instruction of the RISC-V E extension for the srai covergroup.
//
#define RVTEST_E
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32E")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",srai)
RVTEST_SIGBASE( x1,signature_x1_1)
inst_0:
// rs1 != rd, rs1==x0, rd==x2, rs1_val < 0 and imm_val == (xlen-1), rs1_val == -536870913, rs1_val < 0 and imm_val > 0 and imm_val < xlen
// opcode: srai ; op1:x0; dest:x2; op1val:0x0; immval:0x1f
TEST_IMM_OP( srai, x2, x0, 0x0, 0x0, 0x1f, x1, 0, x5)
inst_1:
// rs1 == rd, rs1==x14, rd==x14, rs1_val == 2147483647, rs1_val == (2**(xlen-1)-1) and imm_val >= 0 and imm_val < xlen, rs1_val > 0 and imm_val > 0 and imm_val < xlen
// opcode: srai ; op1:x14; dest:x14; op1val:0x7fffffff; immval:0xc
TEST_IMM_OP( srai, x14, x14, 0x7ffff, 0x7fffffff, 0xc, x1, 4, x5)
inst_2:
// rs1==x3, rd==x11, rs1_val == -1073741825,
// opcode: srai ; op1:x3; dest:x11; op1val:-0x40000001; immval:0x7
TEST_IMM_OP( srai, x11, x3, -0x800001, -0x40000001, 0x7, x1, 8, x5)
inst_3:
// rs1==x15, rd==x4, rs1_val == -268435457, rs1_val < 0 and imm_val == 0
// opcode: srai ; op1:x15; dest:x4; op1val:-0x10000001; immval:0x0
TEST_IMM_OP( srai, x4, x15, -0x10000001, -0x10000001, 0x0, x1, 12, x5)
inst_4:
// rs1==x7, rd==x10, rs1_val == -134217729, imm_val == 21
// opcode: srai ; op1:x7; dest:x10; op1val:-0x8000001; immval:0x15
TEST_IMM_OP( srai, x10, x7, -0x41, -0x8000001, 0x15, x1, 16, x5)
inst_5:
// rs1==x8, rd==x6, rs1_val == -67108865, imm_val == 10
// opcode: srai ; op1:x8; dest:x6; op1val:-0x4000001; immval:0xa
TEST_IMM_OP( srai, x6, x8, -0x10001, -0x4000001, 0xa, x1, 20, x5)
inst_6:
// rs1==x9, rd==x13, rs1_val == -33554433, imm_val == 2
// opcode: srai ; op1:x9; dest:x13; op1val:-0x2000001; immval:0x2
TEST_IMM_OP( srai, x13, x9, -0x800001, -0x2000001, 0x2, x1, 24, x5)
RVTEST_SIGBASE( x3,signature_x3_0)
inst_7:
// rs1==x5, rd==x0, rs1_val == -16777217,
// opcode: srai ; op1:x5; dest:x0; op1val:-0x1000001; immval:0x12
TEST_IMM_OP( srai, x0, x5, 0, -0x1000001, 0x12, x3, 0, x6)
inst_8:
// rs1==x10, rd==x8, rs1_val == -8388609, imm_val == 30
// opcode: srai ; op1:x10; dest:x8; op1val:-0x800001; immval:0x1e
TEST_IMM_OP( srai, x8, x10, -0x1, -0x800001, 0x1e, x3, 4, x6)
inst_9:
// rs1==x13, rd==x5, rs1_val == -4194305,
// opcode: srai ; op1:x13; dest:x5; op1val:-0x400001; immval:0x9
TEST_IMM_OP( srai, x5, x13, -0x2001, -0x400001, 0x9, x3, 8, x6)
inst_10:
// rs1==x4, rd==x12, rs1_val == -2097153,
// opcode: srai ; op1:x4; dest:x12; op1val:-0x200001; immval:0x7
TEST_IMM_OP( srai, x12, x4, -0x4001, -0x200001, 0x7, x3, 12, x6)
inst_11:
// rs1==x12, rd==x7, rs1_val == -1048577,
// opcode: srai ; op1:x12; dest:x7; op1val:-0x100001; immval:0x7
TEST_IMM_OP( srai, x7, x12, -0x2001, -0x100001, 0x7, x3, 16, x6)
inst_12:
// rs1==x2, rd==x15, rs1_val == -524289,
// opcode: srai ; op1:x2; dest:x15; op1val:-0x80001; immval:0x7
TEST_IMM_OP( srai, x15, x2, -0x1001, -0x80001, 0x7, x3, 20, x6)
inst_13:
// rs1==x1, rd==x9, rs1_val == -262145, imm_val == 8
// opcode: srai ; op1:x1; dest:x9; op1val:-0x40001; immval:0x8
TEST_IMM_OP( srai, x9, x1, -0x401, -0x40001, 0x8, x3, 24, x6)
inst_14:
// rs1==x6, rd==x1, rs1_val == -131073,
// opcode: srai ; op1:x6; dest:x1; op1val:-0x20001; immval:0x13
TEST_IMM_OP( srai, x1, x6, -0x1, -0x20001, 0x13, x3, 28, x2)
RVTEST_SIGBASE( x1,signature_x1_2)
inst_15:
// rs1==x11, rd==x3, rs1_val == -65537, imm_val == 4
// opcode: srai ; op1:x11; dest:x3; op1val:-0x10001; immval:0x4
TEST_IMM_OP( srai, x3, x11, -0x1001, -0x10001, 0x4, x1, 0, x2)
inst_16:
// rs1_val == -32769,
// opcode: srai ; op1:x10; dest:x11; op1val:-0x8001; immval:0x7
TEST_IMM_OP( srai, x11, x10, -0x101, -0x8001, 0x7, x1, 4, x2)
inst_17:
// rs1_val == -16385, imm_val == 16
// opcode: srai ; op1:x10; dest:x11; op1val:-0x4001; immval:0x10
TEST_IMM_OP( srai, x11, x10, -0x1, -0x4001, 0x10, x1, 8, x2)
inst_18:
// rs1_val == -8193,
// opcode: srai ; op1:x10; dest:x11; op1val:-0x2001; immval:0x13
TEST_IMM_OP( srai, x11, x10, -0x1, -0x2001, 0x13, x1, 12, x2)
inst_19:
// rs1_val == -4097,
// opcode: srai ; op1:x10; dest:x11; op1val:-0x1001; immval:0x1e
TEST_IMM_OP( srai, x11, x10, -0x1, -0x1001, 0x1e, x1, 16, x2)
inst_20:
// rs1_val == -2049, imm_val == 15
// opcode: srai ; op1:x10; dest:x11; op1val:-0x801; immval:0xf
TEST_IMM_OP( srai, x11, x10, -0x1, -0x801, 0xf, x1, 20, x2)
inst_21:
// rs1_val == -1025,
// opcode: srai ; op1:x10; dest:x11; op1val:-0x401; immval:0x11
TEST_IMM_OP( srai, x11, x10, -0x1, -0x401, 0x11, x1, 24, x2)
inst_22:
// rs1_val == -513,
// opcode: srai ; op1:x10; dest:x11; op1val:-0x201; immval:0xb
TEST_IMM_OP( srai, x11, x10, -0x1, -0x201, 0xb, x1, 28, x2)
inst_23:
// rs1_val == -257, imm_val == 1
// opcode: srai ; op1:x10; dest:x11; op1val:-0x101; immval:0x1
TEST_IMM_OP( srai, x11, x10, -0x81, -0x101, 0x1, x1, 32, x2)
inst_24:
// rs1_val == -129,
// opcode: srai ; op1:x10; dest:x11; op1val:-0x81; immval:0xc
TEST_IMM_OP( srai, x11, x10, -0x1, -0x81, 0xc, x1, 36, x2)
inst_25:
// rs1_val == -65,
// opcode: srai ; op1:x10; dest:x11; op1val:-0x41; immval:0x13
TEST_IMM_OP( srai, x11, x10, -0x1, -0x41, 0x13, x1, 40, x2)
inst_26:
// rs1_val == -33,
// opcode: srai ; op1:x10; dest:x11; op1val:-0x21; immval:0xd
TEST_IMM_OP( srai, x11, x10, -0x1, -0x21, 0xd, x1, 44, x2)
inst_27:
// rs1_val == -17,
// opcode: srai ; op1:x10; dest:x11; op1val:-0x11; immval:0x1e
TEST_IMM_OP( srai, x11, x10, -0x1, -0x11, 0x1e, x1, 48, x2)
inst_28:
// rs1_val == -9,
// opcode: srai ; op1:x10; dest:x11; op1val:-0x9; immval:0x12
TEST_IMM_OP( srai, x11, x10, -0x1, -0x9, 0x12, x1, 52, x2)
inst_29:
// rs1_val == -5,
// opcode: srai ; op1:x10; dest:x11; op1val:-0x5; immval:0xf
TEST_IMM_OP( srai, x11, x10, -0x1, -0x5, 0xf, x1, 56, x2)
inst_30:
// rs1_val == -3,
// opcode: srai ; op1:x10; dest:x11; op1val:-0x3; immval:0x9
TEST_IMM_OP( srai, x11, x10, -0x1, -0x3, 0x9, x1, 60, x2)
inst_31:
// rs1_val == -2,
// opcode: srai ; op1:x10; dest:x11; op1val:-0x2; immval:0x1f
TEST_IMM_OP( srai, x11, x10, -0x1, -0x2, 0x1f, x1, 64, x2)
inst_32:
// imm_val == 23, rs1_val == 4096
// opcode: srai ; op1:x10; dest:x11; op1val:0x1000; immval:0x17
TEST_IMM_OP( srai, x11, x10, 0x0, 0x1000, 0x17, x1, 68, x2)
inst_33:
// imm_val == 27, rs1_val == -1431655766, rs1_val==-1431655766
// opcode: srai ; op1:x10; dest:x11; op1val:-0x55555556; immval:0x1b
TEST_IMM_OP( srai, x11, x10, -0xb, -0x55555556, 0x1b, x1, 72, x2)
inst_34:
// imm_val == 29, rs1_val == 0 and imm_val >= 0 and imm_val < xlen, rs1_val==0
// opcode: srai ; op1:x10; dest:x11; op1val:0x0; immval:0x1d
TEST_IMM_OP( srai, x11, x10, 0x0, 0x0, 0x1d, x1, 76, x2)
inst_35:
// rs1_val == -2147483648, rs1_val == (-2**(xlen-1)) and imm_val >= 0 and imm_val < xlen
// opcode: srai ; op1:x10; dest:x11; op1val:-0x80000000; immval:0x2
TEST_IMM_OP( srai, x11, x10, -0x20000000, -0x80000000, 0x2, x1, 80, x2)
inst_36:
// rs1_val == 1073741824,
// opcode: srai ; op1:x10; dest:x11; op1val:0x40000000; immval:0x2
TEST_IMM_OP( srai, x11, x10, 0x10000000, 0x40000000, 0x2, x1, 84, x2)
inst_37:
// rs1_val == 536870912,
// opcode: srai ; op1:x10; dest:x11; op1val:0x20000000; immval:0x4
TEST_IMM_OP( srai, x11, x10, 0x2000000, 0x20000000, 0x4, x1, 88, x2)
inst_38:
// rs1_val == 268435456,
// opcode: srai ; op1:x10; dest:x11; op1val:0x10000000; immval:0xe
TEST_IMM_OP( srai, x11, x10, 0x4000, 0x10000000, 0xe, x1, 92, x2)
inst_39:
// rs1_val == 134217728,
// opcode: srai ; op1:x10; dest:x11; op1val:0x8000000; immval:0x15
TEST_IMM_OP( srai, x11, x10, 0x40, 0x8000000, 0x15, x1, 96, x2)
inst_40:
// rs1_val == 67108864,
// opcode: srai ; op1:x10; dest:x11; op1val:0x4000000; immval:0xc
TEST_IMM_OP( srai, x11, x10, 0x4000, 0x4000000, 0xc, x1, 100, x2)
inst_41:
// rs1_val == 33554432,
// opcode: srai ; op1:x10; dest:x11; op1val:0x2000000; immval:0x9
TEST_IMM_OP( srai, x11, x10, 0x10000, 0x2000000, 0x9, x1, 104, x2)
inst_42:
// rs1_val == 16777216,
// opcode: srai ; op1:x10; dest:x11; op1val:0x1000000; immval:0xe
TEST_IMM_OP( srai, x11, x10, 0x400, 0x1000000, 0xe, x1, 108, x2)
inst_43:
// rs1_val == 8388608,
// opcode: srai ; op1:x10; dest:x11; op1val:0x800000; immval:0xb
TEST_IMM_OP( srai, x11, x10, 0x1000, 0x800000, 0xb, x1, 112, x2)
inst_44:
// rs1_val == 4194304,
// opcode: srai ; op1:x10; dest:x11; op1val:0x400000; immval:0x11
TEST_IMM_OP( srai, x11, x10, 0x20, 0x400000, 0x11, x1, 116, x2)
inst_45:
// rs1_val == 2097152,
// opcode: srai ; op1:x10; dest:x11; op1val:0x200000; immval:0x4
TEST_IMM_OP( srai, x11, x10, 0x20000, 0x200000, 0x4, x1, 120, x2)
inst_46:
// rs1_val == 1048576,
// opcode: srai ; op1:x10; dest:x11; op1val:0x100000; immval:0x1b
TEST_IMM_OP( srai, x11, x10, 0x0, 0x100000, 0x1b, x1, 124, x2)
inst_47:
// rs1_val == 524288,
// opcode: srai ; op1:x10; dest:x11; op1val:0x80000; immval:0x17
TEST_IMM_OP( srai, x11, x10, 0x0, 0x80000, 0x17, x1, 128, x2)
inst_48:
// rs1_val == 262144,
// opcode: srai ; op1:x10; dest:x11; op1val:0x40000; immval:0x11
TEST_IMM_OP( srai, x11, x10, 0x2, 0x40000, 0x11, x1, 132, x2)
inst_49:
// rs1_val == 131072,
// opcode: srai ; op1:x10; dest:x11; op1val:0x20000; immval:0x9
TEST_IMM_OP( srai, x11, x10, 0x100, 0x20000, 0x9, x1, 136, x2)
inst_50:
// rs1_val == 65536,
// opcode: srai ; op1:x10; dest:x11; op1val:0x10000; immval:0x10
TEST_IMM_OP( srai, x11, x10, 0x1, 0x10000, 0x10, x1, 140, x2)
inst_51:
// rs1_val == 32768,
// opcode: srai ; op1:x10; dest:x11; op1val:0x8000; immval:0xa
TEST_IMM_OP( srai, x11, x10, 0x20, 0x8000, 0xa, x1, 144, x2)
inst_52:
// rs1_val == 16384,
// opcode: srai ; op1:x10; dest:x11; op1val:0x4000; immval:0x12
TEST_IMM_OP( srai, x11, x10, 0x0, 0x4000, 0x12, x1, 148, x2)
inst_53:
// rs1_val == 8192,
// opcode: srai ; op1:x10; dest:x11; op1val:0x2000; immval:0x5
TEST_IMM_OP( srai, x11, x10, 0x100, 0x2000, 0x5, x1, 152, x2)
inst_54:
// rs1_val == 2048,
// opcode: srai ; op1:x10; dest:x11; op1val:0x800; immval:0x6
TEST_IMM_OP( srai, x11, x10, 0x20, 0x800, 0x6, x1, 156, x2)
inst_55:
// rs1_val == 1024,
// opcode: srai ; op1:x10; dest:x11; op1val:0x400; immval:0x17
TEST_IMM_OP( srai, x11, x10, 0x0, 0x400, 0x17, x1, 160, x2)
inst_56:
// rs1_val == 512,
// opcode: srai ; op1:x10; dest:x11; op1val:0x200; immval:0xb
TEST_IMM_OP( srai, x11, x10, 0x0, 0x200, 0xb, x1, 164, x2)
inst_57:
// rs1_val == 256,
// opcode: srai ; op1:x10; dest:x11; op1val:0x100; immval:0x9
TEST_IMM_OP( srai, x11, x10, 0x0, 0x100, 0x9, x1, 168, x2)
inst_58:
// rs1_val == 128,
// opcode: srai ; op1:x10; dest:x11; op1val:0x80; immval:0x2
TEST_IMM_OP( srai, x11, x10, 0x20, 0x80, 0x2, x1, 172, x2)
inst_59:
// rs1_val == 64,
// opcode: srai ; op1:x10; dest:x11; op1val:0x40; immval:0x11
TEST_IMM_OP( srai, x11, x10, 0x0, 0x40, 0x11, x1, 176, x2)
inst_60:
// rs1_val == 32,
// opcode: srai ; op1:x10; dest:x11; op1val:0x20; immval:0xb
TEST_IMM_OP( srai, x11, x10, 0x0, 0x20, 0xb, x1, 180, x2)
inst_61:
// rs1_val == 16,
// opcode: srai ; op1:x10; dest:x11; op1val:0x10; immval:0xd
TEST_IMM_OP( srai, x11, x10, 0x0, 0x10, 0xd, x1, 184, x2)
inst_62:
// rs1_val == 8, rs1_val > 0 and imm_val == (xlen-1)
// opcode: srai ; op1:x10; dest:x11; op1val:0x8; immval:0x1f
TEST_IMM_OP( srai, x11, x10, 0x0, 0x8, 0x1f, x1, 188, x2)
inst_63:
// rs1_val == 4, rs1_val==4
// opcode: srai ; op1:x10; dest:x11; op1val:0x4; immval:0x1f
TEST_IMM_OP( srai, x11, x10, 0x0, 0x4, 0x1f, x1, 192, x2)
inst_64:
// rs1_val == 2, rs1_val==2
// opcode: srai ; op1:x10; dest:x11; op1val:0x2; immval:0xc
TEST_IMM_OP( srai, x11, x10, 0x0, 0x2, 0xc, x1, 196, x2)
inst_65:
// rs1_val == 1, rs1_val == 1 and imm_val >= 0 and imm_val < xlen
// opcode: srai ; op1:x10; dest:x11; op1val:0x1; immval:0x9
TEST_IMM_OP( srai, x11, x10, 0x0, 0x1, 0x9, x1, 200, x2)
inst_66:
// rs1_val==46341,
// opcode: srai ; op1:x10; dest:x11; op1val:0xb505; immval:0xb
TEST_IMM_OP( srai, x11, x10, 0x16, 0xb505, 0xb, x1, 204, x2)
inst_67:
// rs1_val==-46339,
// opcode: srai ; op1:x10; dest:x11; op1val:-0xb503; immval:0xf
TEST_IMM_OP( srai, x11, x10, -0x2, -0xb503, 0xf, x1, 208, x2)
inst_68:
// rs1_val==1717986919,
// opcode: srai ; op1:x10; dest:x11; op1val:0x66666667; immval:0x8
TEST_IMM_OP( srai, x11, x10, 0x666666, 0x66666667, 0x8, x1, 212, x2)
inst_69:
// rs1_val==858993460,
// opcode: srai ; op1:x10; dest:x11; op1val:0x33333334; immval:0xc
TEST_IMM_OP( srai, x11, x10, 0x33333, 0x33333334, 0xc, x1, 216, x2)
inst_70:
// rs1_val==6,
// opcode: srai ; op1:x10; dest:x11; op1val:0x6; immval:0x17
TEST_IMM_OP( srai, x11, x10, 0x0, 0x6, 0x17, x1, 220, x2)
inst_71:
// rs1_val==-1431655765,
// opcode: srai ; op1:x10; dest:x11; op1val:-0x55555555; immval:0xb
TEST_IMM_OP( srai, x11, x10, -0xaaaab, -0x55555555, 0xb, x1, 224, x2)
inst_72:
// rs1_val==3,
// opcode: srai ; op1:x10; dest:x11; op1val:0x3; immval:0x8
TEST_IMM_OP( srai, x11, x10, 0x0, 0x3, 0x8, x1, 228, x2)
inst_73:
// rs1_val == 1431655765, rs1_val==1431655765
// opcode: srai ; op1:x10; dest:x11; op1val:0x55555555; immval:0x1e
TEST_IMM_OP( srai, x11, x10, 0x1, 0x55555555, 0x1e, x1, 232, x2)
inst_74:
// rs1_val == imm_val and imm_val > 0 and imm_val < xlen, rs1_val==5
// opcode: srai ; op1:x10; dest:x11; op1val:0x5; immval:0x5
TEST_IMM_OP( srai, x11, x10, 0x0, 0x5, 0x5, x1, 236, x2)
inst_75:
// rs1_val > 0 and imm_val == 0,
// opcode: srai ; op1:x10; dest:x11; op1val:0x2; immval:0x0
TEST_IMM_OP( srai, x11, x10, 0x2, 0x2, 0x0, x1, 240, x2)
inst_76:
// rs1_val==1431655766,
// opcode: srai ; op1:x10; dest:x11; op1val:0x55555556; immval:0x2
TEST_IMM_OP( srai, x11, x10, 0x15555555, 0x55555556, 0x2, x1, 244, x2)
inst_77:
// rs1_val==46339,
// opcode: srai ; op1:x10; dest:x11; op1val:0xb503; immval:0x1
TEST_IMM_OP( srai, x11, x10, 0x5a81, 0xb503, 0x1, x1, 248, x2)
inst_78:
// rs1_val==1717986917,
// opcode: srai ; op1:x10; dest:x11; op1val:0x66666665; immval:0x10
TEST_IMM_OP( srai, x11, x10, 0x6666, 0x66666665, 0x10, x1, 252, x2)
inst_79:
// rs1_val==858993458,
// opcode: srai ; op1:x10; dest:x11; op1val:0x33333332; immval:0x12
TEST_IMM_OP( srai, x11, x10, 0xccc, 0x33333332, 0x12, x1, 256, x2)
inst_80:
// rs1_val==1431655764,
// opcode: srai ; op1:x10; dest:x11; op1val:0x55555554; immval:0x1b
TEST_IMM_OP( srai, x11, x10, 0xa, 0x55555554, 0x1b, x1, 260, x2)
inst_81:
// rs1_val==46340,
// opcode: srai ; op1:x10; dest:x11; op1val:0xb504; immval:0x1e
TEST_IMM_OP( srai, x11, x10, 0x0, 0xb504, 0x1e, x1, 264, x2)
inst_82:
// rs1_val==-46340,
// opcode: srai ; op1:x10; dest:x11; op1val:-0xb504; immval:0x11
TEST_IMM_OP( srai, x11, x10, -0x1, -0xb504, 0x11, x1, 268, x2)
inst_83:
// rs1_val==1717986918,
// opcode: srai ; op1:x10; dest:x11; op1val:0x66666666; immval:0xe
TEST_IMM_OP( srai, x11, x10, 0x19999, 0x66666666, 0xe, x1, 272, x2)
inst_84:
// rs1_val==858993459,
// opcode: srai ; op1:x10; dest:x11; op1val:0x33333333; immval:0x12
TEST_IMM_OP( srai, x11, x10, 0xccc, 0x33333333, 0x12, x1, 276, x2)
inst_85:
// rs1_val < 0 and imm_val == (xlen-1), rs1_val == -536870913, rs1_val < 0 and imm_val > 0 and imm_val < xlen
// opcode: srai ; op1:x10; dest:x11; op1val:-0x20000001; immval:0x1f
TEST_IMM_OP( srai, x11, x10, -0x1, -0x20000001, 0x1f, x1, 280, x2)
inst_86:
// rs1_val == -16777217,
// opcode: srai ; op1:x10; dest:x11; op1val:-0x1000001; immval:0x12
TEST_IMM_OP( srai, x11, x10, -0x41, -0x1000001, 0x12, x1, 284, x2)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
signature_x1_0:
.fill 0*(XLEN/32),4,0xdeadbeef
signature_x1_1:
.fill 7*(XLEN/32),4,0xdeadbeef
signature_x3_0:
.fill 8*(XLEN/32),4,0xdeadbeef
signature_x1_2:
.fill 72*(XLEN/32),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

529
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-srl-01.S
View File

@ -1,529 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version : 0.5.1
// timestamp : Mon Aug 2 08:58:53 2021 GMT
// usage : riscv_ctg \
// --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/rv32e.cgf \
// --base-isa rv32e \
// --randomize
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the srl instruction of the RISC-V E extension for the srl covergroup.
//
#define RVTEST_E
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32E")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",srl)
RVTEST_SIGBASE( x1,signature_x1_1)
inst_0:
// rs1 != rs2 and rs1 != rd and rs2 != rd, rs1==x10, rs2==x4, rd==x7, rs1_val < 0 and rs2_val == 0, rs1_val == -9
// opcode: srl ; op1:x10; op2:x4; dest:x7; op1val:-0x9; op2val:0x0
TEST_RR_OP(srl, x7, x10, x4, 0xfffffff7, -0x9, 0x0, x1, 0, x6)
inst_1:
// rs1 == rd != rs2, rs1==x15, rs2==x0, rd==x15, rs2_val == 15, rs1_val < 0 and rs2_val > 0 and rs2_val < xlen
// opcode: srl ; op1:x15; op2:x0; dest:x15; op1val:-0x6; op2val:0x0
TEST_RR_OP(srl, x15, x15, x0, 0xfffffffa, -0x6, 0x0, x1, 4, x6)
inst_2:
// rs2 == rd != rs1, rs1==x2, rs2==x3, rd==x3, rs2_val == 23, rs1_val == -2049
// opcode: srl ; op1:x2; op2:x3; dest:x3; op1val:-0x801; op2val:0x17
TEST_RR_OP(srl, x3, x2, x3, 0x1ff, -0x801, 0x17, x1, 8, x6)
inst_3:
// rs1 == rs2 != rd, rs1==x5, rs2==x5, rd==x12, rs2_val == 27, rs1_val == -1048577
// opcode: srl ; op1:x5; op2:x5; dest:x12; op1val:-0x100001; op2val:-0x100001
TEST_RR_OP(srl, x12, x5, x5, 0x1, -0x100001, -0x100001, x1, 12, x6)
inst_4:
// rs1 == rs2 == rd, rs1==x14, rs2==x14, rd==x14, rs2_val == 29, rs1_val == -16777217
// opcode: srl ; op1:x14; op2:x14; dest:x14; op1val:-0x1000001; op2val:-0x1000001
TEST_RR_OP(srl, x14, x14, x14, 0x1, -0x1000001, -0x1000001, x1, 16, x6)
inst_5:
// rs1==x12, rs2==x10, rd==x2, rs2_val == 30, rs1_val == -1073741825
// opcode: srl ; op1:x12; op2:x10; dest:x2; op1val:-0x40000001; op2val:0x1e
TEST_RR_OP(srl, x2, x12, x10, 0x2, -0x40000001, 0x1e, x1, 20, x6)
inst_6:
// rs1==x11, rs2==x15, rd==x9, rs1_val == 2147483647, rs1_val > 0 and rs2_val > 0 and rs2_val < xlen, rs1_val == (2**(xlen-1)-1) and rs2_val >= 0 and rs2_val < xlen
// opcode: srl ; op1:x11; op2:x15; dest:x9; op1val:0x7fffffff; op2val:0x1b
TEST_RR_OP(srl, x9, x11, x15, 0xf, 0x7fffffff, 0x1b, x1, 24, x6)
inst_7:
// rs1==x4, rs2==x6, rd==x10, rs1_val == -536870913,
// opcode: srl ; op1:x4; op2:x6; dest:x10; op1val:-0x20000001; op2val:0x13
TEST_RR_OP(srl, x10, x4, x6, 0x1bff, -0x20000001, 0x13, x1, 28, x2)
RVTEST_SIGBASE( x10,signature_x10_0)
inst_8:
// rs1==x0, rs2==x9, rd==x8, rs1_val == -268435457,
// opcode: srl ; op1:x0; op2:x9; dest:x8; op1val:0x0; op2val:0xe
TEST_RR_OP(srl, x8, x0, x9, 0x0, 0x0, 0xe, x10, 0, x2)
inst_9:
// rs1==x1, rs2==x7, rd==x11, rs1_val == -134217729,
// opcode: srl ; op1:x1; op2:x7; dest:x11; op1val:-0x8000001; op2val:0x13
TEST_RR_OP(srl, x11, x1, x7, 0x1eff, -0x8000001, 0x13, x10, 4, x2)
inst_10:
// rs1==x7, rs2==x12, rd==x5, rs1_val == -67108865,
// opcode: srl ; op1:x7; op2:x12; dest:x5; op1val:-0x4000001; op2val:0x1b
TEST_RR_OP(srl, x5, x7, x12, 0x1f, -0x4000001, 0x1b, x10, 8, x2)
inst_11:
// rs1==x6, rs2==x13, rd==x1, rs1_val == -33554433,
// opcode: srl ; op1:x6; op2:x13; dest:x1; op1val:-0x2000001; op2val:0x6
TEST_RR_OP(srl, x1, x6, x13, 0x3f7ffff, -0x2000001, 0x6, x10, 12, x2)
inst_12:
// rs1==x9, rs2==x8, rd==x4, rs1_val == -8388609,
// opcode: srl ; op1:x9; op2:x8; dest:x4; op1val:-0x800001; op2val:0xe
TEST_RR_OP(srl, x4, x9, x8, 0x3fdff, -0x800001, 0xe, x10, 16, x2)
inst_13:
// rs1==x3, rs2==x11, rd==x6, rs1_val == -4194305, rs2_val == 8
// opcode: srl ; op1:x3; op2:x11; dest:x6; op1val:-0x400001; op2val:0x8
TEST_RR_OP(srl, x6, x3, x11, 0xffbfff, -0x400001, 0x8, x10, 20, x2)
inst_14:
// rs1==x13, rs2==x1, rd==x0, rs1_val == -2097153, rs2_val == 4
// opcode: srl ; op1:x13; op2:x1; dest:x0; op1val:-0x200001; op2val:0x4
TEST_RR_OP(srl, x0, x13, x1, 0, -0x200001, 0x4, x10, 24, x3)
inst_15:
// rs1==x8, rs2==x2, rd==x13, rs1_val == -524289,
// opcode: srl ; op1:x8; op2:x2; dest:x13; op1val:-0x80001; op2val:0x1d
TEST_RR_OP(srl, x13, x8, x2, 0x7, -0x80001, 0x1d, x10, 28, x3)
RVTEST_SIGBASE( x1,signature_x1_2)
inst_16:
// rs1_val == -262145,
// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:-0x40001; op2val:0x4
TEST_RR_OP(srl, x12, x10, x11, 0xfffbfff, -0x40001, 0x4, x1, 0, x3)
inst_17:
// rs1_val == -131073,
// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:-0x20001; op2val:0x8
TEST_RR_OP(srl, x12, x10, x11, 0xfffdff, -0x20001, 0x8, x1, 4, x3)
inst_18:
// rs1_val == -65537,
// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:-0x10001; op2val:0x1e
TEST_RR_OP(srl, x12, x10, x11, 0x3, -0x10001, 0x1e, x1, 8, x3)
inst_19:
// rs1_val == -32769,
// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:-0x8001; op2val:0x1d
TEST_RR_OP(srl, x12, x10, x11, 0x7, -0x8001, 0x1d, x1, 12, x3)
inst_20:
// rs1_val == -16385, rs2_val == 10
// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:-0x4001; op2val:0xa
TEST_RR_OP(srl, x12, x10, x11, 0x3fffef, -0x4001, 0xa, x1, 16, x3)
inst_21:
// rs1_val == -8193,
// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:-0x2001; op2val:0xe
TEST_RR_OP(srl, x12, x10, x11, 0x3ffff, -0x2001, 0xe, x1, 20, x3)
inst_22:
// rs1_val == -4097,
// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:-0x1001; op2val:0x1f
TEST_RR_OP(srl, x12, x10, x11, 0x1, -0x1001, 0x1f, x1, 24, x3)
inst_23:
// rs1_val == -1025,
// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:-0x401; op2val:0x1e
TEST_RR_OP(srl, x12, x10, x11, 0x3, -0x401, 0x1e, x1, 28, x3)
inst_24:
// rs1_val == -513,
// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:-0x201; op2val:0x11
TEST_RR_OP(srl, x12, x10, x11, 0x7fff, -0x201, 0x11, x1, 32, x3)
inst_25:
// rs1_val == -257,
// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:-0x101; op2val:0x1d
TEST_RR_OP(srl, x12, x10, x11, 0x7, -0x101, 0x1d, x1, 36, x3)
inst_26:
// rs1_val == -129,
// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:-0x81; op2val:0xd
TEST_RR_OP(srl, x12, x10, x11, 0x7ffff, -0x81, 0xd, x1, 40, x3)
inst_27:
// rs1_val == -65,
// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:-0x41; op2val:0x9
TEST_RR_OP(srl, x12, x10, x11, 0x7fffff, -0x41, 0x9, x1, 44, x3)
inst_28:
// rs1_val == -33, rs2_val == 21
// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:-0x21; op2val:0x15
TEST_RR_OP(srl, x12, x10, x11, 0x7ff, -0x21, 0x15, x1, 48, x3)
inst_29:
// rs1_val == -17,
// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:-0x11; op2val:0xe
TEST_RR_OP(srl, x12, x10, x11, 0x3ffff, -0x11, 0xe, x1, 52, x3)
inst_30:
// rs1_val == -5,
// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:-0x5; op2val:0x0
TEST_RR_OP(srl, x12, x10, x11, 0xfffffffb, -0x5, 0x0, x1, 56, x3)
inst_31:
// rs1_val == -3,
// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:-0x3; op2val:0x1f
TEST_RR_OP(srl, x12, x10, x11, 0x1, -0x3, 0x1f, x1, 60, x3)
inst_32:
// rs1_val == -2,
// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:-0x2; op2val:0x5
TEST_RR_OP(srl, x12, x10, x11, 0x7ffffff, -0x2, 0x5, x1, 64, x3)
inst_33:
// rs2_val == 16, rs1_val == 524288
// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0x80000; op2val:0x10
TEST_RR_OP(srl, x12, x10, x11, 0x8, 0x80000, 0x10, x1, 68, x3)
inst_34:
// rs2_val == 2, rs1_val==46341
// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0xb505; op2val:0x2
TEST_RR_OP(srl, x12, x10, x11, 0x2d41, 0xb505, 0x2, x1, 72, x3)
inst_35:
// rs2_val == 1, rs1_val == 268435456
// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0x10000000; op2val:0x1
TEST_RR_OP(srl, x12, x10, x11, 0x8000000, 0x10000000, 0x1, x1, 76, x3)
inst_36:
// rs1_val == -2147483648, rs1_val == (-2**(xlen-1)) and rs2_val >= 0 and rs2_val < xlen
// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:-0x80000000; op2val:0x17
TEST_RR_OP(srl, x12, x10, x11, 0x100, -0x80000000, 0x17, x1, 80, x3)
inst_37:
// rs1_val == 1073741824,
// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0x40000000; op2val:0x6
TEST_RR_OP(srl, x12, x10, x11, 0x1000000, 0x40000000, 0x6, x1, 84, x3)
inst_38:
// rs1_val == 536870912,
// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0x20000000; op2val:0xa
TEST_RR_OP(srl, x12, x10, x11, 0x80000, 0x20000000, 0xa, x1, 88, x3)
inst_39:
// rs1_val == 134217728,
// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0x8000000; op2val:0x11
TEST_RR_OP(srl, x12, x10, x11, 0x400, 0x8000000, 0x11, x1, 92, x3)
inst_40:
// rs1_val == 67108864,
// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0x4000000; op2val:0xe
TEST_RR_OP(srl, x12, x10, x11, 0x1000, 0x4000000, 0xe, x1, 96, x3)
inst_41:
// rs1_val == 33554432,
// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0x2000000; op2val:0x12
TEST_RR_OP(srl, x12, x10, x11, 0x80, 0x2000000, 0x12, x1, 100, x3)
inst_42:
// rs1_val == 16777216,
// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0x1000000; op2val:0xa
TEST_RR_OP(srl, x12, x10, x11, 0x4000, 0x1000000, 0xa, x1, 104, x3)
inst_43:
// rs1_val == 8388608,
// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0x800000; op2val:0x13
TEST_RR_OP(srl, x12, x10, x11, 0x10, 0x800000, 0x13, x1, 108, x3)
inst_44:
// rs1_val == 4194304,
// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0x400000; op2val:0xb
TEST_RR_OP(srl, x12, x10, x11, 0x800, 0x400000, 0xb, x1, 112, x3)
inst_45:
// rs1_val == 2097152,
// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0x200000; op2val:0x8
TEST_RR_OP(srl, x12, x10, x11, 0x2000, 0x200000, 0x8, x1, 116, x3)
inst_46:
// rs1_val == 1048576,
// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0x100000; op2val:0xe
TEST_RR_OP(srl, x12, x10, x11, 0x40, 0x100000, 0xe, x1, 120, x3)
inst_47:
// rs1_val == 262144,
// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0x40000; op2val:0x11
TEST_RR_OP(srl, x12, x10, x11, 0x2, 0x40000, 0x11, x1, 124, x3)
inst_48:
// rs1_val == 131072,
// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0x20000; op2val:0xe
TEST_RR_OP(srl, x12, x10, x11, 0x8, 0x20000, 0xe, x1, 128, x3)
inst_49:
// rs1_val == 65536,
// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0x10000; op2val:0x13
TEST_RR_OP(srl, x12, x10, x11, 0x0, 0x10000, 0x13, x1, 132, x3)
inst_50:
// rs1_val == 32768,
// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0x8000; op2val:0xf
TEST_RR_OP(srl, x12, x10, x11, 0x1, 0x8000, 0xf, x1, 136, x3)
inst_51:
// rs1_val == 16384,
// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0x4000; op2val:0xe
TEST_RR_OP(srl, x12, x10, x11, 0x1, 0x4000, 0xe, x1, 140, x3)
inst_52:
// rs1_val == 8192,
// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0x2000; op2val:0x8
TEST_RR_OP(srl, x12, x10, x11, 0x20, 0x2000, 0x8, x1, 144, x3)
inst_53:
// rs1_val == 4096,
// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0x1000; op2val:0x6
TEST_RR_OP(srl, x12, x10, x11, 0x40, 0x1000, 0x6, x1, 148, x3)
inst_54:
// rs1_val == 2048,
// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0x800; op2val:0x1b
TEST_RR_OP(srl, x12, x10, x11, 0x0, 0x800, 0x1b, x1, 152, x3)
inst_55:
// rs1_val == 1024,
// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0x400; op2val:0x13
TEST_RR_OP(srl, x12, x10, x11, 0x0, 0x400, 0x13, x1, 156, x3)
inst_56:
// rs1_val == 512,
// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0x200; op2val:0x3
TEST_RR_OP(srl, x12, x10, x11, 0x40, 0x200, 0x3, x1, 160, x3)
inst_57:
// rs1_val == 256,
// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0x100; op2val:0x1e
TEST_RR_OP(srl, x12, x10, x11, 0x0, 0x100, 0x1e, x1, 164, x3)
inst_58:
// rs1_val == 128,
// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0x80; op2val:0xa
TEST_RR_OP(srl, x12, x10, x11, 0x0, 0x80, 0xa, x1, 168, x3)
inst_59:
// rs1_val == 64,
// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0x40; op2val:0x4
TEST_RR_OP(srl, x12, x10, x11, 0x4, 0x40, 0x4, x1, 172, x3)
inst_60:
// rs1_val == 32,
// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0x20; op2val:0xd
TEST_RR_OP(srl, x12, x10, x11, 0x0, 0x20, 0xd, x1, 176, x3)
inst_61:
// rs1_val == 16,
// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0x10; op2val:0x11
TEST_RR_OP(srl, x12, x10, x11, 0x0, 0x10, 0x11, x1, 180, x3)
inst_62:
// rs1_val == 8,
// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0x8; op2val:0x12
TEST_RR_OP(srl, x12, x10, x11, 0x0, 0x8, 0x12, x1, 184, x3)
inst_63:
// rs1_val == 4, rs1_val==4
// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0x4; op2val:0x10
TEST_RR_OP(srl, x12, x10, x11, 0x0, 0x4, 0x10, x1, 188, x3)
inst_64:
// rs1_val == 2, rs1_val==2, rs1_val == rs2_val and rs2_val > 0 and rs2_val < xlen
// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0x2; op2val:0x2
TEST_RR_OP(srl, x12, x10, x11, 0x0, 0x2, 0x2, x1, 192, x3)
inst_65:
// rs1_val == 1, rs1_val == 1 and rs2_val >= 0 and rs2_val < xlen
// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0x1; op2val:0x1f
TEST_RR_OP(srl, x12, x10, x11, 0x0, 0x1, 0x1f, x1, 196, x3)
inst_66:
// rs1_val==-46339,
// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:-0xb503; op2val:0x6
TEST_RR_OP(srl, x12, x10, x11, 0x3fffd2b, -0xb503, 0x6, x1, 200, x3)
inst_67:
// rs1_val==1717986919,
// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0x66666667; op2val:0xe
TEST_RR_OP(srl, x12, x10, x11, 0x19999, 0x66666667, 0xe, x1, 204, x3)
inst_68:
// rs1_val==858993460,
// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0x33333334; op2val:0x9
TEST_RR_OP(srl, x12, x10, x11, 0x199999, 0x33333334, 0x9, x1, 208, x3)
inst_69:
// rs1_val==6,
// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0x6; op2val:0xd
TEST_RR_OP(srl, x12, x10, x11, 0x0, 0x6, 0xd, x1, 212, x3)
inst_70:
// rs1_val==-1431655765,
// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555; op2val:0xe
TEST_RR_OP(srl, x12, x10, x11, 0x2aaaa, -0x55555555, 0xe, x1, 216, x3)
inst_71:
// rs1_val==1431655766, rs1_val > 0 and rs2_val == 0
// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0x55555556; op2val:0x0
TEST_RR_OP(srl, x12, x10, x11, 0x55555556, 0x55555556, 0x0, x1, 220, x3)
inst_72:
// rs1_val==46339,
// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0xb503; op2val:0xd
TEST_RR_OP(srl, x12, x10, x11, 0x5, 0xb503, 0xd, x1, 224, x3)
inst_73:
// rs1_val==3,
// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0x3; op2val:0xf
TEST_RR_OP(srl, x12, x10, x11, 0x0, 0x3, 0xf, x1, 228, x3)
inst_74:
// rs1_val == -1431655766, rs1_val==-1431655766
// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556; op2val:0x4
TEST_RR_OP(srl, x12, x10, x11, 0xaaaaaaa, -0x55555556, 0x4, x1, 232, x3)
inst_75:
// rs1_val == 1431655765, rs1_val==1431655765
// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0x55555555; op2val:0x7
TEST_RR_OP(srl, x12, x10, x11, 0xaaaaaa, 0x55555555, 0x7, x1, 236, x3)
inst_76:
// rs1_val == 0 and rs2_val >= 0 and rs2_val < xlen, rs1_val==0
// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0x0; op2val:0x7
TEST_RR_OP(srl, x12, x10, x11, 0x0, 0x0, 0x7, x1, 240, x3)
inst_77:
// rs1_val==1717986917,
// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0x66666665; op2val:0x1b
TEST_RR_OP(srl, x12, x10, x11, 0xc, 0x66666665, 0x1b, x1, 244, x3)
inst_78:
// rs1_val==858993458,
// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0x33333332; op2val:0x11
TEST_RR_OP(srl, x12, x10, x11, 0x1999, 0x33333332, 0x11, x1, 248, x3)
inst_79:
// rs1_val==1431655764,
// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0x55555554; op2val:0x13
TEST_RR_OP(srl, x12, x10, x11, 0xaaa, 0x55555554, 0x13, x1, 252, x3)
inst_80:
// rs1_val==46340,
// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0xb504; op2val:0x12
TEST_RR_OP(srl, x12, x10, x11, 0x0, 0xb504, 0x12, x1, 256, x3)
inst_81:
// rs1_val==-46340,
// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:-0xb504; op2val:0x4
TEST_RR_OP(srl, x12, x10, x11, 0xffff4af, -0xb504, 0x4, x1, 260, x3)
inst_82:
// rs1_val==1717986918,
// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0x66666666; op2val:0x1b
TEST_RR_OP(srl, x12, x10, x11, 0xc, 0x66666666, 0x1b, x1, 264, x3)
inst_83:
// rs1_val==858993459,
// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0x33333333; op2val:0x15
TEST_RR_OP(srl, x12, x10, x11, 0x199, 0x33333333, 0x15, x1, 268, x3)
inst_84:
// rs1_val==5,
// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0x5; op2val:0x10
TEST_RR_OP(srl, x12, x10, x11, 0x0, 0x5, 0x10, x1, 272, x3)
inst_85:
// rs2_val == 27, rs1_val == -1048577
// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:-0x100001; op2val:0x1b
TEST_RR_OP(srl, x12, x10, x11, 0x1f, -0x100001, 0x1b, x1, 276, x3)
inst_86:
// rs2_val == 29, rs1_val == -16777217
// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:-0x1000001; op2val:0x1d
TEST_RR_OP(srl, x12, x10, x11, 0x7, -0x1000001, 0x1d, x1, 280, x3)
inst_87:
// rs1_val == -268435457,
// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:-0x10000001; op2val:0xe
TEST_RR_OP(srl, x12, x10, x11, 0x3bfff, -0x10000001, 0xe, x1, 284, x3)
inst_88:
// rs1_val == -2097153, rs2_val == 4
// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:-0x200001; op2val:0x4
TEST_RR_OP(srl, x12, x10, x11, 0xffdffff, -0x200001, 0x4, x1, 288, x3)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
signature_x1_0:
.fill 0*(XLEN/32),4,0xdeadbeef
signature_x1_1:
.fill 8*(XLEN/32),4,0xdeadbeef
signature_x10_0:
.fill 8*(XLEN/32),4,0xdeadbeef
signature_x1_2:
.fill 73*(XLEN/32),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

524
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-srli-01.S
View File

@ -1,524 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version : 0.5.1
// timestamp : Mon Aug 2 08:58:53 2021 GMT
// usage : riscv_ctg \
// --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/rv32e.cgf \
// --base-isa rv32e \
// --randomize
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the srli instruction of the RISC-V E extension for the srli covergroup.
//
#define RVTEST_E
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32E")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",srli)
RVTEST_SIGBASE( x1,signature_x1_1)
inst_0:
// rs1 != rd, rs1==x4, rd==x5, rs1_val < 0 and imm_val == (xlen-1), rs1_val == -65, rs1_val < 0 and imm_val > 0 and imm_val < xlen
// opcode: srli ; op1:x4; dest:x5; op1val:-0x41; immval:0x1f
TEST_IMM_OP( srli, x5, x4, 0x1, -0x41, 0x1f, x1, 0, x10)
inst_1:
// rs1 == rd, rs1==x9, rd==x9, rs1_val == 2147483647, rs1_val == (2**(xlen-1)-1) and imm_val >= 0 and imm_val < xlen, rs1_val > 0 and imm_val > 0 and imm_val < xlen, imm_val == 8
// opcode: srli ; op1:x9; dest:x9; op1val:0x7fffffff; immval:0x8
TEST_IMM_OP( srli, x9, x9, 0x7fffff, 0x7fffffff, 0x8, x1, 4, x10)
inst_2:
// rs1==x0, rd==x6, rs1_val == -1073741825, imm_val == 23
// opcode: srli ; op1:x0; dest:x6; op1val:0x0; immval:0x17
TEST_IMM_OP( srli, x6, x0, 0x0, 0x0, 0x17, x1, 8, x10)
inst_3:
// rs1==x12, rd==x4, rs1_val == -536870913,
// opcode: srli ; op1:x12; dest:x4; op1val:-0x20000001; immval:0x6
TEST_IMM_OP( srli, x4, x12, 0x37fffff, -0x20000001, 0x6, x1, 12, x10)
inst_4:
// rs1==x8, rd==x14, rs1_val == -268435457, imm_val == 10
// opcode: srli ; op1:x8; dest:x14; op1val:-0x10000001; immval:0xa
TEST_IMM_OP( srli, x14, x8, 0x3bffff, -0x10000001, 0xa, x1, 16, x10)
inst_5:
// rs1==x7, rd==x3, rs1_val == -134217729, imm_val == 2
// opcode: srli ; op1:x7; dest:x3; op1val:-0x8000001; immval:0x2
TEST_IMM_OP( srli, x3, x7, 0x3dffffff, -0x8000001, 0x2, x1, 20, x10)
inst_6:
// rs1==x6, rd==x2, rs1_val == -67108865,
// opcode: srli ; op1:x6; dest:x2; op1val:-0x4000001; immval:0x12
TEST_IMM_OP( srli, x2, x6, 0x3eff, -0x4000001, 0x12, x1, 24, x10)
inst_7:
// rs1==x11, rd==x15, rs1_val == -33554433, imm_val == 16
// opcode: srli ; op1:x11; dest:x15; op1val:-0x2000001; immval:0x10
TEST_IMM_OP( srli, x15, x11, 0xfdff, -0x2000001, 0x10, x1, 28, x10)
RVTEST_SIGBASE( x4,signature_x4_0)
inst_8:
// rs1==x5, rd==x13, rs1_val == -16777217, imm_val == 1
// opcode: srli ; op1:x5; dest:x13; op1val:-0x1000001; immval:0x1
TEST_IMM_OP( srli, x13, x5, 0x7f7fffff, -0x1000001, 0x1, x4, 0, x6)
inst_9:
// rs1==x15, rd==x11, rs1_val == -8388609,
// opcode: srli ; op1:x15; dest:x11; op1val:-0x800001; immval:0x11
TEST_IMM_OP( srli, x11, x15, 0x7fbf, -0x800001, 0x11, x4, 4, x6)
inst_10:
// rs1==x2, rd==x12, rs1_val == -4194305, imm_val == 15
// opcode: srli ; op1:x2; dest:x12; op1val:-0x400001; immval:0xf
TEST_IMM_OP( srli, x12, x2, 0x1ff7f, -0x400001, 0xf, x4, 8, x6)
inst_11:
// rs1==x14, rd==x7, rs1_val == -2097153,
// opcode: srli ; op1:x14; dest:x7; op1val:-0x200001; immval:0x7
TEST_IMM_OP( srli, x7, x14, 0x1ffbfff, -0x200001, 0x7, x4, 12, x6)
inst_12:
// rs1==x13, rd==x0, rs1_val == -1048577,
// opcode: srli ; op1:x13; dest:x0; op1val:-0x100001; immval:0xc
TEST_IMM_OP( srli, x0, x13, 0, -0x100001, 0xc, x4, 16, x6)
inst_13:
// rs1==x3, rd==x10, rs1_val == -524289, imm_val == 21
// opcode: srli ; op1:x3; dest:x10; op1val:-0x80001; immval:0x15
TEST_IMM_OP( srli, x10, x3, 0x7ff, -0x80001, 0x15, x4, 20, x6)
inst_14:
// rs1==x10, rd==x1, rs1_val == -262145,
// opcode: srli ; op1:x10; dest:x1; op1val:-0x40001; immval:0x10
TEST_IMM_OP( srli, x1, x10, 0xfffb, -0x40001, 0x10, x4, 24, x6)
inst_15:
// rs1==x1, rd==x8, rs1_val == -131073,
// opcode: srli ; op1:x1; dest:x8; op1val:-0x20001; immval:0x11
TEST_IMM_OP( srli, x8, x1, 0x7ffe, -0x20001, 0x11, x4, 28, x2)
RVTEST_SIGBASE( x1,signature_x1_2)
inst_16:
// rs1_val == -65537,
// opcode: srli ; op1:x10; dest:x11; op1val:-0x10001; immval:0xb
TEST_IMM_OP( srli, x11, x10, 0x1fffdf, -0x10001, 0xb, x1, 0, x2)
inst_17:
// rs1_val == -32769,
// opcode: srli ; op1:x10; dest:x11; op1val:-0x8001; immval:0x12
TEST_IMM_OP( srli, x11, x10, 0x3fff, -0x8001, 0x12, x1, 4, x2)
inst_18:
// rs1_val == -16385, rs1_val < 0 and imm_val == 0
// opcode: srli ; op1:x10; dest:x11; op1val:-0x4001; immval:0x0
TEST_IMM_OP( srli, x11, x10, 0xffffbfff, -0x4001, 0x0, x1, 8, x2)
inst_19:
// rs1_val == -8193,
// opcode: srli ; op1:x10; dest:x11; op1val:-0x2001; immval:0x13
TEST_IMM_OP( srli, x11, x10, 0x1fff, -0x2001, 0x13, x1, 12, x2)
inst_20:
// rs1_val == -4097,
// opcode: srli ; op1:x10; dest:x11; op1val:-0x1001; immval:0xa
TEST_IMM_OP( srli, x11, x10, 0x3ffffb, -0x1001, 0xa, x1, 16, x2)
inst_21:
// rs1_val == -2049,
// opcode: srli ; op1:x10; dest:x11; op1val:-0x801; immval:0x15
TEST_IMM_OP( srli, x11, x10, 0x7ff, -0x801, 0x15, x1, 20, x2)
inst_22:
// rs1_val == -1025,
// opcode: srli ; op1:x10; dest:x11; op1val:-0x401; immval:0x6
TEST_IMM_OP( srli, x11, x10, 0x3ffffef, -0x401, 0x6, x1, 24, x2)
inst_23:
// rs1_val == -513,
// opcode: srli ; op1:x10; dest:x11; op1val:-0x201; immval:0x13
TEST_IMM_OP( srli, x11, x10, 0x1fff, -0x201, 0x13, x1, 28, x2)
inst_24:
// rs1_val == -257,
// opcode: srli ; op1:x10; dest:x11; op1val:-0x101; immval:0x8
TEST_IMM_OP( srli, x11, x10, 0xfffffe, -0x101, 0x8, x1, 32, x2)
inst_25:
// rs1_val == -129,
// opcode: srli ; op1:x10; dest:x11; op1val:-0x81; immval:0x8
TEST_IMM_OP( srli, x11, x10, 0xffffff, -0x81, 0x8, x1, 36, x2)
inst_26:
// rs1_val == -33,
// opcode: srli ; op1:x10; dest:x11; op1val:-0x21; immval:0x2
TEST_IMM_OP( srli, x11, x10, 0x3ffffff7, -0x21, 0x2, x1, 40, x2)
inst_27:
// rs1_val == -17,
// opcode: srli ; op1:x10; dest:x11; op1val:-0x11; immval:0x12
TEST_IMM_OP( srli, x11, x10, 0x3fff, -0x11, 0x12, x1, 44, x2)
inst_28:
// rs1_val == -9,
// opcode: srli ; op1:x10; dest:x11; op1val:-0x9; immval:0x2
TEST_IMM_OP( srli, x11, x10, 0x3ffffffd, -0x9, 0x2, x1, 48, x2)
inst_29:
// rs1_val == -5,
// opcode: srli ; op1:x10; dest:x11; op1val:-0x5; immval:0x6
TEST_IMM_OP( srli, x11, x10, 0x3ffffff, -0x5, 0x6, x1, 52, x2)
inst_30:
// rs1_val == -3,
// opcode: srli ; op1:x10; dest:x11; op1val:-0x3; immval:0xf
TEST_IMM_OP( srli, x11, x10, 0x1ffff, -0x3, 0xf, x1, 56, x2)
inst_31:
// rs1_val == -2,
// opcode: srli ; op1:x10; dest:x11; op1val:-0x2; immval:0xc
TEST_IMM_OP( srli, x11, x10, 0xfffff, -0x2, 0xc, x1, 60, x2)
inst_32:
// imm_val == 27, rs1_val == 262144
// opcode: srli ; op1:x10; dest:x11; op1val:0x40000; immval:0x1b
TEST_IMM_OP( srli, x11, x10, 0x0, 0x40000, 0x1b, x1, 64, x2)
inst_33:
// imm_val == 29,
// opcode: srli ; op1:x10; dest:x11; op1val:-0x40000000; immval:0x1d
TEST_IMM_OP( srli, x11, x10, 0x6, -0x40000000, 0x1d, x1, 68, x2)
inst_34:
// imm_val == 30, rs1_val == 64
// opcode: srli ; op1:x10; dest:x11; op1val:0x40; immval:0x1e
TEST_IMM_OP( srli, x11, x10, 0x0, 0x40, 0x1e, x1, 72, x2)
inst_35:
// rs1_val == -2147483648, rs1_val == (-2**(xlen-1)) and imm_val >= 0 and imm_val < xlen
// opcode: srli ; op1:x10; dest:x11; op1val:-0x80000000; immval:0xa
TEST_IMM_OP( srli, x11, x10, 0x200000, -0x80000000, 0xa, x1, 76, x2)
inst_36:
// rs1_val == 1073741824, rs1_val > 0 and imm_val == 0
// opcode: srli ; op1:x10; dest:x11; op1val:0x40000000; immval:0x0
TEST_IMM_OP( srli, x11, x10, 0x40000000, 0x40000000, 0x0, x1, 80, x2)
inst_37:
// rs1_val == 536870912,
// opcode: srli ; op1:x10; dest:x11; op1val:0x20000000; immval:0x11
TEST_IMM_OP( srli, x11, x10, 0x1000, 0x20000000, 0x11, x1, 84, x2)
inst_38:
// rs1_val == 268435456,
// opcode: srli ; op1:x10; dest:x11; op1val:0x10000000; immval:0x11
TEST_IMM_OP( srli, x11, x10, 0x800, 0x10000000, 0x11, x1, 88, x2)
inst_39:
// rs1_val == 134217728,
// opcode: srli ; op1:x10; dest:x11; op1val:0x8000000; immval:0xb
TEST_IMM_OP( srli, x11, x10, 0x10000, 0x8000000, 0xb, x1, 92, x2)
inst_40:
// rs1_val == 67108864,
// opcode: srli ; op1:x10; dest:x11; op1val:0x4000000; immval:0x1e
TEST_IMM_OP( srli, x11, x10, 0x0, 0x4000000, 0x1e, x1, 96, x2)
inst_41:
// rs1_val == 33554432,
// opcode: srli ; op1:x10; dest:x11; op1val:0x2000000; immval:0x13
TEST_IMM_OP( srli, x11, x10, 0x40, 0x2000000, 0x13, x1, 100, x2)
inst_42:
// rs1_val == 16777216,
// opcode: srli ; op1:x10; dest:x11; op1val:0x1000000; immval:0xd
TEST_IMM_OP( srli, x11, x10, 0x800, 0x1000000, 0xd, x1, 104, x2)
inst_43:
// rs1_val == 8388608,
// opcode: srli ; op1:x10; dest:x11; op1val:0x800000; immval:0x7
TEST_IMM_OP( srli, x11, x10, 0x10000, 0x800000, 0x7, x1, 108, x2)
inst_44:
// rs1_val == 4194304,
// opcode: srli ; op1:x10; dest:x11; op1val:0x400000; immval:0x6
TEST_IMM_OP( srli, x11, x10, 0x10000, 0x400000, 0x6, x1, 112, x2)
inst_45:
// rs1_val == 2097152, imm_val == 4
// opcode: srli ; op1:x10; dest:x11; op1val:0x200000; immval:0x4
TEST_IMM_OP( srli, x11, x10, 0x20000, 0x200000, 0x4, x1, 116, x2)
inst_46:
// rs1_val == 1048576,
// opcode: srli ; op1:x10; dest:x11; op1val:0x100000; immval:0x9
TEST_IMM_OP( srli, x11, x10, 0x800, 0x100000, 0x9, x1, 120, x2)
inst_47:
// rs1_val == 524288,
// opcode: srli ; op1:x10; dest:x11; op1val:0x80000; immval:0xb
TEST_IMM_OP( srli, x11, x10, 0x100, 0x80000, 0xb, x1, 124, x2)
inst_48:
// rs1_val == 131072,
// opcode: srli ; op1:x10; dest:x11; op1val:0x20000; immval:0x10
TEST_IMM_OP( srli, x11, x10, 0x2, 0x20000, 0x10, x1, 128, x2)
inst_49:
// rs1_val == 65536,
// opcode: srli ; op1:x10; dest:x11; op1val:0x10000; immval:0x0
TEST_IMM_OP( srli, x11, x10, 0x10000, 0x10000, 0x0, x1, 132, x2)
inst_50:
// rs1_val == 32768,
// opcode: srli ; op1:x10; dest:x11; op1val:0x8000; immval:0x10
TEST_IMM_OP( srli, x11, x10, 0x0, 0x8000, 0x10, x1, 136, x2)
inst_51:
// rs1_val == 16384,
// opcode: srli ; op1:x10; dest:x11; op1val:0x4000; immval:0x6
TEST_IMM_OP( srli, x11, x10, 0x100, 0x4000, 0x6, x1, 140, x2)
inst_52:
// rs1_val == 8192,
// opcode: srli ; op1:x10; dest:x11; op1val:0x2000; immval:0x4
TEST_IMM_OP( srli, x11, x10, 0x200, 0x2000, 0x4, x1, 144, x2)
inst_53:
// rs1_val == 4096,
// opcode: srli ; op1:x10; dest:x11; op1val:0x1000; immval:0xf
TEST_IMM_OP( srli, x11, x10, 0x0, 0x1000, 0xf, x1, 148, x2)
inst_54:
// rs1_val == 2048,
// opcode: srli ; op1:x10; dest:x11; op1val:0x800; immval:0x8
TEST_IMM_OP( srli, x11, x10, 0x8, 0x800, 0x8, x1, 152, x2)
inst_55:
// rs1_val == 1024,
// opcode: srli ; op1:x10; dest:x11; op1val:0x400; immval:0x12
TEST_IMM_OP( srli, x11, x10, 0x0, 0x400, 0x12, x1, 156, x2)
inst_56:
// rs1_val == 512,
// opcode: srli ; op1:x10; dest:x11; op1val:0x200; immval:0xe
TEST_IMM_OP( srli, x11, x10, 0x0, 0x200, 0xe, x1, 160, x2)
inst_57:
// rs1_val == 256,
// opcode: srli ; op1:x10; dest:x11; op1val:0x100; immval:0x13
TEST_IMM_OP( srli, x11, x10, 0x0, 0x100, 0x13, x1, 164, x2)
inst_58:
// rs1_val == 128,
// opcode: srli ; op1:x10; dest:x11; op1val:0x80; immval:0x8
TEST_IMM_OP( srli, x11, x10, 0x0, 0x80, 0x8, x1, 168, x2)
inst_59:
// rs1_val == 32,
// opcode: srli ; op1:x10; dest:x11; op1val:0x20; immval:0xb
TEST_IMM_OP( srli, x11, x10, 0x0, 0x20, 0xb, x1, 172, x2)
inst_60:
// rs1_val == 16,
// opcode: srli ; op1:x10; dest:x11; op1val:0x10; immval:0x17
TEST_IMM_OP( srli, x11, x10, 0x0, 0x10, 0x17, x1, 176, x2)
inst_61:
// rs1_val == 8,
// opcode: srli ; op1:x10; dest:x11; op1val:0x8; immval:0x1d
TEST_IMM_OP( srli, x11, x10, 0x0, 0x8, 0x1d, x1, 180, x2)
inst_62:
// rs1_val == 4, rs1_val==4
// opcode: srli ; op1:x10; dest:x11; op1val:0x4; immval:0x9
TEST_IMM_OP( srli, x11, x10, 0x0, 0x4, 0x9, x1, 184, x2)
inst_63:
// rs1_val == 2, rs1_val==2
// opcode: srli ; op1:x10; dest:x11; op1val:0x2; immval:0x11
TEST_IMM_OP( srli, x11, x10, 0x0, 0x2, 0x11, x1, 188, x2)
inst_64:
// rs1_val == 1, rs1_val == 1 and imm_val >= 0 and imm_val < xlen, rs1_val > 0 and imm_val == (xlen-1)
// opcode: srli ; op1:x10; dest:x11; op1val:0x1; immval:0x1f
TEST_IMM_OP( srli, x11, x10, 0x0, 0x1, 0x1f, x1, 192, x2)
inst_65:
// rs1_val==46341,
// opcode: srli ; op1:x10; dest:x11; op1val:0xb505; immval:0xd
TEST_IMM_OP( srli, x11, x10, 0x5, 0xb505, 0xd, x1, 196, x2)
inst_66:
// rs1_val==-46339,
// opcode: srli ; op1:x10; dest:x11; op1val:-0xb503; immval:0x7
TEST_IMM_OP( srli, x11, x10, 0x1fffe95, -0xb503, 0x7, x1, 200, x2)
inst_67:
// rs1_val==1717986919,
// opcode: srli ; op1:x10; dest:x11; op1val:0x66666667; immval:0xb
TEST_IMM_OP( srli, x11, x10, 0xccccc, 0x66666667, 0xb, x1, 204, x2)
inst_68:
// rs1_val==858993460,
// opcode: srli ; op1:x10; dest:x11; op1val:0x33333334; immval:0xe
TEST_IMM_OP( srli, x11, x10, 0xcccc, 0x33333334, 0xe, x1, 208, x2)
inst_69:
// rs1_val==6,
// opcode: srli ; op1:x10; dest:x11; op1val:0x6; immval:0xe
TEST_IMM_OP( srli, x11, x10, 0x0, 0x6, 0xe, x1, 212, x2)
inst_70:
// rs1_val==-1431655765,
// opcode: srli ; op1:x10; dest:x11; op1val:-0x55555555; immval:0x1
TEST_IMM_OP( srli, x11, x10, 0x55555555, -0x55555555, 0x1, x1, 216, x2)
inst_71:
// rs1_val==1431655766,
// opcode: srli ; op1:x10; dest:x11; op1val:0x55555556; immval:0x10
TEST_IMM_OP( srli, x11, x10, 0x5555, 0x55555556, 0x10, x1, 220, x2)
inst_72:
// rs1_val==46339,
// opcode: srli ; op1:x10; dest:x11; op1val:0xb503; immval:0x15
TEST_IMM_OP( srli, x11, x10, 0x0, 0xb503, 0x15, x1, 224, x2)
inst_73:
// rs1_val==0, rs1_val == 0 and imm_val >= 0 and imm_val < xlen
// opcode: srli ; op1:x10; dest:x11; op1val:0x0; immval:0x17
TEST_IMM_OP( srli, x11, x10, 0x0, 0x0, 0x17, x1, 228, x2)
inst_74:
// rs1_val==3,
// opcode: srli ; op1:x10; dest:x11; op1val:0x3; immval:0x8
TEST_IMM_OP( srli, x11, x10, 0x0, 0x3, 0x8, x1, 232, x2)
inst_75:
// rs1_val == -1431655766, rs1_val==-1431655766
// opcode: srli ; op1:x10; dest:x11; op1val:-0x55555556; immval:0x2
TEST_IMM_OP( srli, x11, x10, 0x2aaaaaaa, -0x55555556, 0x2, x1, 236, x2)
inst_76:
// rs1_val == 1431655765, rs1_val==1431655765
// opcode: srli ; op1:x10; dest:x11; op1val:0x55555555; immval:0xb
TEST_IMM_OP( srli, x11, x10, 0xaaaaa, 0x55555555, 0xb, x1, 240, x2)
inst_77:
// rs1_val == imm_val and imm_val > 0 and imm_val < xlen,
// opcode: srli ; op1:x10; dest:x11; op1val:0x4; immval:0x4
TEST_IMM_OP( srli, x11, x10, 0x0, 0x4, 0x4, x1, 244, x2)
inst_78:
// rs1_val==1717986917,
// opcode: srli ; op1:x10; dest:x11; op1val:0x66666665; immval:0x15
TEST_IMM_OP( srli, x11, x10, 0x333, 0x66666665, 0x15, x1, 248, x2)
inst_79:
// rs1_val==858993458,
// opcode: srli ; op1:x10; dest:x11; op1val:0x33333332; immval:0x6
TEST_IMM_OP( srli, x11, x10, 0xcccccc, 0x33333332, 0x6, x1, 252, x2)
inst_80:
// rs1_val==1431655764,
// opcode: srli ; op1:x10; dest:x11; op1val:0x55555554; immval:0x6
TEST_IMM_OP( srli, x11, x10, 0x1555555, 0x55555554, 0x6, x1, 256, x2)
inst_81:
// rs1_val==46340,
// opcode: srli ; op1:x10; dest:x11; op1val:0xb504; immval:0x17
TEST_IMM_OP( srli, x11, x10, 0x0, 0xb504, 0x17, x1, 260, x2)
inst_82:
// rs1_val==-46340,
// opcode: srli ; op1:x10; dest:x11; op1val:-0xb504; immval:0x8
TEST_IMM_OP( srli, x11, x10, 0xffff4a, -0xb504, 0x8, x1, 264, x2)
inst_83:
// rs1_val==1717986918,
// opcode: srli ; op1:x10; dest:x11; op1val:0x66666666; immval:0x9
TEST_IMM_OP( srli, x11, x10, 0x333333, 0x66666666, 0x9, x1, 268, x2)
inst_84:
// rs1_val==858993459,
// opcode: srli ; op1:x10; dest:x11; op1val:0x33333333; immval:0x1e
TEST_IMM_OP( srli, x11, x10, 0x0, 0x33333333, 0x1e, x1, 272, x2)
inst_85:
// rs1_val==5,
// opcode: srli ; op1:x10; dest:x11; op1val:0x5; immval:0xb
TEST_IMM_OP( srli, x11, x10, 0x0, 0x5, 0xb, x1, 276, x2)
inst_86:
// rs1_val == -1073741825, imm_val == 23
// opcode: srli ; op1:x10; dest:x11; op1val:-0x40000001; immval:0x17
TEST_IMM_OP( srli, x11, x10, 0x17f, -0x40000001, 0x17, x1, 280, x2)
inst_87:
// rs1_val == -1048577,
// opcode: srli ; op1:x10; dest:x11; op1val:-0x100001; immval:0xc
TEST_IMM_OP( srli, x11, x10, 0xffeff, -0x100001, 0xc, x1, 284, x2)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
signature_x1_0:
.fill 0*(XLEN/32),4,0xdeadbeef
signature_x1_1:
.fill 8*(XLEN/32),4,0xdeadbeef
signature_x4_0:
.fill 8*(XLEN/32),4,0xdeadbeef
signature_x1_2:
.fill 72*(XLEN/32),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3009
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sub-01.S
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tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sw-align-01.S
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@ -1,419 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version : 0.5.1
// timestamp : Mon Aug 2 08:58:53 2021 GMT
// usage : riscv_ctg \
// --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/rv32e.cgf \
// --base-isa rv32e \
// --randomize
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the sw instruction of the RISC-V E extension for the sw-align covergroup.
//
#define RVTEST_E
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32E")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",sw-align)
RVTEST_SIGBASE( x2,signature_x2_1)
inst_0:
// rs1 != rs2, rs1==x13, rs2==x1, ea_align == 0 and (imm_val % 4) == 0, imm_val > 0, rs2_val == 67108864
// opcode: sw; op1:x13; op2:x1; op2val:0x4000000; immval:0x4; align:0
TEST_STORE(x2,x9,0,x13,x1,0x4000000,0x4,0,sw,0)
inst_1:
// rs1==x7, rs2==x6, rs2_val == 2147483647, rs2_val == (2**(xlen-1)-1)
// opcode: sw; op1:x7; op2:x6; op2val:0x7fffffff; immval:0x20; align:0
TEST_STORE(x2,x9,0,x7,x6,0x7fffffff,0x20,4,sw,0)
inst_2:
// rs1==x5, rs2==x0, rs2_val == -1073741825, imm_val < 0
// opcode: sw; op1:x5; op2:x0; op2val:0x0; immval:-0x4; align:0
TEST_STORE(x2,x9,0,x5,x0,0x0,-0x4,8,sw,0)
inst_3:
// rs1==x4, rs2==x5, rs2_val == -536870913, ea_align == 0 and (imm_val % 4) == 3
// opcode: sw; op1:x4; op2:x5; op2val:-0x20000001; immval:-0x11; align:0
TEST_STORE(x2,x9,0,x4,x5,-0x20000001,-0x11,12,sw,0)
inst_4:
// rs1==x12, rs2==x3, rs2_val == -268435457,
// opcode: sw; op1:x12; op2:x3; op2val:-0x10000001; immval:-0x101; align:0
TEST_STORE(x2,x9,0,x12,x3,-0x10000001,-0x101,16,sw,0)
inst_5:
// rs1==x8, rs2==x10, rs2_val == -134217729,
// opcode: sw; op1:x8; op2:x10; op2val:-0x8000001; immval:-0x1; align:0
TEST_STORE(x2,x9,0,x8,x10,-0x8000001,-0x1,20,sw,0)
inst_6:
// rs1==x1, rs2==x8, rs2_val == -67108865,
// opcode: sw; op1:x1; op2:x8; op2val:-0x4000001; immval:-0x401; align:0
TEST_STORE(x2,x9,0,x1,x8,-0x4000001,-0x401,24,sw,0)
inst_7:
// rs1==x6, rs2==x15, rs2_val == -33554433,
// opcode: sw; op1:x6; op2:x15; op2val:-0x2000001; immval:0x40; align:0
TEST_STORE(x2,x9,0,x6,x15,-0x2000001,0x40,28,sw,0)
inst_8:
// rs1==x11, rs2==x14, rs2_val == -16777217, ea_align == 0 and (imm_val % 4) == 1
// opcode: sw; op1:x11; op2:x14; op2val:-0x1000001; immval:0x555; align:0
TEST_STORE(x2,x5,0,x11,x14,-0x1000001,0x555,32,sw,0)
RVTEST_SIGBASE( x1,signature_x1_0)
inst_9:
// rs1==x15, rs2==x7, rs2_val == -8388609,
// opcode: sw; op1:x15; op2:x7; op2val:-0x800001; immval:-0x201; align:0
TEST_STORE(x1,x5,0,x15,x7,-0x800001,-0x201,0,sw,0)
inst_10:
// rs1==x3, rs2==x12, rs2_val == -4194305,
// opcode: sw; op1:x3; op2:x12; op2val:-0x400001; immval:-0x8; align:0
TEST_STORE(x1,x5,0,x3,x12,-0x400001,-0x8,4,sw,0)
inst_11:
// rs1==x14, rs2==x9, rs2_val == -2097153,
// opcode: sw; op1:x14; op2:x9; op2val:-0x200001; immval:-0x800; align:0
TEST_STORE(x1,x5,0,x14,x9,-0x200001,-0x800,8,sw,0)
inst_12:
// rs1==x9, rs2==x13, rs2_val == -1048577,
// opcode: sw; op1:x9; op2:x13; op2val:-0x100001; immval:0x9; align:0
TEST_STORE(x1,x5,0,x9,x13,-0x100001,0x9,12,sw,0)
inst_13:
// rs1==x10, rs2==x4, rs2_val == -524289,
// opcode: sw; op1:x10; op2:x4; op2val:-0x80001; immval:0x7; align:0
TEST_STORE(x1,x5,0,x10,x4,-0x80001,0x7,16,sw,0)
inst_14:
// rs1==x2, rs2==x11, rs2_val == -262145, ea_align == 0 and (imm_val % 4) == 2
// opcode: sw; op1:x2; op2:x11; op2val:-0x40001; immval:0x6; align:0
TEST_STORE(x1,x3,0,x2,x11,-0x40001,0x6,20,sw,0)
inst_15:
// rs2==x2, rs2_val == -131073,
// opcode: sw; op1:x9; op2:x2; op2val:-0x20001; immval:0x20; align:0
TEST_STORE(x1,x3,0,x9,x2,-0x20001,0x20,24,sw,0)
inst_16:
// rs2_val == -65537,
// opcode: sw; op1:x10; op2:x11; op2val:-0x10001; immval:-0x81; align:0
TEST_STORE(x1,x3,0,x10,x11,-0x10001,-0x81,28,sw,0)
inst_17:
// rs2_val == -32769,
// opcode: sw; op1:x10; op2:x11; op2val:-0x8001; immval:-0x11; align:0
TEST_STORE(x1,x3,0,x10,x11,-0x8001,-0x11,32,sw,0)
inst_18:
// rs2_val == -16385, imm_val == 0
// opcode: sw; op1:x10; op2:x11; op2val:-0x4001; immval:0x0; align:0
TEST_STORE(x1,x3,0,x10,x11,-0x4001,0x0,36,sw,0)
inst_19:
// rs2_val == -8193,
// opcode: sw; op1:x10; op2:x11; op2val:-0x2001; immval:0x3ff; align:0
TEST_STORE(x1,x3,0,x10,x11,-0x2001,0x3ff,40,sw,0)
inst_20:
// rs2_val == -4097,
// opcode: sw; op1:x10; op2:x11; op2val:-0x1001; immval:0x200; align:0
TEST_STORE(x1,x3,0,x10,x11,-0x1001,0x200,44,sw,0)
inst_21:
// rs2_val == -2049,
// opcode: sw; op1:x10; op2:x11; op2val:-0x801; immval:0x4; align:0
TEST_STORE(x1,x3,0,x10,x11,-0x801,0x4,48,sw,0)
inst_22:
// rs2_val == -1025,
// opcode: sw; op1:x10; op2:x11; op2val:-0x401; immval:-0x401; align:0
TEST_STORE(x1,x3,0,x10,x11,-0x401,-0x401,52,sw,0)
inst_23:
// rs2_val == -513,
// opcode: sw; op1:x10; op2:x11; op2val:-0x201; immval:0x3ff; align:0
TEST_STORE(x1,x3,0,x10,x11,-0x201,0x3ff,56,sw,0)
inst_24:
// rs2_val == -257,
// opcode: sw; op1:x10; op2:x11; op2val:-0x101; immval:-0x81; align:0
TEST_STORE(x1,x3,0,x10,x11,-0x101,-0x81,60,sw,0)
inst_25:
// rs2_val == -129,
// opcode: sw; op1:x10; op2:x11; op2val:-0x81; immval:0x1; align:0
TEST_STORE(x1,x3,0,x10,x11,-0x81,0x1,64,sw,0)
inst_26:
// rs2_val == -65,
// opcode: sw; op1:x10; op2:x11; op2val:-0x41; immval:-0xa; align:0
TEST_STORE(x1,x3,0,x10,x11,-0x41,-0xa,68,sw,0)
inst_27:
// rs2_val == -33,
// opcode: sw; op1:x10; op2:x11; op2val:-0x21; immval:0x3; align:0
TEST_STORE(x1,x3,0,x10,x11,-0x21,0x3,72,sw,0)
inst_28:
// rs2_val == -17,
// opcode: sw; op1:x10; op2:x11; op2val:-0x11; immval:0x2; align:0
TEST_STORE(x1,x3,0,x10,x11,-0x11,0x2,76,sw,0)
inst_29:
// rs2_val == -9,
// opcode: sw; op1:x10; op2:x11; op2val:-0x9; immval:-0xa; align:0
TEST_STORE(x1,x3,0,x10,x11,-0x9,-0xa,80,sw,0)
inst_30:
// rs2_val == -5,
// opcode: sw; op1:x10; op2:x11; op2val:-0x5; immval:0x40; align:0
TEST_STORE(x1,x3,0,x10,x11,-0x5,0x40,84,sw,0)
inst_31:
// rs2_val == -3,
// opcode: sw; op1:x10; op2:x11; op2val:-0x3; immval:0x1; align:0
TEST_STORE(x1,x3,0,x10,x11,-0x3,0x1,88,sw,0)
inst_32:
// rs2_val == -2,
// opcode: sw; op1:x10; op2:x11; op2val:-0x2; immval:-0x201; align:0
TEST_STORE(x1,x3,0,x10,x11,-0x2,-0x201,92,sw,0)
inst_33:
// rs2_val == -2147483648, rs2_val == (-2**(xlen-1))
// opcode: sw; op1:x10; op2:x11; op2val:-0x80000000; immval:0x20; align:0
TEST_STORE(x1,x3,0,x10,x11,-0x80000000,0x20,96,sw,0)
inst_34:
// rs2_val == 1073741824,
// opcode: sw; op1:x10; op2:x11; op2val:0x40000000; immval:-0x401; align:0
TEST_STORE(x1,x3,0,x10,x11,0x40000000,-0x401,100,sw,0)
inst_35:
// rs2_val == 536870912,
// opcode: sw; op1:x10; op2:x11; op2val:0x20000000; immval:-0x8; align:0
TEST_STORE(x1,x3,0,x10,x11,0x20000000,-0x8,104,sw,0)
inst_36:
// rs2_val == 1,
// opcode: sw; op1:x10; op2:x11; op2val:0x1; immval:-0x2; align:0
TEST_STORE(x1,x3,0,x10,x11,0x1,-0x2,108,sw,0)
inst_37:
// rs2_val == -1431655766,
// opcode: sw; op1:x10; op2:x11; op2val:-0x55555556; immval:-0x556; align:0
TEST_STORE(x1,x3,0,x10,x11,-0x55555556,-0x556,112,sw,0)
inst_38:
// rs2_val == 1431655765,
// opcode: sw; op1:x10; op2:x11; op2val:0x55555555; immval:0x40; align:0
TEST_STORE(x1,x3,0,x10,x11,0x55555555,0x40,116,sw,0)
inst_39:
// rs2_val == 0,
// opcode: sw; op1:x10; op2:x11; op2val:0x0; immval:-0xa; align:0
TEST_STORE(x1,x3,0,x10,x11,0x0,-0xa,120,sw,0)
inst_40:
// rs2_val == 268435456,
// opcode: sw; op1:x10; op2:x11; op2val:0x10000000; immval:-0x4; align:0
TEST_STORE(x1,x3,0,x10,x11,0x10000000,-0x4,124,sw,0)
inst_41:
// rs2_val == 134217728,
// opcode: sw; op1:x10; op2:x11; op2val:0x8000000; immval:0x7ff; align:0
TEST_STORE(x1,x3,0,x10,x11,0x8000000,0x7ff,128,sw,0)
inst_42:
// rs2_val == 33554432,
// opcode: sw; op1:x10; op2:x11; op2val:0x2000000; immval:0x555; align:0
TEST_STORE(x1,x3,0,x10,x11,0x2000000,0x555,132,sw,0)
inst_43:
// rs2_val == 16777216,
// opcode: sw; op1:x10; op2:x11; op2val:0x1000000; immval:0x1; align:0
TEST_STORE(x1,x3,0,x10,x11,0x1000000,0x1,136,sw,0)
inst_44:
// rs2_val == 8388608,
// opcode: sw; op1:x10; op2:x11; op2val:0x800000; immval:-0x5; align:0
TEST_STORE(x1,x3,0,x10,x11,0x800000,-0x5,140,sw,0)
inst_45:
// rs2_val == 4194304,
// opcode: sw; op1:x10; op2:x11; op2val:0x400000; immval:0x2; align:0
TEST_STORE(x1,x3,0,x10,x11,0x400000,0x2,144,sw,0)
inst_46:
// rs2_val == 2097152,
// opcode: sw; op1:x10; op2:x11; op2val:0x200000; immval:-0x1; align:0
TEST_STORE(x1,x3,0,x10,x11,0x200000,-0x1,148,sw,0)
inst_47:
// rs2_val == 1048576,
// opcode: sw; op1:x10; op2:x11; op2val:0x100000; immval:-0x9; align:0
TEST_STORE(x1,x3,0,x10,x11,0x100000,-0x9,152,sw,0)
inst_48:
// rs2_val == 524288,
// opcode: sw; op1:x10; op2:x11; op2val:0x80000; immval:0x400; align:0
TEST_STORE(x1,x3,0,x10,x11,0x80000,0x400,156,sw,0)
inst_49:
// rs2_val == 262144,
// opcode: sw; op1:x10; op2:x11; op2val:0x40000; immval:0x555; align:0
TEST_STORE(x1,x3,0,x10,x11,0x40000,0x555,160,sw,0)
inst_50:
// rs2_val == 131072,
// opcode: sw; op1:x10; op2:x11; op2val:0x20000; immval:-0x8; align:0
TEST_STORE(x1,x3,0,x10,x11,0x20000,-0x8,164,sw,0)
inst_51:
// rs2_val == 65536,
// opcode: sw; op1:x10; op2:x11; op2val:0x10000; immval:-0x2; align:0
TEST_STORE(x1,x3,0,x10,x11,0x10000,-0x2,168,sw,0)
inst_52:
// rs2_val == 32768,
// opcode: sw; op1:x10; op2:x11; op2val:0x8000; immval:-0xa; align:0
TEST_STORE(x1,x3,0,x10,x11,0x8000,-0xa,172,sw,0)
inst_53:
// rs2_val == 16384,
// opcode: sw; op1:x10; op2:x11; op2val:0x4000; immval:-0x1; align:0
TEST_STORE(x1,x3,0,x10,x11,0x4000,-0x1,176,sw,0)
inst_54:
// rs2_val == 8192,
// opcode: sw; op1:x10; op2:x11; op2val:0x2000; immval:-0x201; align:0
TEST_STORE(x1,x3,0,x10,x11,0x2000,-0x201,180,sw,0)
inst_55:
// rs2_val == 4096,
// opcode: sw; op1:x10; op2:x11; op2val:0x1000; immval:0x7; align:0
TEST_STORE(x1,x3,0,x10,x11,0x1000,0x7,184,sw,0)
inst_56:
// rs2_val == 2048,
// opcode: sw; op1:x10; op2:x11; op2val:0x800; immval:-0x81; align:0
TEST_STORE(x1,x3,0,x10,x11,0x800,-0x81,188,sw,0)
inst_57:
// rs2_val == 1024,
// opcode: sw; op1:x10; op2:x11; op2val:0x400; immval:-0x401; align:0
TEST_STORE(x1,x3,0,x10,x11,0x400,-0x401,192,sw,0)
inst_58:
// rs2_val == 512,
// opcode: sw; op1:x10; op2:x11; op2val:0x200; immval:0x7; align:0
TEST_STORE(x1,x3,0,x10,x11,0x200,0x7,196,sw,0)
inst_59:
// rs2_val == 256,
// opcode: sw; op1:x10; op2:x11; op2val:0x100; immval:-0x101; align:0
TEST_STORE(x1,x3,0,x10,x11,0x100,-0x101,200,sw,0)
inst_60:
// rs2_val == 128,
// opcode: sw; op1:x10; op2:x11; op2val:0x80; immval:-0x21; align:0
TEST_STORE(x1,x3,0,x10,x11,0x80,-0x21,204,sw,0)
inst_61:
// rs2_val == 64,
// opcode: sw; op1:x10; op2:x11; op2val:0x40; immval:0x40; align:0
TEST_STORE(x1,x3,0,x10,x11,0x40,0x40,208,sw,0)
inst_62:
// rs2_val == 32,
// opcode: sw; op1:x10; op2:x11; op2val:0x20; immval:0x9; align:0
TEST_STORE(x1,x3,0,x10,x11,0x20,0x9,212,sw,0)
inst_63:
// rs2_val == 16,
// opcode: sw; op1:x10; op2:x11; op2val:0x10; immval:0x10; align:0
TEST_STORE(x1,x3,0,x10,x11,0x10,0x10,216,sw,0)
inst_64:
// rs2_val == 8,
// opcode: sw; op1:x10; op2:x11; op2val:0x8; immval:0x400; align:0
TEST_STORE(x1,x3,0,x10,x11,0x8,0x400,220,sw,0)
inst_65:
// rs2_val == 4,
// opcode: sw; op1:x10; op2:x11; op2val:0x4; immval:-0x401; align:0
TEST_STORE(x1,x3,0,x10,x11,0x4,-0x401,224,sw,0)
inst_66:
// rs2_val == 2,
// opcode: sw; op1:x10; op2:x11; op2val:0x2; immval:-0x400; align:0
TEST_STORE(x1,x3,0,x10,x11,0x2,-0x400,228,sw,0)
inst_67:
// rs2_val == -1073741825, imm_val < 0
// opcode: sw; op1:x10; op2:x11; op2val:-0x40000001; immval:-0x4; align:0
TEST_STORE(x1,x3,0,x10,x11,-0x40000001,-0x4,232,sw,0)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
signature_x2_0:
.fill 0*(XLEN/32),4,0xdeadbeef
signature_x2_1:
.fill 9*(XLEN/32),4,0xdeadbeef
signature_x1_0:
.fill 59*(XLEN/32),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3004
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-xor-01.S
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tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-xori-01.S
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4
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/K_unratified/Makefile
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@ -1,4 +0,0 @@
include ../../Makefile.include
$(eval $(call compile_template,-march=rv32ib -mabi=ilp32 -DXLEN=$(XLEN)))

31
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/K_unratified/Makefrag
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@ -1,31 +0,0 @@
# RISC-V Compliance Test RV32K Makefrag
#
#
# Copyright (c) 2021 Imperas Software Ltd., www.imperas.com
# Copyright (c) 2021 Indian Institute of Technology Madras
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
# either express or implied.
#
# See the License for the specific language governing permissions and
# limitations under the License.
#
#
#
# Description: Makefrag for RV32K compliance tests
rv32k_sc_tests = \
rv32k_tests = $(addsuffix .elf, $(rv32k_sc_tests))
target_tests += $(rv32k_tests)

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zifencei/Makefile
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@ -1,3 +0,0 @@
include ../../Makefile.include
$(eval $(call compile_template,-march=rv32i -mabi=ilp32 -DXLEN=$(XLEN)))

34
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zifencei/Makefrag
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@ -1,34 +0,0 @@
# RISC-V Architecture Test RV32I Makefrag
#
# Copyright (c) 2017, Codasip Ltd.
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
# * Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# * Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# * Neither the name of the Codasip Ltd. nor the
# names of its contributors may be used to endorse or promote products
# derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd. BE LIABLE FOR ANY
# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Description: Makefrag for RV32I architectural tests
rv32i_sc_tests = \
rv32i_tests = $(addsuffix .elf, $(rv32i_sc_tests))
target_tests += $(rv32i_tests)

4
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/Makefile
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@ -1,4 +0,0 @@
include ../../Makefile.include
$(eval $(call compile_template,-march=rv64ib -mabi=lp64 -DXLEN=$(XLEN)))

31
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/Makefrag
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@ -1,31 +0,0 @@
# RISC-V Compliance Test RV64K Makefrag
#
#
# Copyright (c) 2021 Imperas Software Ltd., www.imperas.com
# Copyright (c) 2021 Indian Institute of Technology Madras
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
# either express or implied.
#
# See the License for the specific language governing permissions and
# limitations under the License.
#
#
#
# Description: Makefrag for RV64K compliance tests
rv64k_sc_tests = \
rv64k_tests = $(addsuffix .elf, $(rv64k_sc_tests))
target_tests += $(rv64k_tests)

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