Jordan Carlin
82d9467eea
Add coverage of FIOM in different privelege modes
2024-01-18 19:29:16 -08:00
Jordan Carlin
12b2baff82
add coverage of sfence.inval.ir instruction and fix sret coverage
2024-01-18 17:33:59 -08:00
David Harris
f986f53fc2
Merge pull request #580 from ross144/main
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Fixes remaining issues with issue #405 . Virtual memory now works without d$.
2024-01-18 07:37:57 -08:00
Rose Thompson
ff6bb3be0c
Fixed another bug with virtual memory and no caches.
2024-01-18 09:29:52 -06:00
Rose Thompson
e8474373e4
Fixed it so Virtual Memory work without a D$.
2024-01-18 09:18:17 -06:00
David Harris
7069a90cb1
Merge pull request #579 from naichewa/main
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fixed SPI tests failing when no I$ disabled
2024-01-17 17:50:43 -08:00
naichewa
8b60992e72
fixed SPI tests failing when no icache
2024-01-17 14:38:11 -08:00
Rose Thompson
2d3dc55986
Fixed bug. After I$ invalidated. If the pipelined wasn't stalled the I$ still output the old instruction on the next cycle. Now the I$ ensure that invalidation leads to the next cycle not hitting.
2024-01-17 12:19:10 -06:00
Rose Thompson
ed0f0d924b
Merge pull request #577 from davidharrishmc/dev
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Zfh fix and typo corrections
2024-01-16 14:23:23 -06:00
David Harris
60e09965d5
Enabled Zfh support in rv64gc
2024-01-16 11:14:43 -08:00
David Harris
846a0c4d50
Check fma operations don't support H precision
2024-01-16 11:12:06 -08:00
David Harris
1a77c08f6e
Fixed issues 575 and 477 about FPU tests failing when Zfh = 1.
2024-01-16 10:46:44 -08:00
David Harris
dcd40c6be7
Fixed spelling of output
2024-01-16 10:27:31 -08:00
David Harris
abecc98563
Fixed spelling of precision
2024-01-16 10:26:00 -08:00
David Harris
0c331e7828
Merge pull request #576 from ross144/main
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Fixes some but not all of the Issue #405 bugs. Fixes non-cached atomics, zifence when there is no dcache, and more serious bug with compressedF not supressed on the last cycle of a bus fetch.
2024-01-16 10:03:02 -08:00
Rose Thompson
ff5554ca61
Atomics work correctly without a d cache.
2024-01-16 10:43:20 -06:00
David Harris
bb3a7850c4
Simplified floating-point parameters in config-shared
2024-01-15 17:48:41 -08:00
Rose Thompson
dfe5ef4427
Added logic for the non-cache atomics.
2024-01-15 17:47:17 -06:00
Rose Thompson
82a786f185
Hmm. Verilator is complaining about the parameter width. I'm not sure why so I changed to 1 bit.
2024-01-15 17:36:01 -06:00
Rose Thompson
614a83331f
Fixed part of issue #405 .
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The non-cache version of the bus controller did not have the correct supression of BusCommitted for a read only controller.
2024-01-15 17:29:00 -06:00
Rose Thompson
83df3dfe83
Fixed the zifencei bug (part of issue 405).
2024-01-15 16:02:37 -06:00
David Harris
0235970313
Optimized away unused support for fmv with quads
2024-01-15 13:40:12 -08:00
Rose Thompson
dc99027570
Merge branch 'main' of https://github.com/openhwgroup/cvw
2024-01-15 15:29:35 -06:00
David Harris
0d56a281b9
Cleaned up indentation in testbench-fp
2024-01-15 13:25:46 -08:00
David Harris
da4eca4854
Tested Zfh support using unreleased version of risch-arch-test Zfh tests. Fixed two bugs in fmv to/from int.
2024-01-15 13:24:57 -08:00
Rose Thompson
b11e8ea420
Merge pull request #573 from davidharrishmc/dev
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fcvt fix, coverage improvement
2024-01-15 11:53:00 -06:00
David Harris
9e78a7e290
Incorporated jstine fixes of FPU special case and testbench for conversion
2024-01-15 07:25:08 -08:00
David Harris
50b7ddb450
Increase verilator stack size limit
2024-01-15 07:24:18 -08:00
David Harris
f8c88a398a
Coverage improvements
2024-01-15 07:16:41 -08:00
David Harris
ed9fa07ba3
tests/coverage/tlbmisc.S
2024-01-15 07:16:11 -08:00
David Harris
fd181169fe
Corrected spelling of negative
2024-01-15 07:15:23 -08:00
David Harris
bf0d02b9b6
Merge pull request #572 from stineje/main
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Update for fp to int conversion for IEEE 754 vs. RISC-V
2024-01-15 07:12:11 -08:00
David Harris
332194a95f
Merge pull request #570 from Sanket-0510/sanket_dockerfile_issue
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fixed python to python3 in dockerfile
2024-01-15 06:25:46 -08:00
James E. Stine
b14cd67bef
Values for IEEE 754 vs. RISC-V Table 11.4 in the RISC-V Unprivileged ISA
2024-01-14 22:08:42 -06:00
James E. Stine
f267c20601
Update QP for Makefile that works on Ubuntu and RHEL - adds API call to quadmath instead of RHEL printf of %Q. This will allow the examples to compile for both OSes
2024-01-14 22:07:32 -06:00
sanket
9c5e49862b
fixed python to python3 in dockerfile
2024-01-14 01:15:20 +05:30
David Harris
c62ddc234a
Merge pull request #567 from jordancarlin/main
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Add Zcb coverage and fix c.sext.b bug in decompress module
2024-01-12 19:44:36 -08:00
Jordan Carlin
51f670c821
Merge branch 'openhwgroup:main' into main
2024-01-12 19:43:01 -08:00
Rose Thompson
dd5f69cb78
Merge pull request #565 from davidharrishmc/dev
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Dev
2024-01-12 21:30:27 -06:00
Jordan Carlin
6c797570fa
Add coverage for all Zcb instructions
2024-01-12 19:10:13 -08:00
Jordan Carlin
092d10a3cd
correct c.sext.b encoding and remove unreachable code in 01100 case
2024-01-12 19:09:10 -08:00
David Harris
a9acb5f269
Added comments with a way to build Sail on RedHat
2024-01-12 18:13:11 -08:00
David Harris
d7b016e8f3
Cleaned up Zicond implementation
2024-01-12 18:12:52 -08:00
David Harris
1e100cf770
Merge pull request #564 from ross144/main
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Modified priv tests to work with 128MiB memory limit. Modified rv64gc to use only 128MiB. Simulation is faster 3 minutes vs 2m22s. Required for VCS.
2024-01-12 18:09:53 -08:00
Rose Thompson
1531526981
Merge branch 'main' of https://github.com/openhwgroup/cvw
2024-01-12 20:06:36 -06:00
Rose Thompson
3fd44126e6
Merge pull request #563 from openhwgroup/revert-562-main
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Revert "Fixes for Issue #541 "
2024-01-12 20:06:28 -06:00
Rose Thompson
404c657b45
Merge branch 'main' of https://github.com/openhwgroup/cvw
2024-01-12 20:03:13 -06:00
Rose Thompson
ba95e5fafd
Reduced the rv64gc config to 128MiB memory.
2024-01-12 20:01:05 -06:00
Rose Thompson
0b2af0c99a
Modifed the sv39 tests so they work with just 128MiB physical memory.
2024-01-12 20:00:21 -06:00
Rose Thompson
e6a2595936
Modified sv48 svadu test to work with 128MB rather than 2GB physical memory.
2024-01-12 11:05:06 -06:00
