mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-03 10:15:19 +00:00
Merge pull request #573 from davidharrishmc/dev
fcvt fix, coverage improvement
This commit is contained in:
Rose Thompson
GitHub
commit
b11e8ea420
@ -46,4 +46,7 @@ extend PATH /usr/local/bin/verilator # Change this for your path to Verilator
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#set path = ($RISCV/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64 $path)
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#setenv LD_LIBRARY_PATH $RISCV/imperas_riscv_tests/riscv-ovpsim-plus/bin/Linux64:$LD_LIBRARY_PATH # remove if no imperas
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# Verilator needs a larger stack to simulate CORE-V Wally
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limit stacksize unlimited
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echo "setup done"
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@ -37,7 +37,7 @@ module fclassify import cvw::*; #(parameter cvw_t P) (
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);
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logic PInf, PZero, PNorm, PSubnorm; // is the input a positive infinity/zero/normal/subnormal
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logic NInf, NZero, NNorm, NSubnorm; // is the input a negitive infinity/zero/normal/subnormal
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logic NInf, NZero, NNorm, NSubnorm; // is the input a negative infinity/zero/normal/subnormal
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logic XNorm; // is the input normal
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// determine the sub categories
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@ -215,7 +215,7 @@ module fctrl import cvw::*; #(parameter cvw_t P) (
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// rounding modes:
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// 000 - round to nearest, ties to even
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// 001 - round twords 0 - round to min magnitude
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// 010 - round down - round twords negitive infinity
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// 010 - round down - round twords negative infinity
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// 011 - round up - round twords positive infinity
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// 100 - round to nearest, ties to max magnitude - round to nearest, ties away from zero
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// 111 - dynamic - choose FRM_REGW as rounding mode
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@ -80,7 +80,7 @@ module fcvt import cvw::*; #(parameter cvw_t P) (
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///////////////////////////////////////////////////////////////////////////
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// negation
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///////////////////////////////////////////////////////////////////////////
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// 1) negate the input if the input is a negitive singed integer
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// 1) negate the input if the input is a negative singed integer
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// 2) trim the input to the proper size (kill the 32 most significant zeroes if needed)
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assign PosInt = Cs ? -Int : Int;
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@ -182,7 +182,7 @@ module fcvt import cvw::*; #(parameter cvw_t P) (
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assign Ce = {1'b0, OldExp} - (P.NE+1)'(P.BIAS) - {{P.NE-P.LOGCVTLEN+1{1'b0}}, (LeadingZeros)} + {2'b0, NewBias};
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// find if the result is dnormal or underflows
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// - if Calculated expoenent is 0 or negitive (and the input/result is not exactaly 0)
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// - if Calculated expoenent is 0 or negative (and the input/result is not exactaly 0)
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// - can't underflow an integer to Fp conversion
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assign ResSubnormUf = (~|Ce | Ce[P.NE])&~XZero&~IntToFp;
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@ -190,7 +190,7 @@ module fcvt import cvw::*; #(parameter cvw_t P) (
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// shifter
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///////////////////////////////////////////////////////////////////////////
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// kill the shift if it's negitive
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// kill the shift if it's negative
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// select the amount to shift by
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// fp -> int:
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// - shift left by CalcExp - essentially shifting until the unbiased exponent = 0
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@ -42,8 +42,8 @@ module fmaadd import cvw::*; #(parameter cvw_t P) (
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output logic [3*P.NF+3:0] Sm // the positive sum
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);
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logic [3*P.NF+3:0] PreSum, NegPreSum; // possibly negitive sum
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logic NegSum; // was the sum negitive
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logic [3*P.NF+3:0] PreSum, NegPreSum; // possibly negative sum
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logic NegSum; // was the sum negative
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///////////////////////////////////////////////////////////////////////////////
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// Addition
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@ -54,8 +54,8 @@ module fmaadd import cvw::*; #(parameter cvw_t P) (
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// Kill the product if the product is too small to effect the addition (determined in fma1.sv)
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assign PmKilled = {2*P.NF+2{~KillProd}}&Pm;
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// Do the addition
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// - calculate a positive and negitive sum in parallel
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// if there was a small negitive number killed in the alignment stage one needs to be subtracted from the sum
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// - calculate a positive and negative sum in parallel
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// if there was a small negative number killed in the alignment stage one needs to be subtracted from the sum
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// prod - addend where some of the addend is put into the sticky bit then don't add +1 from negation
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// ie ~(InvA&ASticky&~KillProd)&InvA = (~ASticky|KillProd)&InvA
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// addend - prod where product is killed (and not exactly zero) then don't add +1 from negation
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@ -66,10 +66,10 @@ module fmaadd import cvw::*; #(parameter cvw_t P) (
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// Choose the positive sum and accompanying LZA result.
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assign Sm = NegSum ? NegPreSum : PreSum;
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// is the result negitive
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// if p - z is the Sum negitive
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// is the result negative
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// if p - z is the Sum negative
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// if -p + z is the Sum positive
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// if -p - z then the Sum is negitive
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// if -p - z then the Sum is negative
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assign Ss = NegSum^Ps;
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assign Se = KillProd ? {2'b0, Ze} : Pe;
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endmodule
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@ -45,7 +45,7 @@ module fmaalign import cvw::*; #(parameter cvw_t P) (
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///////////////////////////////////////////////////////////////////////////////
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// determine the shift count for alignment
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// - negitive means Z is larger, so shift Z left
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// - negative means Z is larger, so shift Z left
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// - positive means the product is larger, so shift Z right
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// This could have been done using Pe, but ACnt is on the critical path so we replicate logic for speed
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assign ACnt = {2'b0, Xe} + {2'b0, Ye} - {2'b0, (P.NE)'(P.BIAS)} + (P.NE+2)'(P.NF+2) - {2'b0, Ze};
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@ -36,7 +36,7 @@ module divshiftcalc import cvw::*; #(parameter cvw_t P) (
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);
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logic [P.LOGNORMSHIFTSZ-1:0] NormShift; // normalized result shift amount
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logic [P.LOGNORMSHIFTSZ-1:0] DivSubnormShiftAmt; // subnormal result shift amount (killed if negitive)
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logic [P.LOGNORMSHIFTSZ-1:0] DivSubnormShiftAmt; // subnormal result shift amount (killed if negative)
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logic [P.NE+1:0] DivSubnormShift; // subnormal result shift amount
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// is the result subnormal
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@ -62,7 +62,7 @@ module divshiftcalc import cvw::*; #(parameter cvw_t P) (
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// shift one more if the it's a minimally redundent radix 4 - one entire cycle needed for integer bit
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assign NormShift = (P.LOGNORMSHIFTSZ)'(P.NF);
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// if the shift amount is negitive then don't shift (keep sticky bit)
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// if the shift amount is negative then don't shift (keep sticky bit)
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// need to multiply the early termination shift by LOGR*DIVCOPIES = left shift of log2(LOGR*DIVCOPIES)
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assign DivSubnormShiftAmt = DivSubnormShiftPos ? DivSubnormShift[P.LOGNORMSHIFTSZ-1:0] : '0;
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assign DivShiftAmt = DivResSubnorm ? DivSubnormShiftAmt : NormShift;
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@ -47,7 +47,7 @@ module flags import cvw::*; #(parameter cvw_t P) (
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input logic Int64, // convert to 64 bit integer
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input logic Signed, // convert to a signed integer
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input logic [P.NE:0] CvtCe, // the calculated expoent - Cvt
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input logic [1:0] CvtNegResMsbs, // the negitive integer result's most significant bits
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input logic [1:0] CvtNegResMsbs, // the negative integer result's most significant bits
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// divsqrt
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input logic DivOp, // conversion opperation?
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input logic Sqrt, // Sqrt?
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@ -122,7 +122,7 @@ module flags import cvw::*; #(parameter cvw_t P) (
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// calulate overflow flag:
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// if the result is greater than or equal to the max exponent(not taking into account sign)
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// | and the exponent isn't negitive
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// | and the exponent isn't negative
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// | | if the input isnt infinity or NaN
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// | | |
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assign Overflow = ResExpGteMax & ~FullRe[P.NE+1]&~(InfIn|NaNIn|DivByZero);
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@ -132,7 +132,7 @@ module flags import cvw::*; #(parameter cvw_t P) (
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///////////////////////////////////////////////////////////////////////////////
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// calculate underflow flag: detecting tininess after rounding
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// the exponent is negitive
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// the exponent is negative
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// | the result is subnormal
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// | | the result is normal and rounded from a Subnorm
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// | | | and if given an unbounded exponent the result does not round
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@ -170,7 +170,7 @@ module flags import cvw::*; #(parameter cvw_t P) (
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// invalid flag for integer result
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// if the input is NaN or infinity
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// | if the integer res overflows (out of range)
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// | | if the input was negitive but ouputing to a unsigned number
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// | | if the input was negative but ouputing to a unsigned number
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// | | | the res doesn't round to zero
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// | | | | or the res rounds up out of bounds
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// | | | | and the res didn't underflow
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@ -47,7 +47,7 @@ module resultsign(
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// determine the sign for a result of 0
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// The IEEE754-2019 standard specifies:
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// - the sign of an exact zero sum (with operands of diffrent signs) should be positive unless rounding toward negitive infinity
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// - the sign of an exact zero sum (with operands of diffrent signs) should be positive unless rounding toward negative infinity
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// - when the exact result of an FMA opperation is non-zero, but is zero due to rounding, use the sign of the exact result
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// - if x = +0 or -0 then x+x=x and x-(-x)=x
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// - the sign of a product is the exclisive or or the opperand's signs
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@ -63,10 +63,10 @@ module resultsign(
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assign Zeros = (FmaPs^FmaAs)&~(Round|Guard|Sticky)&~Mult ? Frm[1:0] == 2'b10 : FmaPs;
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// determine the sign of an infinity result
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// is the result negitive
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// if p - z is the Sum negitive
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// is the result negative
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// if p - z is the Sum negative
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// if -p + z is the Sum positive
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// if -p - z then the Sum is negitive
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// if -p - z then the Sum is negative
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assign Infs = ZInf ? FmaAs : FmaPs;
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// select the result sign
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@ -277,7 +277,7 @@ module specialcase import cvw::*; #(parameter cvw_t P) (
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// IEEE 754
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// select the overflow integer res
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// - negitive infinity and out of range negitive input
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// - negative infinity and out of range negative input
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// | int | long |
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// signed | -2^31 | -2^63 |
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// unsigned | 2^32-1 | 2^64-1 |
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@ -291,7 +291,7 @@ module specialcase import cvw::*; #(parameter cvw_t P) (
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// RISC-V
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// select the overflow integer res
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// - negitive infinity and out of range negitive input
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// - negative infinity and out of range negative input
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// | int | long |
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// signed | -2^31 | -2^63 |
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// unsigned | 0 | 0 |
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@ -303,38 +303,37 @@ module specialcase import cvw::*; #(parameter cvw_t P) (
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//
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// other: 32 bit unsinged res should be sign extended as if it were a signed number
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if(P.IEEE754) begin
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if(P.IEEE754) begin
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always_comb
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if(Signed)
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if(Xs&~NaNIn) // signed negitive
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if(Int64) OfIntRes = {1'b1, {P.XLEN-1{1'b0}}};
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else OfIntRes = {{P.XLEN-32{1'b1}}, 1'b1, {31{1'b0}}};
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else // signed positive
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if(Int64) OfIntRes = {1'b1, {P.XLEN-1{1'b0}}};
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else OfIntRes = {{P.XLEN-32{1'b1}}, 1'b1, {31{1'b0}}};
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else
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if(Xs&~NaNIn) OfIntRes = {P.XLEN{1'b1}}; // unsigned negitive
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else OfIntRes = {P.XLEN{1'b1}}; // unsigned positive
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end // if (P.IEEE754)
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else begin
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if(Signed)
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if(Xs&~NaNIn) // signed negative
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if(Int64) OfIntRes = {1'b1, {P.XLEN-1{1'b0}}};
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else OfIntRes = {{P.XLEN-32{1'b1}}, 1'b1, {31{1'b0}}};
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else // signed positive
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if(Int64) OfIntRes = {1'b1, {P.XLEN-1{1'b0}}};
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else OfIntRes = {{P.XLEN-32{1'b1}}, 1'b1, {31{1'b0}}};
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else
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if(Xs&~NaNIn) OfIntRes = {P.XLEN{1'b1}}; // unsigned negative
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else OfIntRes = {P.XLEN{1'b1}}; // unsigned positive
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end else begin
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always_comb
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if(Signed)
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if(Xs&~NaNIn) // signed negitive
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if(Int64) OfIntRes = {1'b1, {P.XLEN-1{1'b0}}};
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else OfIntRes = {{P.XLEN-32{1'b1}}, 1'b1, {31{1'b0}}};
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else // signed positive
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if(Int64) OfIntRes = {1'b0, {P.XLEN-1{1'b1}}};
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else OfIntRes = {{P.XLEN-32{1'b0}}, 1'b0, {31{1'b1}}};
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else
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if(Xs&~NaNIn) OfIntRes = {P.XLEN{1'b0}}; // unsigned negitive
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else OfIntRes = {P.XLEN{1'b1}}; // unsigned positive
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end // else: !if(P.IEEE754)
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if(Signed)
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if(Xs&~NaNIn) // signed negative
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if(Int64) OfIntRes = {1'b1, {P.XLEN-1{1'b0}}};
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else OfIntRes = {{P.XLEN-32{1'b1}}, 1'b1, {31{1'b0}}};
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else // signed positive
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if(Int64) OfIntRes = {1'b0, {P.XLEN-1{1'b1}}};
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else OfIntRes = {{P.XLEN-32{1'b0}}, 1'b0, {31{1'b1}}};
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else
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if(Xs&~NaNIn) OfIntRes = {P.XLEN{1'b0}}; // unsigned negative
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else OfIntRes = {P.XLEN{1'b1}}; // unsigned positive
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end
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// select the integer output
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// - if the input is invalid (out of bounds NaN or Inf) then output overflow res
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// - if the input underflows
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// - if rounding and signed opperation and negitive input, output -1
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// - if rounding and signed opperation and negative input, output -1
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// - otherwise output a rounded 0
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// - otherwise output the normal res (trmined and sign extended if nessisary)
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always_comb
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@ -160,9 +160,9 @@ module csrs import cvw::*; #(parameter cvw_t P) (
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CSRSReadValM = 0;
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IllegalCSRSAccessM = 1;
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end
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STIMECMPH: if (STCE)
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STIMECMPH: if (STCE & P.XLEN == 32) // not supported for RV64
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CSRSReadValM = {{(P.XLEN-32){1'b0}}, STIMECMP_REGW[63:32]};
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else begin // not supported for RV64
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else begin
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CSRSReadValM = 0;
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IllegalCSRSAccessM = 1;
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end
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@ -882,98 +882,88 @@ module testbenchfp;
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// - the sign of the NaN does not matter for the opperations being tested
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// - when 2 or more NaNs are inputed the NaN that is propigated doesn't matter
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if (UnitVal !== `CVTFPUNIT & UnitVal !== `CVTINTUNIT)
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case (FmtVal)
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2'b11: NaNGood = (((P.IEEE754==0)&AnsNaN&(Res === {1'b0, {P.Q_NE+1{1'b1}}, {P.Q_NF-1{1'b0}}})) |
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(AnsFlg[4]&(Res[P.Q_LEN-2:0] === {{P.Q_NE+1{1'b1}}, {P.Q_NF-1{1'b0}}})) |
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(XNaN&(Res[P.Q_LEN-2:0] === {X[P.Q_LEN-2:P.Q_NF],1'b1,X[P.Q_NF-2:0]})) |
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(YNaN&(Res[P.Q_LEN-2:0] === {Y[P.Q_LEN-2:P.Q_NF],1'b1,Y[P.Q_NF-2:0]})) |
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(ZNaN&(Res[P.Q_LEN-2:0] === {Z[P.Q_LEN-2:P.Q_NF],1'b1,Z[P.Q_NF-2:0]})));
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2'b01: NaNGood = (((P.IEEE754==0)&AnsNaN&(Res[P.D_LEN-1:0] === {1'b0, {P.D_NE+1{1'b1}}, {P.D_NF-1{1'b0}}})) |
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(AnsFlg[4]&(Res[P.D_LEN-2:0] === {{P.D_NE+1{1'b1}}, {P.D_NF-1{1'b0}}})) |
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(XNaN&(Res[P.D_LEN-2:0] === {X[P.D_LEN-2:P.D_NF],1'b1,X[P.D_NF-2:0]})) |
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(YNaN&(Res[P.D_LEN-2:0] === {Y[P.D_LEN-2:P.D_NF],1'b1,Y[P.D_NF-2:0]})) |
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(ZNaN&(Res[P.D_LEN-2:0] === {Z[P.D_LEN-2:P.D_NF],1'b1,Z[P.D_NF-2:0]})));
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2'b00: NaNGood = (((P.IEEE754==0)&AnsNaN&(Res[P.S_LEN-1:0] === {1'b0, {P.S_NE+1{1'b1}}, {P.S_NF-1{1'b0}}})) |
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(AnsFlg[4]&(Res[P.S_LEN-2:0] === {{P.S_NE+1{1'b1}}, {P.S_NF-1{1'b0}}})) |
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(XNaN&(Res[P.S_LEN-2:0] === {X[P.S_LEN-2:P.S_NF],1'b1,X[P.S_NF-2:0]})) |
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(YNaN&(Res[P.S_LEN-2:0] === {Y[P.S_LEN-2:P.S_NF],1'b1,Y[P.S_NF-2:0]})) |
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(ZNaN&(Res[P.S_LEN-2:0] === {Z[P.S_LEN-2:P.S_NF],1'b1,Z[P.S_NF-2:0]})));
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2'b10: NaNGood = (((P.IEEE754==0)&AnsNaN&(Res[P.H_LEN-1:0] === {1'b0, {P.H_NE+1{1'b1}}, {P.H_NF-1{1'b0}}})) |
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(AnsFlg[4]&(Res[P.H_LEN-2:0] === {{P.H_NE+1{1'b1}}, {P.H_NF-1{1'b0}}})) |
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(XNaN&(Res[P.H_LEN-2:0] === {X[P.H_LEN-2:P.H_NF],1'b1,X[P.H_NF-2:0]})) |
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(YNaN&(Res[P.H_LEN-2:0] === {Y[P.H_LEN-2:P.H_NF],1'b1,Y[P.H_NF-2:0]})) |
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(ZNaN&(Res[P.H_LEN-2:0] === {Z[P.H_LEN-2:P.H_NF],1'b1,Z[P.H_NF-2:0]})));
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endcase
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else if (UnitVal === `CVTFPUNIT) // if converting from floating point to floating point OpCtrl contains the final FP format
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case (OpCtrlVal[1:0])
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2'b11: NaNGood = (((P.IEEE754==0)&AnsNaN&(Res === {1'b0, {P.Q_NE+1{1'b1}}, {P.Q_NF-1{1'b0}}})) |
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(AnsFlg[4]&(Res[P.Q_LEN-2:0] === {{P.Q_NE+1{1'b1}}, {P.Q_NF-1{1'b0}}})) |
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(AnsNaN&(Res[P.Q_LEN-2:0] === Ans[P.Q_LEN-2:0])) |
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(XNaN&(Res[P.Q_LEN-2:0] === {X[P.Q_LEN-2:P.Q_NF],1'b1,X[P.Q_NF-2:0]})) |
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(YNaN&(Res[P.Q_LEN-2:0] === {Y[P.Q_LEN-2:P.Q_NF],1'b1,Y[P.Q_NF-2:0]})));
|
||||
2'b01: NaNGood = (((P.IEEE754==0)&AnsNaN&(Res[P.D_LEN-1:0] === {1'b0, {P.D_NE+1{1'b1}}, {P.D_NF-1{1'b0}}})) |
|
||||
(AnsFlg[4]&(Res[P.D_LEN-2:0] === {{P.D_NE+1{1'b1}}, {P.D_NF-1{1'b0}}})) |
|
||||
(AnsNaN&(Res[P.D_LEN-2:0] === Ans[P.D_LEN-2:0])) |
|
||||
(XNaN&(Res[P.D_LEN-2:0] === {X[P.D_LEN-2:P.D_NF],1'b1,X[P.D_NF-2:0]})) |
|
||||
(YNaN&(Res[P.D_LEN-2:0] === {Y[P.D_LEN-2:P.D_NF],1'b1,Y[P.D_NF-2:0]})));
|
||||
2'b00: NaNGood = (((P.IEEE754==0)&AnsNaN&(Res[P.S_LEN-1:0] === {1'b0, {P.S_NE+1{1'b1}}, {P.S_NF-1{1'b0}}})) |
|
||||
(AnsFlg[4]&(Res[P.S_LEN-2:0] === {{P.S_NE+1{1'b1}}, {P.S_NF-1{1'b0}}})) |
|
||||
(AnsNaN&(Res[P.S_LEN-2:0] === Ans[P.S_LEN-2:0])) |
|
||||
(XNaN&(Res[P.S_LEN-2:0] === {X[P.S_LEN-2:P.S_NF],1'b1,X[P.S_NF-2:0]})) |
|
||||
(YNaN&(Res[P.S_LEN-2:0] === {Y[P.S_LEN-2:P.S_NF],1'b1,Y[P.S_NF-2:0]})));
|
||||
2'b10: NaNGood = (((P.IEEE754==0)&AnsNaN&(Res[P.H_LEN-1:0] === {1'b0, {P.H_NE+1{1'b1}}, {P.H_NF-1{1'b0}}})) |
|
||||
(AnsFlg[4]&(Res[P.H_LEN-2:0] === {{P.H_NE+1{1'b1}}, {P.H_NF-1{1'b0}}})) |
|
||||
(AnsNaN&(Res[P.H_LEN-2:0] === Ans[P.H_LEN-2:0])) |
|
||||
(XNaN&(Res[P.H_LEN-2:0] === {X[P.H_LEN-2:P.H_NF],1'b1,X[P.H_NF-2:0]})) |
|
||||
(YNaN&(Res[P.H_LEN-2:0] === {Y[P.H_LEN-2:P.H_NF],1'b1,Y[P.H_NF-2:0]})));
|
||||
endcase
|
||||
else NaNGood = 1'b0; // integers can't be NaNs
|
||||
case (FmtVal)
|
||||
2'b11: NaNGood = (((P.IEEE754==0)&AnsNaN&(Res === {1'b0, {P.Q_NE+1{1'b1}}, {P.Q_NF-1{1'b0}}})) |
|
||||
(AnsFlg[4]&(Res[P.Q_LEN-2:0] === {{P.Q_NE+1{1'b1}}, {P.Q_NF-1{1'b0}}})) |
|
||||
(XNaN&(Res[P.Q_LEN-2:0] === {X[P.Q_LEN-2:P.Q_NF],1'b1,X[P.Q_NF-2:0]})) |
|
||||
(YNaN&(Res[P.Q_LEN-2:0] === {Y[P.Q_LEN-2:P.Q_NF],1'b1,Y[P.Q_NF-2:0]})) |
|
||||
(ZNaN&(Res[P.Q_LEN-2:0] === {Z[P.Q_LEN-2:P.Q_NF],1'b1,Z[P.Q_NF-2:0]})));
|
||||
2'b01: NaNGood = (((P.IEEE754==0)&AnsNaN&(Res[P.D_LEN-1:0] === {1'b0, {P.D_NE+1{1'b1}}, {P.D_NF-1{1'b0}}})) |
|
||||
(AnsFlg[4]&(Res[P.D_LEN-2:0] === {{P.D_NE+1{1'b1}}, {P.D_NF-1{1'b0}}})) |
|
||||
(XNaN&(Res[P.D_LEN-2:0] === {X[P.D_LEN-2:P.D_NF],1'b1,X[P.D_NF-2:0]})) |
|
||||
(YNaN&(Res[P.D_LEN-2:0] === {Y[P.D_LEN-2:P.D_NF],1'b1,Y[P.D_NF-2:0]})) |
|
||||
(ZNaN&(Res[P.D_LEN-2:0] === {Z[P.D_LEN-2:P.D_NF],1'b1,Z[P.D_NF-2:0]})));
|
||||
2'b00: NaNGood = (((P.IEEE754==0)&AnsNaN&(Res[P.S_LEN-1:0] === {1'b0, {P.S_NE+1{1'b1}}, {P.S_NF-1{1'b0}}})) |
|
||||
(AnsFlg[4]&(Res[P.S_LEN-2:0] === {{P.S_NE+1{1'b1}}, {P.S_NF-1{1'b0}}})) |
|
||||
(XNaN&(Res[P.S_LEN-2:0] === {X[P.S_LEN-2:P.S_NF],1'b1,X[P.S_NF-2:0]})) |
|
||||
(YNaN&(Res[P.S_LEN-2:0] === {Y[P.S_LEN-2:P.S_NF],1'b1,Y[P.S_NF-2:0]})) |
|
||||
(ZNaN&(Res[P.S_LEN-2:0] === {Z[P.S_LEN-2:P.S_NF],1'b1,Z[P.S_NF-2:0]})));
|
||||
2'b10: NaNGood = (((P.IEEE754==0)&AnsNaN&(Res[P.H_LEN-1:0] === {1'b0, {P.H_NE+1{1'b1}}, {P.H_NF-1{1'b0}}})) |
|
||||
(AnsFlg[4]&(Res[P.H_LEN-2:0] === {{P.H_NE+1{1'b1}}, {P.H_NF-1{1'b0}}})) |
|
||||
(XNaN&(Res[P.H_LEN-2:0] === {X[P.H_LEN-2:P.H_NF],1'b1,X[P.H_NF-2:0]})) |
|
||||
(YNaN&(Res[P.H_LEN-2:0] === {Y[P.H_LEN-2:P.H_NF],1'b1,Y[P.H_NF-2:0]})) |
|
||||
(ZNaN&(Res[P.H_LEN-2:0] === {Z[P.H_LEN-2:P.H_NF],1'b1,Z[P.H_NF-2:0]})));
|
||||
endcase
|
||||
else if (UnitVal === `CVTFPUNIT) // if converting from floating point to floating point OpCtrl contains the final FP format
|
||||
case (OpCtrlVal[1:0])
|
||||
2'b11: NaNGood = (((P.IEEE754==0)&AnsNaN&(Res === {1'b0, {P.Q_NE+1{1'b1}}, {P.Q_NF-1{1'b0}}})) |
|
||||
(AnsFlg[4]&(Res[P.Q_LEN-2:0] === {{P.Q_NE+1{1'b1}}, {P.Q_NF-1{1'b0}}})) |
|
||||
(AnsNaN&(Res[P.Q_LEN-2:0] === Ans[P.Q_LEN-2:0])) |
|
||||
(XNaN&(Res[P.Q_LEN-2:0] === {X[P.Q_LEN-2:P.Q_NF],1'b1,X[P.Q_NF-2:0]})) |
|
||||
(YNaN&(Res[P.Q_LEN-2:0] === {Y[P.Q_LEN-2:P.Q_NF],1'b1,Y[P.Q_NF-2:0]})));
|
||||
2'b01: NaNGood = (((P.IEEE754==0)&AnsNaN&(Res[P.D_LEN-1:0] === {1'b0, {P.D_NE+1{1'b1}}, {P.D_NF-1{1'b0}}})) |
|
||||
(AnsFlg[4]&(Res[P.D_LEN-2:0] === {{P.D_NE+1{1'b1}}, {P.D_NF-1{1'b0}}})) |
|
||||
(AnsNaN&(Res[P.D_LEN-2:0] === Ans[P.D_LEN-2:0])) |
|
||||
(XNaN&(Res[P.D_LEN-2:0] === {X[P.D_LEN-2:P.D_NF],1'b1,X[P.D_NF-2:0]})) |
|
||||
(YNaN&(Res[P.D_LEN-2:0] === {Y[P.D_LEN-2:P.D_NF],1'b1,Y[P.D_NF-2:0]})));
|
||||
2'b00: NaNGood = (((P.IEEE754==0)&AnsNaN&(Res[P.S_LEN-1:0] === {1'b0, {P.S_NE+1{1'b1}}, {P.S_NF-1{1'b0}}})) |
|
||||
(AnsFlg[4]&(Res[P.S_LEN-2:0] === {{P.S_NE+1{1'b1}}, {P.S_NF-1{1'b0}}})) |
|
||||
(AnsNaN&(Res[P.S_LEN-2:0] === Ans[P.S_LEN-2:0])) |
|
||||
(XNaN&(Res[P.S_LEN-2:0] === {X[P.S_LEN-2:P.S_NF],1'b1,X[P.S_NF-2:0]})) |
|
||||
(YNaN&(Res[P.S_LEN-2:0] === {Y[P.S_LEN-2:P.S_NF],1'b1,Y[P.S_NF-2:0]})));
|
||||
2'b10: NaNGood = (((P.IEEE754==0)&AnsNaN&(Res[P.H_LEN-1:0] === {1'b0, {P.H_NE+1{1'b1}}, {P.H_NF-1{1'b0}}})) |
|
||||
(AnsFlg[4]&(Res[P.H_LEN-2:0] === {{P.H_NE+1{1'b1}}, {P.H_NF-1{1'b0}}})) |
|
||||
(AnsNaN&(Res[P.H_LEN-2:0] === Ans[P.H_LEN-2:0])) |
|
||||
(XNaN&(Res[P.H_LEN-2:0] === {X[P.H_LEN-2:P.H_NF],1'b1,X[P.H_NF-2:0]})) |
|
||||
(YNaN&(Res[P.H_LEN-2:0] === {Y[P.H_LEN-2:P.H_NF],1'b1,Y[P.H_NF-2:0]})));
|
||||
endcase
|
||||
else NaNGood = 1'b0; // integers can't be NaNs
|
||||
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// ||||||| ||| ||| ||||||| ||||||| ||| |||
|
||||
// ||| ||| ||| ||| ||| ||| |||
|
||||
// ||| |||||||||| ||||||| ||| ||||||
|
||||
// ||| ||| ||| ||| ||| ||| |||
|
||||
// ||||||| ||| ||| ||||||| ||||||| ||| |||
|
||||
// ||||||| ||| ||| ||||||| ||||||| ||| |||
|
||||
// ||| ||| ||| ||| ||| ||| |||
|
||||
// ||| |||||||||| ||||||| ||| ||||||
|
||||
// ||| ||| ||| ||| ||| ||| |||
|
||||
// ||||||| ||| ||| ||||||| ||||||| ||| |||
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////////////////////
|
||||
///////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// check if result is correct
|
||||
// wait till the division result is done or one extra cylcle for early termination (to simulate the EM pipline stage)
|
||||
assign ResMatch = ((Res === Ans) | NaNGood | (NaNGood === 1'bx));
|
||||
assign FlagMatch = ((ResFlg === AnsFlg) | (AnsFlg === 5'bx));
|
||||
assign divsqrtop = (OpCtrlVal == `SQRT_OPCTRL) | (OpCtrlVal == `DIV_OPCTRL);
|
||||
assign FMAop = (OpCtrlVal == `FMAUNIT);
|
||||
assign DivDone = OldFDivBusyE & ~FDivBusyE;
|
||||
// check if result is correct
|
||||
// wait till the division result is done or one extra cylcle for early termination (to simulate the EM pipline stage)
|
||||
assign ResMatch = ((Res === Ans) | NaNGood | (NaNGood === 1'bx));
|
||||
assign FlagMatch = ((ResFlg === AnsFlg) | (AnsFlg === 5'bx));
|
||||
assign divsqrtop = (OpCtrlVal == `SQRT_OPCTRL) | (OpCtrlVal == `DIV_OPCTRL);
|
||||
assign FMAop = (OpCtrlVal == `FMAUNIT);
|
||||
assign DivDone = OldFDivBusyE & ~FDivBusyE;
|
||||
|
||||
// Maybe change OpCtrl but for now just look at TEST for fma test
|
||||
assign CheckNow = ((DivDone | ~divsqrtop) | (TEST == "add" | TEST == "fma" | TEST == "sub")) & (UnitVal !== `CVTINTUNIT) & (UnitVal !== `CMPUNIT);
|
||||
if (~(ResMatch & FlagMatch) & CheckNow) begin
|
||||
errors += 1;
|
||||
$display("\nError in %s", Tests[TestNum]);
|
||||
$display("TestNum %d OpCtrl %d", TestNum, OpCtrl[TestNum]);
|
||||
$display("inputs: %h %h %h\nSrcA: %h\n Res: %h %h\n Expected: %h %h", X, Y, Z, SrcA, Res, ResFlg, Ans, AnsFlg);
|
||||
$stop;
|
||||
end
|
||||
|
||||
// TestFloat sets the result to all 1's when there is an invalid result, however in
|
||||
// http://www.jhauser.us/arithmetic/TestFloat-3/doc/TestFloat-general.html it says
|
||||
// for an unsigned integer result 0 is also okay
|
||||
|
||||
// TestFloat outputs 800... for both the largest integer values for both positive and negitive numbers but
|
||||
// the riscv spec specifies 2^31-1 for positive values out of range and NaNs ie 7fff...
|
||||
else if ( ((UnitVal === `CVTINTUNIT) | (UnitVal === `CMPUNIT)) & ~FlagMatch ) begin
|
||||
// ResMatch & FlagMatch checks the result again. It is checked within the
|
||||
// test again to avoid issues related when the values change tests (e.g., f16_eq_rne -> f16_eq_rz)
|
||||
if (~(ResMatch & FlagMatch)) begin
|
||||
errors += 1;
|
||||
$display("\nError in %s", Tests[TestNum]);
|
||||
$display("TestNum %d OpCtrl %d", TestNum, OpCtrl[TestNum]);
|
||||
$display("inputs: %h %h %h\nSrcA: %h\n Res: %h %h\n Ans: %h %h", X, Y, Z, SrcA, Res, ResFlg, Ans, AnsFlg);
|
||||
$stop;
|
||||
end
|
||||
// Maybe change OpCtrl but for now just look at TEST for fma test
|
||||
assign CheckNow = ((DivDone | ~divsqrtop) | (TEST == "add" | TEST == "fma" | TEST == "sub")) & (UnitVal !== `CVTINTUNIT) & (UnitVal !== `CMPUNIT);
|
||||
if (~(ResMatch & FlagMatch) & CheckNow) begin
|
||||
errors += 1;
|
||||
$display("\nError in %s", Tests[TestNum]);
|
||||
$display("TestNum %d OpCtrl %d", TestNum, OpCtrl[TestNum]);
|
||||
$display("inputs: %h %h %h\nSrcA: %h\n Res: %h %h\n Expected: %h %h", X, Y, Z, SrcA, Res, ResFlg, Ans, AnsFlg);
|
||||
$stop;
|
||||
end else if (((UnitVal === `CVTINTUNIT) | (UnitVal === `CMPUNIT)) &
|
||||
~(ResMatch & FlagMatch) & (Ans[0] !== 1'bx)) begin // Check for conversion and comparisons
|
||||
errors += 1;
|
||||
$display("\nError in %s", Tests[TestNum]);
|
||||
$display("TestNum %d OpCtrl %d", TestNum, OpCtrl[TestNum]);
|
||||
$display("inputs: %h %h %h\nSrcA: %h\n Res: %h %h\n Ans: %h %h", X, Y, Z, SrcA, Res, ResFlg, Ans, AnsFlg);
|
||||
$stop;
|
||||
end
|
||||
end
|
||||
|
||||
if (TestVectors[VectorNum][0] === 1'bx & Tests[TestNum] !== "") begin // if reached the eof
|
||||
|
||||
@ -40,6 +40,10 @@ main:
|
||||
sw t5, 0(t0)
|
||||
fence.i
|
||||
|
||||
# Test not being able to write illegal SATP mode
|
||||
li t5, 0xA000000000080010
|
||||
csrw satp, t5
|
||||
|
||||
# Page table root address at 0x80010000; SV48
|
||||
li t5, 0x9000000000080010
|
||||
csrw satp, t5
|
||||
|
||||
Loading…
Reference in New Issue
Block a user