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https://github.com/openhwgroup/cvw
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Merge pull request #567 from jordancarlin/main
Add Zcb coverage and fix c.sext.b bug in decompress module
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c62ddc234a
@ -165,14 +165,14 @@ module decompress import cvw::*; #(parameter cvw_t P) (
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InstrD = {7'b0000000, rs2p, rds1p, 3'b110, rds1p, 7'b0110011}; // c.or
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else // if (instr16[6:5] == 2'b11)
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InstrD = {7'b0000000, rs2p, rds1p, 3'b111, rds1p, 7'b0110011}; // c.and
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else if (instr16[12:10] == 3'b111) begin
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else begin // (instr16[12:10] == 3'b111)
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if (instr16[6:5] == 2'b00 & P.XLEN > 32)
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InstrD = {7'b0100000, rs2p, rds1p, 3'b000, rds1p, 7'b0111011}; // c.subw
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else if (instr16[6:5] == 2'b01 & P.XLEN > 32)
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InstrD = {7'b0000000, rs2p, rds1p, 3'b000, rds1p, 7'b0111011}; // c.addw
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else if (instr16[6:2] == 5'b11000 & P.ZCB_SUPPORTED)
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InstrD = {12'b000011111111, rds1p, 3'b111, rds1p, 7'b0010011}; // c.zext.b = andi rd, rs1, 255
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else if (instr16[6:2] == 5'b10101 & P.ZCB_SUPPORTED)
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else if (instr16[6:2] == 5'b11001 & P.ZCB_SUPPORTED)
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InstrD = {12'b011000000100, rds1p, 3'b001, rds1p, 7'b0010011}; // c.sext.b
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else if (instr16[6:2] == 5'b11010 & P.ZCB_SUPPORTED)
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InstrD = {7'b0000100, 5'b00000, rds1p, 3'b100, rds1p, 3'b011, P.XLEN > 32, 3'b011}; // c.zext.h
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@ -188,9 +188,9 @@ module decompress import cvw::*; #(parameter cvw_t P) (
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IllegalCompInstrD = 1;
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InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
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end
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end else begin // illegal instruction
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/** end else begin // illegal instruction
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IllegalCompInstrD = 1;
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InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
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InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap **/
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end
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5'b01101: InstrD = {immCJ, 5'b00000, 7'b1101111}; // c.j
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5'b01110: InstrD = {immCB[11:5], 5'b00000, rs1p, 3'b000, immCB[4:0], 7'b1100011}; // c.beqz
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@ -40,12 +40,40 @@ main:
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.hword 0x2002 // c.fldsp fs0, 0
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.hword 0xA002 // c.fsdsp fs0, 0
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.hword 0x9C41 // line 134 Illegal compressed instruction
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# Zcb coverage tests
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# could restore assembly language versions when GCC supports Zcb
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# c.lbu s1, 0(s0) // exercise c.lbu
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mv s0, sp
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#c.lbu s1, 0(s0) // exercise c.lbu
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.hword 0x8004 // c.lbu s1, 0(s0)
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#c.lh s1, 0(s0) // exercise c.lh
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.hword 0x8444 // c.lh s1, 0(s0)
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#c.lhu s1, 0(s0) // exercise c.lhu
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.hword 0x8404 // c.lhu s1, 0(s0)
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#c.sb s1, 0(s0) // exercise c.sb
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.hword 0x8804 // c.sb s1, 0(s0)
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#c.sh s1, 0(s0) // exercise c.sh
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.hword 0x8C04 // c.sh s1, 0(s0)
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.hword 0x8C44 // Illegal compressed instruction with op = 00, Instr[15:10] = 100011, Instr[6] = 1 and 0's everywhere else. Line 119 illegal instruction
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.hword 0x9C00 // Illegal compressed instruction with op = 00, Instr[15:10] = 100111, and 0's everywhere else. Line 119 illegal instruction
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li s0, 0xFF
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# c.zext.b s0 // exercise c.zext.b
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.hword 0x9C61 // c.zext.b s0
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# c.sext.b s0 // exercise c.sext.b
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.hword 0x9C65 // c.sext.b s0
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# c.zext.h s0 // exercise c.zext.h
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.hword 0x9C69 // c.zext.h s0
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# c.sext.h s0 // exercise c.sext.h
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.hword 0x9C6D // c.sext.h s0
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# c.zext.w s0 // exercise c.zext.w
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.hword 0x9C71 // c.zext.w s0
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# c.not s0 // exercise c.not
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.hword 0x9C75 // c.not s0
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.hword 0x9C7D // Reserved instruction from line 187 with op = 01, Instr[15:10] = 100111, Instr[6:5] = 11, and 0's everywhere else
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//.hword 0x9C01 //# Illegal compressed instruction with op = 01, instr[15:10] = 100111, and 0's everywhere else
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