325 Commits

Author	SHA1	Message	Date
David Harris	8a910aabf4	Documentation and comment fixes	2024-11-27 05:42:39 -08:00
David Harris	028ffe9f4a	Removing obsolete ***	2024-11-20 07:23:51 -08:00
David Harris	147f62d9a5	Fixed timer offset in RV32 WALLY-wfi; simplified in RV64 WALLY-wfi	2024-11-17 06:43:13 -08:00
David Harris	205db4348c	Fixed cause_m_time_interrupt most significant byte	2024-11-16 18:31:02 -08:00
naichewa	73c2165756	recommit sckmode 10 11 delay regression tests	2024-11-05 11:30:13 -08:00
naichewa	9822902a4f	Revert "Added SCKMODE 10 and 11 delay cases to regression tests" ... unwanted submodule changes This reverts commit 38a88862ac.	2024-11-05 11:17:01 -08:00
naichewa	38a88862ac	Added SCKMODE 10 and 11 delay cases to regression tests	2024-11-04 16:22:42 -08:00
naichewa	3fda7ecb81	Fix SPI regression tests	2024-11-01 13:09:41 -07:00
naichewa	960d72295c	Removed SPI hardware interlock test cases	2024-11-01 11:27:41 -07:00
David Harris	1c1acc467e	Tweaked SPI to avoid breaking VCS, but the SCLK divider still doesn't produce the right frequency and SCLKenableEarly looks like it wouldn't work for SckDiv = 0	2024-10-26 02:01:09 -07:00
Rose Thompson	8fb1673ab3	Updated email address authorship for my files.	2024-10-15 10:27:53 -05:00
Jordan Carlin	8cb0c08e68	more wally-riscv-arch-test cleanup	2024-09-29 10:28:31 -07:00
Jordan Carlin	766b0a83d7	Remove wally32d tests since they are covered elsewhere now	2024-09-29 10:27:20 -07:00
Jordan Carlin	330eda243c	Remove wally32i and wally64i tests since they are covered elsewhere now	2024-09-29 10:26:08 -07:00
David Harris	6e0b0487dd	Recreated coverage changes	2024-09-05 16:32:45 -07:00
naichewa	58be9e0556	Merge branch 'spi_debug'	2024-09-03 15:00:59 -07:00
naichewa	3b7661dfd5	SckDiv Zero bug fixes	2024-09-03 14:58:46 -07:00
David Harris	ff9f0fa140	Updated riscv-isac dependencies for security	2024-09-03 03:46:44 -07:00
Jacob Pease	d8b75440b6	With Naiche's help, we fixed the SPI controllers clock polarity and phase settings. Added conditions to the SPI regression tests.	2024-08-20 16:24:37 -05:00
David Harris	32a8a6b3d1	Merge pull request #873 from Shreesh-Kulkarni/main ... Modified riscv-isacov and riscv-ctg files to support some missing quad instructions.	2024-08-16 11:10:35 -07:00
Shreesh-Kulkarni	82b42a5faf	Modified riscv-isacov and riscv-ctg files to support some missing quad instructions. Needs debugging.	2024-07-06 08:57:32 -07:00
David Harris	8fe2052b1f	Fix derived configuration with new derivgen script	2024-06-26 16:09:59 -07:00
David Harris	21e5fa3103	Merge pull request #854 from Shreesh-Kulkarni/main ... Files for Quad Precision Testing Support for Wally	2024-06-26 11:41:26 -07:00
Shreesh-Kulkarni	93fb0f2a84	Files for Quad Precision Testing Support for Wally	2024-06-26 11:36:04 -07:00
Jordan Carlin	d58b454a8b	Finish switching Zfa to use riscv-arch-test	2024-06-18 23:31:37 -07:00
Jordan Carlin	6f79dca9c4	Merge branch 'main' of https://github.com/openhwgroup/cvw	2024-05-27 12:29:24 -07:00
Jordan Carlin	dcafe4793e	Add froundnx and fround.d tests	2024-05-24 15:16:35 -07:00
Jordan Carlin	f410bbb79e	Use Zfa tests from riscv-arch-test instead of wally-riscv-arch-test	2024-05-21 00:04:27 -07:00
David Harris	712a167a3a	Removed obsolete testgen files	2024-05-04 02:44:31 -07:00
David Harris	4eb7de7381	Removed Zfh tests from wally-riscv-arch-test now that they are available in riscv-arch-test	2024-03-26 13:58:59 -07:00
David Harris	6688577bc4	Fixed fcvt test macro	2024-03-25 12:21:15 -07:00
David Harris	690338b758	Incorporated fixed fcvt.h.l* instructions; they now run in the testbench	2024-03-25 06:08:27 -07:00
David Harris	b3661a0af4	Removed unused WALLY-lrsc reference outputs that were incorrect and are not used because Sail is the reference instead	2024-03-24 12:31:49 -07:00
David Harris	9ff9f9e0ae	Updated wally-riscv-arch-test to be able to compile zfh and zfa tests. This caused a change in startup code, so certain reference_output results needed to change to compensate. Also commented out fcvtmod test in Zfa that fails because Sail produces the wrong expected value.	2024-03-14 19:03:57 -07:00
David Harris	48799aa87c	Added Zfh and Zfa tests to wally-riscv-arch-test until they are accepted in riscv-arch-test repo	2024-03-14 10:49:36 -07:00
Rose Thompson	402d71e5f4	Added basic Quad testing.	2024-03-07 15:19:53 -06:00
Rose Thompson	a85ace87c7	Sold progress towards a decent q test.	2024-03-07 15:01:48 -06:00
Rose Thompson	1872966b0b	Progress.	2024-03-07 13:02:24 -06:00
David Harris	824bc0dab7	Fixed expected value on WALLY-satp-invalid	2024-02-16 11:12:57 -08:00
Rose Thompson	6110799a1e	Updated the wally rv32 priv tests to not use sail.	2024-02-16 11:39:06 -06:00
David Harris	b362320dd9	Removed unused Makefiles and Makefrags from wally-riscv-arch-test now that it is only used by riscof	2024-02-16 06:46:49 -08:00
David Harris	d094201362	Added NO_SAIL to wally-riscv-arch-test cases that stopped passing in Sail	2024-02-16 06:27:49 -08:00
David Harris	d9003da8e0	Moved some tests to wally-riscv-arch-test list that are simulated	2024-01-30 10:28:51 -08:00
naichewa	8b60992e72	fixed SPI tests failing when no icache	2024-01-17 14:38:11 -08:00
Rose Thompson	0b2af0c99a	Modifed the sv39 tests so they work with just 128MiB physical memory.	2024-01-12 20:00:21 -06:00
Rose Thompson	e6a2595936	Modified sv48 svadu test to work with 128MB rather than 2GB physical memory.	2024-01-12 11:05:06 -06:00
David Harris	caedab679a	Rewrote testbench to count signature entries rather than looking for x; this will facilitate Verilator which does not use x	2024-01-07 07:14:12 -08:00
David Harris	0ff049db86	Removed unused tests from wally-riscv-arch-test	2023-12-20 13:34:12 -08:00
David Harris	8552369687	Merged PR538, delete unused tests	2023-12-20 13:30:31 -08:00
Rose Thompson	70d0169019	All regression tests which matter are running!	2023-12-20 14:57:52 -06:00