Fix derived configuration with new derivgen script

This commit is contained in:
David Harris 2024-06-26 16:09:59 -07:00
parent 21e5fa3103
commit 8fe2052b1f
2 changed files with 11 additions and 1 deletions

View File

@ -106,6 +106,7 @@ F_SUPPORTED 0
ZCF_SUPPORTED 0
D_SUPPORTED 0
ZCD_SUPPORTED 0
deriv syn_sram_rv64gc_noFPU syn_sram_rv64gc_noPriv
F_SUPPORTED 0
ZCF_SUPPORTED 0
@ -788,10 +789,12 @@ ZKNH_SUPPORTED 1
deriv f_rv32gc rv32gc
D_SUPPORTED 0
ZFH_SUPPORTED 0
ZCD_SUPPORTED 0
deriv fh_rv32gc rv32gc
D_SUPPORTED 0
ZFH_SUPPORTED 1
ZCD_SUPPORTED 0
deriv fd_rv32gc rv32gc
ZFH_SUPPORTED 0
@ -810,10 +813,12 @@ ZFH_SUPPORTED 1
deriv f_rv64gc rv64gc
D_SUPPORTED 0
ZFH_SUPPORTED 0
ZCD_SUPPORTED 0
deriv fh_rv64gc rv64gc
D_SUPPORTED 0
ZFH_SUPPORTED 1
ZCD_SUPPORTED 0
deriv fd_rv64gc rv64gc
ZFH_SUPPORTED 0

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@ -22,7 +22,12 @@ riscv-ctg-> This folder consists of the CTG tool which is responsible for genera
riscof -> The riscof directory in Wally was changed to include some Quad precision template files for compilation. Along with modification of scripts and yaml files to support FLEN=128
TO DO:
Debug why fadd.q_b1 doesn't match Sail vs. Spike
Run the q test on Wally RTL
Make more tests from the working datasets
Get other datasets working by using softfloat to do quad math
Push changes back to riscv-ctg and riscv-isac and remove them from wally-riscv-arch/tsts/riscv-test-suite/rv64i_m/Q
Start by installing riscv-ctg via the following commands :