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Fix derived configuration with new derivgen script
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21e5fa3103
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@ -106,6 +106,7 @@ F_SUPPORTED 0
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ZCF_SUPPORTED 0
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D_SUPPORTED 0
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ZCD_SUPPORTED 0
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deriv syn_sram_rv64gc_noFPU syn_sram_rv64gc_noPriv
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F_SUPPORTED 0
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ZCF_SUPPORTED 0
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@ -788,10 +789,12 @@ ZKNH_SUPPORTED 1
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deriv f_rv32gc rv32gc
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D_SUPPORTED 0
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ZFH_SUPPORTED 0
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ZCD_SUPPORTED 0
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deriv fh_rv32gc rv32gc
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D_SUPPORTED 0
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ZFH_SUPPORTED 1
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ZCD_SUPPORTED 0
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deriv fd_rv32gc rv32gc
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ZFH_SUPPORTED 0
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@ -810,10 +813,12 @@ ZFH_SUPPORTED 1
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deriv f_rv64gc rv64gc
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D_SUPPORTED 0
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ZFH_SUPPORTED 0
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ZCD_SUPPORTED 0
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deriv fh_rv64gc rv64gc
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D_SUPPORTED 0
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ZFH_SUPPORTED 1
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ZCD_SUPPORTED 0
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deriv fd_rv64gc rv64gc
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ZFH_SUPPORTED 0
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@ -22,7 +22,12 @@ riscv-ctg-> This folder consists of the CTG tool which is responsible for genera
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riscof -> The riscof directory in Wally was changed to include some Quad precision template files for compilation. Along with modification of scripts and yaml files to support FLEN=128
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TO DO:
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Debug why fadd.q_b1 doesn't match Sail vs. Spike
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Run the q test on Wally RTL
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Make more tests from the working datasets
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Get other datasets working by using softfloat to do quad math
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Push changes back to riscv-ctg and riscv-isac and remove them from wally-riscv-arch/tsts/riscv-test-suite/rv64i_m/Q
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Start by installing riscv-ctg via the following commands :
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