Rose Thompson
739e73ef81
Revert "Siginficant cleanup of subwordwritemisaligned."
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This reverts commit fbc18abaa0
2024-03-06 15:15:58 -06:00
Rose Thompson
e7ec2bedd4
Revert "Simplifications of subword code."
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This reverts commit a402883115
2024-03-06 15:15:51 -06:00
Rose Thompson
b64b883129
Revert "Removed duplicate endianswap."
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This reverts commit caac48b7f2
2024-03-06 15:15:43 -06:00
Rose Thompson
5447159cfd
Revert "Cleanup."
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This reverts commit e84b7cc147
2024-03-06 15:15:26 -06:00
Rose Thompson
2ea0134329
Revert "Trying an experiment. Use the less compact subwordreaddouble in the fpga synthesize rather than subwordreadmisaligned."
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This reverts commit cba3209e7f
2024-03-06 13:28:59 -06:00
Rose Thompson
068ffda5fb
Revert "Revert "Trying an experiment. Use the less compact subwordreaddouble in the fpga synthesize rather than subwordreadmisaligned.""
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This reverts commit 8136b45ca7
2024-03-06 13:28:47 -06:00
Rose Thompson
a22de45631
Removed unused storedelay from align.
2024-03-02 16:20:31 -06:00
Rose Thompson
8136b45ca7
Revert "Trying an experiment. Use the less compact subwordreaddouble in the fpga synthesize rather than subwordreadmisaligned."
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This reverts commit cba3209e7f
2024-03-02 11:55:43 -06:00
Rose Thompson
cba3209e7f
Trying an experiment. Use the less compact subwordreaddouble in the fpga synthesize rather than subwordreadmisaligned.
2024-03-02 11:38:33 -06:00
Rose Thompson
ab750e150f
Fixed lint errors for alignment.
2024-02-23 14:00:19 -06:00
Rose Thompson
e84b7cc147
Cleanup.
2024-02-23 13:00:21 -06:00
Rose Thompson
caac48b7f2
Removed duplicate endianswap.
2024-02-23 09:42:39 -06:00
Rose Thompson
a402883115
Simplifications of subword code.
2024-02-23 09:41:59 -06:00
Rose Thompson
fbc18abaa0
Siginficant cleanup of subwordwritemisaligned.
2024-02-22 14:17:15 -06:00
Rose Thompson
45c30267a5
Cleanup.
2024-02-22 14:08:04 -06:00
Rose Thompson
69d31d50e2
Updated subword misaligned.
2024-02-22 13:29:39 -06:00
Rose Thompson
7e1ea1e6d9
Beginning subword cleanup.
2024-02-22 09:37:16 -06:00
Rose Thompson
1ece6f8eae
Swapped to the more compact subwordreadmisaligned.sv.
2024-02-22 09:34:16 -06:00
Rose Thompson
3714b2bf4a
Non-ideal fix. Added new output from pma which indicates if the write shift should occur.
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The more ideal solution would be to have the pma indicate if the shift should occur and the maximum amount..
2024-02-22 09:14:43 -06:00
Rose Thompson
6a9c2d8dc4
Closer to getting subword write misaligned working.
2024-02-20 20:23:42 -06:00
Rose Thompson
dac8fc16af
Partially working optimized subwordwrite for misaligned.
2024-02-19 12:26:29 -06:00
Rose Thompson
1fd678b433
Optimized the align logic for loads.
2024-02-14 12:14:19 -06:00
Rose Thompson
e900bb09db
Merge branch 'main' of https://github.com/openhwgroup/cvw
2024-02-01 12:12:05 -06:00
David Harris
1c62c5e433
Fixed logic to work with FLEN < XLEN
2024-01-31 20:24:16 -08:00
Rose Thompson
aa15a63d9c
Merge branch 'main' of https://github.com/openhwgroup/cvw
2024-01-31 13:12:32 -06:00
David Harris
f37c7bb1f6
Incorporated RAM_LATENCY and BURST_EN as parameters rather than define in code. Still need to update testbench to use this
2024-01-30 06:27:18 -08:00
David Harris
45e2317636
Added Wally github address to header comments
2024-01-29 05:38:11 -08:00
Rose Thompson
81d006536a
Lint passes with 32-bit no D$, but many regressions fail.
2024-01-18 09:48:44 -06:00
Rose Thompson
ff6bb3be0c
Fixed another bug with virtual memory and no caches.
2024-01-18 09:29:52 -06:00
Rose Thompson
e8474373e4
Fixed it so Virtual Memory work without a D$.
2024-01-18 09:18:17 -06:00
Rose Thompson
dfe5ef4427
Added logic for the non-cache atomics.
2024-01-15 17:47:17 -06:00
Rose Thompson
82a786f185
Hmm. Verilator is complaining about the parameter width. I'm not sure why so I changed to 1 bit.
2024-01-15 17:36:01 -06:00
Rose Thompson
83df3dfe83
Fixed the zifencei bug (part of issue 405).
2024-01-15 16:02:37 -06:00
Rose Thompson
edc56c669e
Fixed bug 546. non-leaf non-zero PBMT bit raise page fault.
2024-01-05 17:10:14 -06:00
David Harris
680a014876
Finished LSU tlbcontrol coverage tests
2024-01-02 10:16:20 -08:00
David Harris
f4ee05e1ea
Coverage improvements
2024-01-01 08:31:09 -08:00
David Harris
e5ac2d5ef0
Modified align fsm to make coverage easier
2024-01-01 08:21:31 -08:00
Rose Thompson
730efefc41
Cleanup.
2023-12-29 16:18:30 -06:00
Rose Thompson
6a787981c2
Restored cache store delay hazard.
2023-12-29 16:10:27 -06:00
Rose Thompson
0264a17f77
Reverted dtim to use store delay stall, but only (load after store).
2023-12-29 16:06:30 -06:00
Rose Thompson
f59fa5089d
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-12-29 15:13:18 -06:00
Rose Thompson
8030b7d100
Added partial code for uncached amo operations.
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Minor fix for Makefile so coverage tests build.
2023-12-29 15:07:20 -06:00
Rose Thompson
52dad4f130
cbo.zero works for uncached memory now!
2023-12-29 11:11:06 -06:00
David Harris
e8df856fdb
Renamed CMOp to CMOpM in mmu and cache
2023-12-25 05:57:41 -08:00
David Harris
29f57958a9
Fixed WALLY-lrsc in ImperasDV by setting reservation set size to native word size and adjusting imperas.ic lr_sc_grain=8 to match
2023-12-14 15:32:36 -08:00
Rose Thompson
9f4c32d49c
Merge branch 'main' of github.com:ross144/cvw
2023-12-13 20:32:59 -06:00
Rose Thompson
b69a5b59cd
DTIM works without the store delay stall. Still a bit of work remaining. The DTIM needs cleanup.
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The cache needs a bit of clean up and the chapter needs updates.
The controller needs to be updated to remove the store delay hazard for cmo instructions.
2023-12-13 20:32:14 -06:00
David Harris
6c017141c5
Renamed HADE to ADUE for Svadu
2023-12-13 11:49:04 -08:00
Rose Thompson
13bb5d845b
On the way to solving the store delay hazard.
2023-12-13 10:39:01 -06:00
Rose Thompson
1ebc7aa95a
Optimized align.
2023-12-03 16:43:55 -06:00
