947 Commits

Author	SHA1	Message	Date
Rose Thompson	eed6f11df6	Merge branch 'main' of github.com:ross144/cvw	2023-11-20 11:29:45 -06:00
Rose Thompson	23e05cb8b2	Finally have the cbo way muxing controls reduced to something sane.	2023-11-20 11:28:03 -06:00
David Harris	8cb433cb66	Commented IROM preloading	2023-11-19 19:33:57 -08:00
David Harris	acd8a63628	Merge pull request #489 from ross144/main ... fixes issue #487	2023-11-18 19:22:33 -08:00
Jacob Pease	a1e7158bd9	Merge branch 'main' of github.com:openhwgroup/cvw	2023-11-18 19:20:48 -06:00
Jacob Pease	87e6a5ccf2	Updated ROM to preload bootloader from file and infer a block ram when building for FPGA.	2023-11-18 19:15:39 -06:00
Rose Thompson	8cbd3de413	Fixed Zicclsm bug. Misalignment and spill detection were not masked by access type. Therefore a page table walk which always aligned could have had an IEUAdrM misaligned which erroneously caused a shift in the read data.	2023-11-18 19:01:39 -06:00
David Harris	acc2db256f	turn off IDIVONFPU when FSUPPORTED=0. Already checked in sim, but need it in synth too for feature sweep	2023-11-17 20:25:24 -08:00
David Harris	eef39bd495	Fixed typo in lsu parameter	2023-11-15 08:30:48 -08:00
David Harris	817ddbc7c5	Adjusted LSU misaligned buffer to fix synthesis warning	2023-11-15 08:19:50 -08:00
David Harris	98176665de	Fixed messed-up hazard.sv	2023-11-15 08:05:41 -08:00
naichewa	8ffce456bd	Merge branch 'spi' into main	2023-11-14 14:51:06 -08:00
naichewa	1ab7c926ea	Final Code Review	2023-11-14 13:44:59 -08:00
Rose Thompson	bf51948616	Merge pull request #474 from davidharrishmc/dev ... FP and synthesis cleanup	2023-11-14 12:03:01 -08:00
David Harris	8ba0336c6f	Removed unused addins, cleaned up configuration to support half precision on RV64gc, gate unused hazard inputs to reduce critical path in rv32e	2023-11-14 11:01:58 -08:00
David Harris	a77bea9954	Merge pull request #472 from ross144/main ... Merge Zicclsm into main branch and removes the FPGA config. FPGA makefile now automatically creates the config when building	2023-11-14 08:34:06 -08:00
Rose Thompson	95fc5f4a1c	Towards removing the FPGA config file.	2023-11-13 17:20:26 -06:00
Rose Thompson	a6995af91c	Fixed bug in uncore updates which broke SDC.	2023-11-13 16:15:23 -06:00
Rose Thompson	707b0c557c	Cleanup and optimization of Zicclsm.	2023-11-13 14:28:22 -06:00
Rose Thompson	cc7a0b211a	Cleanup.	2023-11-13 12:35:11 -06:00
David Harris	121f685fa2	Removed assign statement inside always block	2023-11-13 07:23:15 -08:00
David Harris	c44ae93e22	DivStickyM no longer mysteriously needs to be gated with SqrtM after divder improvemenst	2023-11-12 20:23:27 -08:00
David Harris	065f3f3f6d	DivStickyM no longer mysteriously needs to be gated with SqrtM after divder improvemenst	2023-11-12 20:23:14 -08:00
David Harris	571c7d3be4	Divider cleanup	2023-11-12 19:41:12 -08:00
David Harris	f437336540	Explained sqrt preshifting	2023-11-12 10:05:54 -08:00
David Harris	7c50b2c571	Renamed qsel to uslc and simplified radix2 uslc	2023-11-12 06:36:57 -08:00
David Harris	002034845a	fdivsqrt comment improvements	2023-11-12 06:15:47 -08:00
David Harris	6ac83c776e	Cleaned up number of bits in fdivsqrt	2023-11-11 15:50:06 -08:00
David Harris	2bf5143163	Bug fixes related to size of fpdivsqrt bit count and number of cycles	2023-11-11 05:58:53 -08:00
David Harris	d5ba8fc5e6	fdivsqrt parameter cleanup	2023-11-10 18:33:08 -08:00
David Harris	3cae2385ab	Simplified out LOGRK parameter	2023-11-10 18:19:41 -08:00
David Harris	7d0d9dcebe	divider cleanup	2023-11-10 18:01:13 -08:00
David Harris	03864642a7	fdivsqrt cleanup	2023-11-10 16:42:32 -08:00
David Harris	c5b12b7331	Merge branch 'main' of https://github.com/openhwgroup/cvw into dev	2023-11-10 16:40:54 -08:00
Rose Thompson	c8cca8dfb8	Simplification.	2023-11-10 18:39:36 -06:00
Rose Thompson	c0e02ae190	Found another bug in the RTL's Zicclsm alignment.	2023-11-10 18:26:55 -06:00
Rose Thompson	02ab9fe99c	Fixed all the bugs associated with the signature and the store side of misaligned access. Load misaligned is still causing some issues.	2023-11-10 17:58:42 -06:00
Rose Thompson	84d86b1994	Fixed spill bugs in the aligner.	2023-11-10 17:18:45 -06:00
David Harris	3108b58290	Simplified integer postnormalization shift	2023-11-10 14:55:36 -08:00
David Harris	b315ead575	Simplified IntDivNormShift	2023-11-10 14:28:57 -08:00
Rose Thompson	b74bfbeefd	Merge branch 'main' into Zicclsm	2023-11-10 16:15:32 -06:00
Rose Thompson	9abd26aad9	Fixed bug which broke the non Zicclsm configs.	2023-11-10 16:08:04 -06:00
David Harris	2903791820	Simplified cycle count logic	2023-11-10 14:00:27 -08:00
David Harris	8f87860146	Reduced duplicated logic in fdivsqrtcycles	2023-11-10 11:25:54 -08:00
David Harris	255873a50c	Divsqrt cleanup: change Q to U, commenting code	2023-11-10 11:21:02 -08:00
David Harris	953c53d065	fdivsqrt parameter cleanup	2023-11-10 09:11:15 -08:00
David Harris	4c106215f4	Started cleaning up shifting leading 1 in fdivsqrt	2023-11-10 08:46:55 -08:00
naichewa	5ce16dcb63	Cleanup	2023-11-09 16:52:55 -08:00
naichewa	3052a68d84	Remove old 2/4 bit logic, add comments, ... clean up unused signals	2023-11-09 16:48:11 -08:00
naichewa	b13b8feee4	updated to-do comments	2023-11-08 15:28:51 -08:00