Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-01-24 13:34:28 +00:00
Code Issues Packages Projects Releases Wiki Activity
2,540 Commits 4 Branches 2 Tags 52 MiB
728e46a794
Commit Graph

2540 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
David Harris
291deb5c39 LSU partitioning 2022-01-14 23:02:28 +00:00
David Harris
36d49a8a74 Moved fp tests from testbench to tests/fp 2022-01-14 23:00:46 +00:00
Ross Thompson
db519a0dca Cleanup IFU comments. 2022-01-14 15:06:30 -06:00
Ross Thompson
a70e12ad75 Optimization in the ifu. Please note this optimization is not strictly correct, 
but is possible.  See comments in the ifu source code for details.
 2022-01-14 12:16:48 -06:00
Ross Thompson
a549079672 More ifu cleanup. 2022-01-14 11:19:12 -06:00
Ross Thompson
ce937a35a8 Added tim only test to regression-wally. Minor cleanup to ifu. 2022-01-14 11:13:06 -06:00
James E. Stine
115ea7dbb0 Update to TestFloat for scripts so can run automatically once 
TestFloat/Softfloat is compiled.  Slight change to the README as well.
 2022-01-14 09:25:37 -06:00
Ross Thompson
5726b5b640 Added support for logic memory in the IFU and LSU. This disables the bus interface. Peripherals do not work. Also requires using testbench-harvard.sv. I hope to merge this testbench with the main testbench.sv soon. 2022-01-13 22:21:43 -06:00
Ross Thompson
9f7e3f147b Partial local dtim in lsu configuration. 2022-01-13 17:50:31 -06:00
David Harris
d356a0d29f Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-01-13 21:46:00 +00:00
David Harris
e3f6c398b5 Mixed C and assembly language test cases; SRT initial version passing tests 2022-01-13 21:45:54 +00:00
Ross Thompson
0b06fa12ef Merge branch 'testDivInterruptInterlock' into main 2022-01-13 11:21:48 -06:00
Ross Thompson
93cb24476f Fixed interger divide so it can be interrupted. 2022-01-13 11:16:50 -06:00
Ross Thompson
4bcabd1a55 Removed unused inputs to hptw. 2022-01-13 11:04:48 -06:00
Ross Thompson
654a33bf92 Fixed bug in the lsu's write back data. If an AMO was uncached it would not be corrected executed because the write data to the bus would not include the amoalu. 2022-01-12 17:41:39 -06:00
Ross Thompson
861450c4d6 Fixed support to allow spills and no icache. 2022-01-12 17:25:16 -06:00
Ross Thompson
000d713cb5 Better solution to the integer divider interrupt interaction. 2022-01-12 14:22:18 -06:00
Ross Thompson
16aa3127b6 Merge branch 'testDivInterruptInterlock' of github.com:davidharrishmc/riscv-wally into testDivInterruptInterlock 2022-01-12 14:17:49 -06:00
Ross Thompson
26fb09c868 Added additional fsm to ILA. 2022-01-12 14:17:16 -06:00
Ross Thompson
6eb2f37ce4 Possible fix for the TrapM DTLBMiss suppression. 2022-01-12 14:17:16 -06:00
Ross Thompson
6b483e621d If a trap occurs concurrent with a I/DTLB miss the interlock fsm incorrectly goes into the states to handle the TLB miss. 
This commit fixes this bug by keeping the interlock fsm in the T0_READY state on TrapM.
 2022-01-12 14:17:16 -06:00
Ross Thompson
48c036a923 Oups. My hack for DivE interrupt prevention was wrong. 2022-01-12 14:17:16 -06:00
Ross Thompson
796316495d Hack "fix" to prevent interrupt from occuring during an integer divide. 
This is not the desired solution but will allow continued debuging of linux.
 2022-01-12 14:17:16 -06:00
Ross Thompson
ecd3912900 Set rv32ic to not use icache. 2022-01-12 14:10:09 -06:00
Ross Thompson
2ed052f152 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-01-12 13:29:19 -06:00
Ross Thompson
87485f9f64 Improve wavefile by adding performance counters. 2022-01-12 10:53:29 -06:00
David Harris
e41ce09b5d C sum example 2022-01-12 09:04:41 +00:00
James E. Stine
52a8ac9132 remove extraneous 2022-01-11 16:01:48 -06:00
James E. Stine
63a37395ef Update on assembly simple/spike 2022-01-11 15:59:56 -06:00
David Harris
c0439110e9 Added inline assembly to simple 2022-01-11 21:32:30 +00:00
David Harris
b1a780e677 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-01-11 21:01:50 +00:00
David Harris
e25760d8e5 Added C test cases 2022-01-11 21:01:48 +00:00
Kip Macsai-Goren
c99456d5e7 Fixed PMA regions, Added passing PMA tests to regression 2022-01-10 22:08:26 +00:00
David Harris
2a7e77d2b1 Do file for riscvsingle 2022-01-10 16:26:18 +00:00
David Harris
6587bd6944 Added fulladder example files 2022-01-10 16:15:05 +00:00
David Harris
4cae11ad28 Merged coremark changes 2022-01-10 05:09:28 +00:00
David Harris
50c17f2a03 Removed unused coremark_bare 2022-01-10 05:05:55 +00:00
David Harris
467aac8463 Added riscvsingle. Removed unnecessary coremark config. Added compiler flags for Coremark. 2022-01-10 05:04:13 +00:00
Ross Thompson
55456e465c Added icache access and icache miss to performance counters. 2022-01-09 22:56:56 -06:00
Ross Thompson
e01c8bc5f6 Added performance counters to wavefile. 2022-01-09 22:42:14 -06:00
Ross Thompson
3109fa1383 Fixed wavefile. 
Converted coremark to use elf2hex.
 2022-01-09 22:03:10 -06:00
Ross Thompson
73f7d36529 Added additional fsm to ILA. 2022-01-09 17:10:57 -06:00
Ross Thompson
c8689dc6ce Possible fix for the TrapM DTLBMiss suppression. 2022-01-09 14:22:14 -06:00
Kip Macsai-Goren
53f3a6dbab comment cleanup 2022-01-09 18:16:42 +00:00
Kip Macsai-Goren
9412a5ff2d updated PMA tests, everything passes except successful writes to protected regions. 2022-01-09 18:16:00 +00:00
Kip Macsai-Goren
a22dc4d163 changed test case types to lookup table instead of beq's 2022-01-09 16:56:37 +00:00
David Harris
89ee6c778e Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-01-09 14:39:33 +00:00
David Harris
80c87d16a9 Fixed RISCV path in coremark Makefile 2022-01-09 14:39:22 +00:00
Ross Thompson
2846118261 If a trap occurs concurrent with a I/DTLB miss the interlock fsm incorrectly goes into the states to handle the TLB miss. 
This commit fixes this bug by keeping the interlock fsm in the T0_READY state on TrapM.
 2022-01-08 20:49:45 -06:00
Ross Thompson
b856301ecf Oups. My hack for DivE interrupt prevention was wrong. 2022-01-08 17:21:27 -06:00