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Configurable RISC-V Processor
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Ross Thompson 796316495d Hack "fix" to prevent interrupt from occuring during an integer divide. 
This is not the desired solution but will allow continued debuging of linux.
2022-01-12 14:17:16 -06:00
addins Added C test cases 2022-01-11 21:01:48 +00:00
benchmarks/riscv-coremark Merged coremark changes 2022-01-10 05:09:28 +00:00
bin Code cleanup 2022-01-07 04:07:04 +00:00
examples C sum example 2022-01-12 09:04:41 +00:00
fpga Updated debug constraints again to match changes in verilog. 2022-01-08 13:28:51 -06:00
pipelined Hack "fix" to prevent interrupt from occuring during an integer divide. 2022-01-12 14:17:16 -06:00
tests Fixed PMA regions, Added passing PMA tests to regression 2022-01-10 22:08:26 +00:00
.gitattributes Renamed wally-pipelined to pipelined 2022-01-04 19:47:41 +00:00
.gitignore Renamed wally-pipelined to pipelined 2022-01-04 19:47:41 +00:00
.gitmodules Added C test cases 2022-01-11 21:01:48 +00:00
LICENSE Initial Checkin 2021-01-14 23:37:51 -05:00
Makefile Renamed wally-pipelined to pipelined 2022-01-04 19:47:41 +00:00
README.md Update README.md 2022-01-05 11:29:54 -08:00
setup.sh Code cleanup 2022-01-07 04:07:04 +00:00
wallyVirtIO.patch added wallyVirtIO.patch from Ross 2021-12-22 07:04:47 -08:00

README.md

riscv-wally

Configurable RISC-V Processor

Wally is a 5-stage pipelined processor configurable to support all the standard RISC-V options, incluidng RV32/64, A, C, F, D, and M extensions, FENCE.I, and the various privileged modes and CSRs. It is written in SystemVerilog. It passes the RISC-V Arch Tests and Imperas tests. As of October 2021, it boots the first 10 million instructions of Buildroot Linux.

See Chapter 2 of draft book of how to install and compile tests.