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Author	SHA1	Message	Date
Kip Macsai-Goren	8a8f903342	updated tests to make correctly with output verification	2022-01-05 21:43:15 +00:00
Kip Macsai-Goren	706c95a383	allowed option for tests to make without spike simulation. added postverify back in for outputs	2022-01-05 21:17:54 +00:00
Kip Macsai-Goren	1db58744b0	updated pma tests to match simpler test library. They don't pass regression yet	2022-01-05 21:13:40 +00:00
Kip Macsai-Goren	cc47b419be	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-01-05 20:17:52 +00:00
Ross Thompson	0310df96a4	Changes to wave file.	2022-01-05 14:16:59 -06:00
Ross Thompson	7086a0ed08	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-01-05 14:15:27 -06:00
Ross Thompson	cc51a27a34	Fixed bug with flush dirty not cleared in the correct cache line.	2022-01-05 14:14:01 -06:00
davidharrishmc	d0d9f73794	Update README.md	2022-01-05 11:29:54 -08:00
Kip Macsai-Goren	b53ab27b26	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-01-05 18:38:29 +00:00
James E. Stine	edbaff4ea3	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-01-05 10:44:28 -06:00
James E. Stine	962e7dc782	Add script to generate memfile using elf2hex	2022-01-05 10:44:01 -06:00
David Harris	d17a305538	Finished removing generate statements	2022-01-05 16:41:17 +00:00
David Harris	6d4714651c	Removed more generate statements	2022-01-05 16:25:08 +00:00
David Harris	da5ead23bf	Removed more generate statements	2022-01-05 16:01:03 +00:00
David Harris	d66f7c841b	Removed generate statements	2022-01-05 14:35:25 +00:00
Ross Thompson	98be8201b2	Renamed most signals inside cache.sv so they are agnostic to i or d.	2022-01-04 23:52:42 -06:00
Ross Thompson	fffaf654e6	the i and d caches now share common verilog.	2022-01-04 23:40:37 -06:00
Ross Thompson	13dbf3cc0f	parameterized the caches with the goal of using common rtl for both i and d caches.	2022-01-04 22:40:51 -06:00
Ross Thompson	888a60d8d6	Switched block for line in caches.	2022-01-04 22:08:18 -06:00
Ross Thompson	cb301a78ad	Fixed bug where last line of dcache was not written back to memory on dcache flush.	2022-01-04 21:55:48 -06:00
Ross Thompson	101a8bdb5b	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-01-04 18:41:52 -06:00
Ross Thompson	ecc7bf5237	Fixed dcache flush.	2022-01-04 18:40:58 -06:00
David Harris	9ddc6db0a6	Removed imperas mmu tests; using wallypriv instead	2022-01-04 23:14:53 +00:00
Kip Macsai-Goren	04bcf5ef38	cleaned up Imperas tests to pass make	2022-01-04 21:32:21 +00:00
Kip Macsai-Goren	c65fc4d5e6	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-01-04 21:30:51 +00:00
Kip Macsai-Goren	46b0cb810d	fixed arch tests to pass make, added 32 bit tests, addded all make-passing tests to tests.vh.	2022-01-04 21:30:38 +00:00
David Harris	0a7ec3e58d	Fixed bad address for F/fmsub_b18-01	2022-01-04 21:04:06 +00:00
Kip Macsai-Goren	5218533ddc	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-01-04 20:58:08 +00:00
David Harris	d1a7416028	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-01-04 19:47:51 +00:00
David Harris	115287adc8	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00
Kip Macsai-Goren	3a1f2befb1	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-01-04 18:16:46 +00:00
Ross Thompson	f84200fee4	Added mmu tests to regression-wally. ... imperas64mmu passes but imperas32mmu does not.	2022-01-04 11:13:36 -06:00
Ross Thompson	4fa19ae4c5	Modified dcache to ensure nontranslated index is used.	2022-01-04 10:53:53 -06:00
Kip Macsai-Goren	ac3bdc271f	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-01-04 06:38:28 +00:00
Ross Thompson	63fb70fa61	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-01-03 23:49:28 -06:00
Ross Thompson	105763d938	Fixed icache stalling cpu when doing an uncached operation.	2022-01-03 23:49:19 -06:00
Kip Macsai-Goren	a763c37959	update 64 bit tests to make make work correctly and general cleanup	2022-01-04 05:02:33 +00:00
Kip Macsai-Goren	03e26f29a4	Update 32 bit memory tests to make make work correcttly and generally cleanup	2022-01-04 04:59:47 +00:00
Kip Macsai-Goren	e13c050fa1	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-01-04 04:55:36 +00:00
Ross Thompson	2d1cb0c3a3	Reordered inputs/outputs in caches.	2022-01-03 22:52:50 -06:00
Ross Thompson	ff24718c28	Added generate around the spill logic so it is only used if supporting compressed instructions.	2022-01-03 22:23:04 -06:00
Ross Thompson	120a9d6a58	Minor improvement to icache.	2022-01-03 22:00:35 -06:00
Ross Thompson	89f4b920ff	More Icache clean up.	2022-01-03 21:22:34 -06:00
Ross Thompson	2f7cb82c72	Major icache cleanup.	2022-01-03 21:12:17 -06:00
Ross Thompson	b045d84147	Removed spill support from icache.	2022-01-03 21:03:02 -06:00
Ross Thompson	8c7638688b	The ifu now directly supports compressed without the icache providing the implemenation. ... The icache still constains all the orignal muxing logic to handle spills. This should be removed.	2022-01-03 20:49:47 -06:00
Ross Thompson	324362eee5	Almost working compressed instructions with compressed detection and processing in ifu rather than icache.	2022-01-03 18:10:15 -06:00
Ross Thompson	82fbc502e0	Prepared the ifu and icache for moving spills to ifu.	2022-01-03 17:09:36 -06:00
Ross Thompson	d77ddd2cbf	Fixed bug with the icache.	2022-01-03 15:55:19 -06:00
Ross Thompson	c501276067	Fixed a bug where the instruction fetch got out of sync with the icache.	2022-01-03 13:27:15 -06:00