Rose Thompson
70d0169019
All regression tests which matter are running!
2023-12-20 14:57:52 -06:00
Rose Thompson
1b59182d59
Updated tests with ending label.
2023-12-20 14:55:37 -06:00
Rose Thompson
b68dd74f89
Reverted logic to bit change.
2023-12-20 13:16:32 -06:00
Rose Thompson
f52ad13a65
Merge branch 'fix'
2023-12-20 13:10:30 -06:00
Rose Thompson
18a96740d5
Revert RAM logic to bit change.
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Added logic to hptw to prevent x propagation.
2023-12-20 13:10:20 -06:00
Rose Thompson
a8ab3c8342
Ok that is a stange bug.
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The testbench used logic for the shadow ram, but the memory used bit. This caused questa to allocate huge amounts of memory and crash. Changing shadow ram to bit fixed the issue.
2023-12-20 12:25:34 -06:00
Rose Thompson
9de434a61b
"Resolved" ram preload issues by replacing the RAM's types with bit from logic. Tested fpga synthesis.
2023-12-20 12:05:25 -06:00
Rose Thompson
9ee1ffe8fe
Almost working with modelsim and verilator.
2023-12-20 11:29:31 -06:00
Rose Thompson
d617eb0977
DON'T keep this commit.
2023-12-19 16:56:40 -06:00
Rose Thompson
49b1b7c7f9
Fixed the last uninitialized memory issue in the priv tests.
2023-12-19 16:51:56 -06:00
Rose Thompson
b04ad23c33
Fixed bugs in the wally64periph signature.
2023-12-19 16:16:59 -06:00
Rose Thompson
726efee1e2
Fixed bugs in the cbom test.
2023-12-19 15:53:48 -06:00
Rose Thompson
418ae0decc
Fixed some regression tests with David's help.
2023-12-19 14:18:21 -06:00
Rose Thompson
4f59bd492d
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-12-19 12:06:04 -06:00
Rose Thompson
2e792606dd
More progress. Most tests are passing in modelsim.
2023-12-19 12:06:00 -06:00
Rose Thompson
74238defc3
Progress.
2023-12-18 20:23:19 -06:00
David Harris
6186181d46
Merge pull request #537 from ross144/main
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Almost having working Verilator. One issue in the testbench remains.
2023-12-18 18:13:56 -08:00
Rose Thompson
1e1759c258
Restored the one hack change which prevents verilator from working.
2023-12-18 17:00:53 -06:00
Rose Thompson
408bb2c35b
Yay! I got verilator to compile our testbench! Does it actually work I don't know.
2023-12-18 16:44:34 -06:00
Rose Thompson
0f7b6ada04
Cleanup.
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Verilator still has issues with riscassertions.sv and the testbench
2023-12-18 16:38:56 -06:00
Rose Thompson
b7b245fe2f
functionName.sv is now linting for rv64gc.
2023-12-18 16:37:26 -06:00
Rose Thompson
c1ac153a4f
Closer to verilator support.
2023-12-18 16:26:56 -06:00
Rose Thompson
58942b246b
Kind of a frustrating set of changes to get the verilator errors out of the copyShadow module.
2023-12-18 13:34:14 -06:00
Rose Thompson
4a3cc8b9c8
More progress towards verilator.
2023-12-18 13:26:43 -06:00
Rose Thompson
5062a8c89c
Added parameter for cache's SRAM length.
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Progress towards verilator support.
2023-12-18 12:50:49 -06:00
Rose Thompson
1d36ce3328
Fixed lint issue.
2023-12-18 12:03:54 -06:00
Rose Thompson
42d115bc27
Merge pull request #536 from stineje/main
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Fix issue with running all and then going from one operand width to a…
2023-12-17 18:59:47 -08:00
James E. Stine
f4c1713ed4
Fix issue with running all and then going from one operand width to another. Issue is due to signals resolving between sizes. I did not catch it before because I did not run through the complete exhaustive tests. This time, went through all tests and tested all the data sizes.
2023-12-17 20:55:06 -06:00
David Harris
0eed57a0b7
Merge pull request #535 from stineje/main
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fix bad typo on spef integration for tsmc28psyn
2023-12-15 21:13:38 -08:00
James E. Stine
54b0285300
fix bad typo on spef integration for tsmc28psyn
2023-12-15 23:06:05 -06:00
David Harris
d6830a1faa
Merge pull request #534 from stineje/main
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Fix some minor issues but main push is for Issue #507 resolution
2023-12-15 19:23:27 -08:00
David Harris
bbdcfe24ca
Merge pull request #533 from ross144/main
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Finally fixed the store delay hazard bug.
2023-12-15 19:13:53 -08:00
James E. Stine
27a7994847
Modify DC to export spef for DC extraction of parasitics. This file can be used to read in an ancillary tool (e.g., snps PrimeTime) to get more detail on power estimation
2023-12-15 17:21:24 -06:00
James E. Stine
01a246422f
Update bug in wally-tool-chain-install.sh script due to misspelling for an environmental variable. In addition, zlibc was removed due to deprecation
2023-12-15 17:04:37 -06:00
James E. Stine
8d8bad61d4
Fix to take care of Issue #507 . Issue was caused with time delay in testbench-fp.sv that interfered with the if statement in the DIVSQRT condition for generating a vector. This original time delay was given to guarantee that the previous operation would complete. However, the testbench was modified to make sure this would not happen and this time delay is not needed obviating any issue that caused Issue #507 . Some other small enhancements were made to the testbench-fp.sv for beautification, as well. A full test was run on the testbench to check its validity.
2023-12-15 17:02:11 -06:00
Rose Thompson
7693c5d4e2
Updates to fpga top level.
2023-12-15 15:32:05 -06:00
Rose Thompson
26cd22c388
Replaced fpga's verilog top with system verilog.
2023-12-15 13:42:52 -06:00
Rose Thompson
dab9d7ab3c
Replaced fpga top level verilog with system verilog.
2023-12-15 13:07:08 -06:00
Rose Thompson
57f163f103
Merge branch 'main' of github.com:ross144/cvw
2023-12-15 11:59:17 -06:00
Rose Thompson
438451ee02
Fixed the AMO hazard.
2023-12-15 11:55:54 -06:00
Rose Thompson
872b830801
Merge pull request #532 from davidharrishmc/dev
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Lint fix and WALLY-lrsc fix to pass ImperasDV
2023-12-14 15:51:58 -08:00
David Harris
29f57958a9
Fixed WALLY-lrsc in ImperasDV by setting reservation set size to native word size and adjusting imperas.ic lr_sc_grain=8 to match
2023-12-14 15:32:36 -08:00
Rose Thompson
34631c54d3
Get's the fpga building again after the git history rewrite.
2023-12-14 17:08:25 -06:00
David Harris
6fbc2c4ded
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2023-12-14 15:03:00 -08:00
David Harris
8eea2bdcc0
Merge pull request #531 from ross144/main
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Updated wavefile
2023-12-14 14:52:31 -08:00
Rose Thompson
1ca9a8be6d
I think I solved the AMO/store hazard issue introduced by removing the store delay hazard.
2023-12-14 16:31:02 -06:00
Rose Thompson
bb712d6860
Updated wavefile.
2023-12-14 14:36:23 -06:00
Rose Thompson
53bf68a585
Merge pull request #528 from davidharrishmc/dev
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Svnapot bug fix
2023-12-13 21:30:47 -08:00
David Harris
83b3c3b346
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2023-12-13 20:59:59 -08:00
David Harris
aa83a13b34
Merge pull request #527 from ross144/main
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Removed majority of Store Delay Stalls. Still working on cleaning up code, but we should consider reruning benchmarks.
2023-12-13 20:59:53 -08:00
