Ross Thompson
279f5bc615
Cleanup cacheLRU.
2022-11-22 14:59:01 -06:00
Ross Thompson
e1dbe58632
File name change for cachereplacement policy to cacheLRU
2022-11-20 22:35:02 -06:00
Ross Thompson
4e926ba4cf
Signal name changes for LRU.
2022-11-20 22:31:36 -06:00
Ross Thompson
00218d559f
Missing a file. Last commit will fail.
2022-11-17 17:45:41 -06:00
Ross Thompson
0106777f02
Finally have the correct replacement policy implementation.
2022-11-17 17:36:37 -06:00
Ross Thompson
faa13a96e0
I found the issue with the cache changes. FlushW is not asserted for all TrapM. Ecall and Ebreak don't flush the W stage. However the ifu's bus controllable must disable the BusRW for all traps.
2022-11-16 15:38:37 -06:00
Ross Thompson
22ad49eef2
Progress on the cache replacement policy implementation.
2022-11-16 15:35:34 -06:00
Ross Thompson
0796cd92fc
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-11-16 12:42:29 -06:00
Ross Thompson
42111db671
Oups found a bug with my cache changes. I took TrapM out of the logic path for selecting the cache's address CAdr (previously RAdr) to improve the critical path. This is fine for the dcache because both the E and M stages are flushed. However for the ICache only F is flushed. PCNextF is valid and points to XTVEC so the cache must take NextAdr rather than PAdr as CAdr.
2022-11-16 12:36:58 -06:00
David Harris
59335ac70f
comment cleanup
2022-11-16 10:23:20 -08:00
David Harris
be9c618c94
Renamed DivBusy to FDivBusyE in FPU
2022-11-16 10:13:27 -08:00
David Harris
128cc86254
Moved DivStartE to fdivsqrtfsm
2022-11-16 10:00:07 -08:00
Ross Thompson
1f21a2bab1
Created improved cache replacement policy implementation. This version is generic and works for any number of ways. Not fully tested and is currently commented out.
2022-11-16 11:15:34 -06:00
cturek
ffd03e9548
Attempt to fix FPGA synth errors
2022-11-15 20:34:28 +00:00
cturek
98b66aab9f
Fixed lint errors in postprocessing
2022-11-15 20:31:23 +00:00
Ross Thompson
3df51716b1
Fixed a bug with the hptw configuration not correctly avoiding UPDATE_PTE state.
2022-11-14 16:02:20 -06:00
Ross Thompson
b53f8eceef
Renamed Flush to FlushStage in the cache.
2022-11-14 14:11:05 -06:00
Ross Thompson
284b97aff6
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-11-14 13:48:56 -06:00
David Harris
6372139af4
Removed comment about nonexistent possible bug
2022-11-14 09:56:33 -08:00
David Harris
06dbed92c8
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-11-14 09:52:24 -08:00
David Harris
f9202187ba
Removed comment about nonexistent possible bug
2022-11-14 09:52:21 -08:00
Ross Thompson
13e6f7d80b
Changed names of cache signals.
2022-11-13 21:36:12 -06:00
Ross Thompson
788ae5fb18
Updated wave file.
2022-11-13 21:34:45 -06:00
cturek
abaa33b92a
Added majority of combinational logic
2022-11-14 00:06:38 +00:00
cturek
6740d77b63
Added Quotient/Remainder calcs to normal termination
2022-11-13 23:44:34 +00:00
cturek
12e3646153
Added flops for n and m, added B=0 signal
2022-11-13 23:02:43 +00:00
cturek
f10700e666
Added A<B signal to fdivsqrt, started postprocessing merge
2022-11-13 22:40:26 +00:00
Ross Thompson
9d7ba19fe1
Changed IMWriteDataM to IHWriteDataM.
2022-11-13 12:27:48 -06:00
Ross Thompson
421c6f9c48
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
...
hazard was not a straight forward merge. I changed the way the LSU and IFU generate IFUStallF and LSUStallM. They need to be suppressed by TrapM now.
2022-11-13 12:25:22 -06:00
David Harris
84c4558641
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-11-13 04:23:26 -08:00
David Harris
879e62912b
HPTW cleanup
2022-11-13 04:23:23 -08:00
David Harris
2ebdfa3f68
Comments about division hazards
2022-11-13 04:17:37 -08:00
Ross Thompson
54544ae251
Moved all remaining bus logic from the LSU into ahbcacheinterface.
2022-11-11 14:30:32 -06:00
cturek
4a8661649c
Added integer step counter to fsm
2022-11-11 00:23:25 +00:00
Ross Thompson
c028306ba3
Fixed name change in hptw.
2022-11-10 16:13:31 -06:00
Ross Thompson
d912981ec9
Wavefile update.
2022-11-10 15:48:06 -06:00
Ross Thompson
40367eaf45
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-11-10 15:46:25 -06:00
Ross Thompson
8658a25218
Renamed Word to Beat for ahbcacheinterface.
2022-11-09 17:52:50 -06:00
Ross Thompson
028e2b0f91
Renamed CACHE_EVICT to CACHE_WRITEBACK.
2022-11-09 17:43:06 -06:00
cturek
9d30a832c3
Reoredered tests for arch32m
2022-11-09 18:42:00 +00:00
cturek
b723e16893
Fixed asign and bsign
2022-11-09 18:41:26 +00:00
Ross Thompson
be8e0eee1b
Removed TrapM from the LSU and IFU. TrapM is replaced with FlushW for both. (Don't like this for the IFU).
...
FlushW prevents writting the cache, dtim, and bus state. FlushW still gates HTRANS.
FlushW does not impact the mealy outputs of the cache and bus FSMs and hazard is updated to
not stall W if we get a trap.
2022-11-07 15:50:55 -06:00
David Harris
f7b94c12fc
Moved lsuvirtmem muxes into hptw
2022-11-07 11:13:34 -08:00
Ross Thompson
d4f4950d2c
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-11-07 09:10:51 -06:00
cturek
d571b5f9a5
propagated otfc swap to Rad2 and 4 qslc
2022-11-06 23:32:38 +00:00
Ross Thompson
e7d24609cd
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-11-06 17:22:25 -06:00
cturek
54f09f3616
Added conditional OTFC swap for simplified int postprocessing
2022-11-06 23:09:09 +00:00
cturek
c3e635c788
Finished Int Preprocessinggit add ../src/fpu/fdivsqrt/fdivsqrtpreproc.sv
2022-11-06 22:40:21 +00:00
cturek
a49ea2a16d
Added n and rightshiftx
2022-11-06 22:31:48 +00:00
cturek
350d4d254f
p calculation
2022-11-06 22:24:21 +00:00
cturek
83051a5351
Changed lzc names, started int/fp size merge in preproc
2022-11-06 22:21:35 +00:00
cturek
2cbe2fd70b
Added n, p, and m signals between fdivsqrt submodules. Added w64 and mdue to divsqrt testbench.
2022-11-06 22:08:18 +00:00
cturek
6bc4c1318e
Added new macros for int div preprocessing, added p, n, and rightshiftx logic
2022-11-06 21:53:48 +00:00
David Harris
53a88fec8f
Reorder embench tests to prevent crash
2022-11-04 15:21:51 -07:00
David Harris
60cfa0d69c
HPTW cleanup
2022-11-04 15:21:09 -07:00
Ross Thompson
44ee31a7f6
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-11-04 13:30:08 -05:00
cturek
06a9305766
renamed remOp to RemOp
2022-11-03 22:37:25 +00:00
cturek
e37f564e84
Added rem/div operation to postprocessor
2022-11-02 17:49:40 +00:00
Ross Thompson
44171c342d
Reduced complexity of logic supressing cache operations.
2022-11-01 15:23:24 -05:00
cturek
e8d7607e87
Added buffered signals for int/fp
2022-10-28 21:47:24 +00:00
cturek
9f41e57f03
Config Cleanup
2022-10-27 22:38:56 +00:00
Ross Thompson
dc3a9f2342
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-10-26 14:48:50 -05:00
Ross Thompson
403434580d
Fixed the uart transmit fifo overrun bug.
2022-10-26 14:48:09 -05:00
cturek
7301fc7f18
small signal cleanup
2022-10-26 18:42:49 +00:00
cturek
6caf7bb7e2
abs for int inputs
2022-10-26 16:18:05 +00:00
cturek
ec4646b412
Added signed division to fdivsqrt
2022-10-26 16:13:41 +00:00
cturek
71d16eacef
unbroke DIVb
2022-10-26 16:11:51 +00:00
cturek
1febdb75b7
Config cleanup
2022-10-25 21:04:09 +00:00
Jacob Pease
160ca366c8
Added PLIC signals for debugging on FPGA.
2022-10-25 13:57:09 -05:00
cturek
ff7d6b2932
Started Integer Preprocessing
2022-10-25 17:48:43 +00:00
Ross Thompson
9ba487c323
Setup to run with both the vcu108 and vcu118 boards. Set the parameters in the Makefile.
2022-10-24 15:38:39 -05:00
Ross Thompson
7244ca1e7b
Bit width error.
2022-10-24 13:48:47 -05:00
Ross Thompson
51408c620e
Found a way to remove the interlock fsm. Dramatically reducing the complexity of virtual memory and page table walks.
2022-10-23 13:46:50 -05:00
Ross Thompson
775309165b
Small cleanup of interlockfsm.
2022-10-22 16:29:51 -05:00
Ross Thompson
a59df0c77d
Created one off test to replicate the floating point forwarding hazard bug.
2022-10-22 16:29:12 -05:00
Ross Thompson
6696624971
comment updates.
2022-10-22 16:28:44 -05:00
Ross Thompson
12c5525807
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-10-22 16:27:30 -05:00
Ross Thompson
4db912678d
Changed FDivBusyE to stall the whole pipeline. Any instruction in the Executation which depended on the output of an instruction in the writeback stage would be lost if the back end of the pipelined advanced. The solution is to stall the whole pipeline.
2022-10-22 16:27:20 -05:00
Jacob Pease
b1170ec7a2
Extended rxfifotimeout count to actually be 4 characters long.
2022-10-20 17:35:49 -05:00
Ross Thompson
2c5847b01f
Moving interlockfsm changes to a temporary branch.
...
reduced complexity of cache mux controls.
2022-10-19 15:08:23 -05:00
Ross Thompson
9cadd4c6ec
Broken don't use this state.
2022-10-19 14:31:22 -05:00
Ross Thompson
c6a9b17918
Noted possible bug with endianness during hptw.
...
Minor complexity reduction in interlockfsm. I think there is a lot of room to simplify.
2022-10-19 12:20:19 -05:00
Ross Thompson
a53ca5c99f
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-10-19 10:42:31 -05:00
Ross Thompson
d6f907f444
Sort of solved the bit width warning for dtim, irom ranges.
2022-10-19 10:42:19 -05:00
Ross Thompson
d4c5440f25
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-10-18 15:06:09 -05:00
Ross Thompson
92accfb1a6
Updated uart settings and fpga wave config.
2022-10-18 15:05:33 -05:00
Ross Thompson
47608df73e
Possible fix for interrupt during a floating point divide.
2022-10-18 15:04:21 -05:00
Ross Thompson
65c2fe294a
Merged cacheable with seluncachedadr.
2022-10-17 13:29:21 -05:00
David Harris
aa5fe52407
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-10-14 17:33:36 -07:00
David Harris
51b702fa17
Removed unused FPU waves
2022-10-14 17:33:32 -07:00
amaiuolo
56455bb9ad
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
2022-10-13 22:36:57 +00:00
amaiuolo
1ae48e0edc
added amaiuolo@hmc.edu
2022-10-13 22:36:52 +00:00
Ross Thompson
22603464ae
Fixed uncached read bug introduced by yesterday's changes.
2022-10-13 11:11:36 -05:00
Ross Thompson
a4390dd07f
Fixed LSU to correctly handle the difference between LLEN and AHBW.
2022-10-12 12:06:15 -05:00
Ross Thompson
b79872180b
Actually fixed the bus width issue coming out of the cache.
...
The root cause is the ahb bus width can be different from LLEN.
If we switch the d-cache to outputing LLEN and on LLEN intervals, subword read needs to operate on LLEN as well.
Then the cache always outputs LLEN data which may need to be muxed down into 2 or more subwords if ABHW is smaller than LLEN.
2022-10-12 11:33:10 -05:00
Kip Macsai-Goren
1dd9cb6697
quick fix to endianness wapping 64 bit reads in 32 bit confgs
2022-10-11 23:08:02 +00:00
Ross Thompson
7ddcf38fa9
Modified LSU to support DTIM without CSRs.
2022-10-11 14:05:20 -05:00
Ross Thompson
77de96905a
Fixed first problem with the rv64i IROM.
2022-10-11 11:35:40 -05:00
Ross Thompson
dfd07a57fd
Modified the do scripts to change the DTIM_RANGE and IROM_RANGE to large values from the defaults.
...
The defaults are used for synthesis.
rv64i and rv32i: DTIM 2KiB, IROM 2KiB
rv32ic: DTIM 4KiB, IROM 16KiB
Regression tests require 8MiB or larger so modelsim overrides.
2022-10-11 10:47:13 -05:00
David Harris
cc9a2fc62d
Removed imperas tests from rv32i/rv64i because the configs lack privileged support expected in the tests. Also cleaned up comment in LSU
2022-10-10 10:22:12 -07:00
David Harris
31e9af0eb2
Made simple RV64 configuration be RV64i. Eliminated rv64ic and rv64fp. Fixed some bugs related to new width
2022-10-10 09:10:55 -07:00
David Harris
fde4832642
Removed unnecessary configuration conditions from subwordread sign extension/NaN boxing
2022-10-10 07:12:37 -07:00
Ross Thompson
4bf5245f75
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-10-09 16:46:51 -05:00
Ross Thompson
9d23b0e6d6
Reorganized the configs.
2022-10-09 16:46:48 -05:00
David Harris
04dc0ac02c
New fdivsqrtqsel4cmp module based on comparators rather than table lookup
2022-10-09 04:47:44 -07:00
David Harris
4f312ea2e7
Moved shift into divsqrt stage and cleaned up comments
2022-10-09 04:45:45 -07:00
David Harris
2aa43848f5
fdivsqrt code cleanup
2022-10-09 03:37:27 -07:00
Ross Thompson
6ff4abd4f7
Cleaned up the new muxes to select between IROM/ICACHE/BUS and DTIM/DCACHE/BUS.
2022-10-05 15:46:53 -05:00
Ross Thompson
28584e4cca
Fixed wally32e.
2022-10-05 15:37:01 -05:00
Ross Thompson
52a1d3dafe
Name clarifications.
2022-10-05 15:36:56 -05:00
Ross Thompson
aa09b1ef16
Fixed bug with combined dtim+bus.
2022-10-05 15:16:01 -05:00
Ross Thompson
98521d073f
Possibly have working dtim + bus config.
2022-10-05 15:08:20 -05:00
Ross Thompson
b01ee070bd
Updated wavefile.
2022-10-05 14:55:40 -05:00
Ross Thompson
bf6f0e7219
Fixed bug in EBU.
2022-10-05 14:51:12 -05:00
Ross Thompson
cabcb5e89e
Modified the LSU and IFU to allow concurrent DTIM/DCACHE+BUS and IROM/ICACHE+BUS.
...
Don't use this commit as the rv32i tests are not passing.
2022-10-05 14:51:02 -05:00
Ross Thompson
5e09d1cca7
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-10-05 14:03:44 -05:00
David Harris
29033dc334
Changed RV32i config to use DTIM and bus. Don't use this commit - it will break rv32i tests.
2022-10-05 11:46:52 -07:00
Ross Thompson
ea70e1c598
Optimized the ebu's beat counting.
2022-10-05 10:58:23 -05:00
Ross Thompson
294645a49f
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-10-04 17:38:49 -05:00
Ross Thompson
494f8b94f4
Reordered the eviction and fetch in cache so it follows a more logical order.
2022-10-04 17:36:07 -05:00
Ross Thompson
18e739befc
Modified cache lru to not have the delayed write.
2022-10-04 15:14:58 -05:00
Kip Macsai-Goren
c18c181fc0
fixed endianness mstatush problem, passes make, not regression
2022-10-04 17:37:39 +00:00
Kip Macsai-Goren
3f6d05f7a2
addded renamed file
2022-10-04 17:37:05 +00:00
Kip Macsai-Goren
9a0b98037b
Merge branch 'main' of github.com:davidharrishmc/riscv-wally
2022-10-04 17:33:54 +00:00
Kip Macsai-Goren
fb464b9546
Renamed endianswap to match module name
2022-10-04 17:33:49 +00:00
Ross Thompson
0ed0c18aa1
Fixed a very subtle bug in the trap handler. It was possible to select the wrong cause if an interrupt was pending, but it was supressed by Committed and another exception triggered.
2022-10-02 16:21:21 -05:00
Ross Thompson
d08c29e3c5
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-10-01 15:01:22 -05:00
Ross Thompson
41ab4850e1
Disable IFU bus access on TrapM.
2022-10-01 14:54:16 -05:00
Ross Thompson
e27fcb1577
Added logic to not implement the save/restore muxes for LSU in the EBU's controller input stage.
2022-09-29 18:37:34 -05:00
David Harris
657f16dfd1
Adding start signals for integer divider to fdivsqrt
2022-09-29 16:30:25 -07:00
Ross Thompson
2c0132aa9c
Renamed signals in EBU.
2022-09-29 18:29:38 -05:00
cturek
e8a869e0e7
Added integer inputs and flags to divsqrt
2022-09-29 23:08:27 +00:00
Ross Thompson
58d597b614
Simplification to EBU.
2022-09-29 18:06:34 -05:00
Ross Thompson
d81af3bca8
Fixed HTRANS not changing after accepting HREADY. This exposed a bug in uncore.
2022-09-29 11:54:03 -05:00
Ross Thompson
32449dfe97
Hmm. the icache and ifu didn't have a CommittedF signals going back to the privileged unit. They probably should. If an interrupt occurred during the middle of an instruction fetch icache miss I think it would corrupt the icache.
2022-09-28 17:39:51 -05:00
Ross Thompson
4db017dac3
Possible fix for ifu/lsu arbiration issue.
2022-09-27 17:24:35 -05:00
Ross Thompson
4062fe56c0
Possible fix to the bus cache interaction.
2022-09-27 11:34:33 -05:00
Ross Thompson
07bb11518e
Found a hidden bug in the cache to bus fsm interlock.
2022-09-26 17:41:30 -05:00
Ross Thompson
996c4ca8f2
renamed ahbmulticontroller to ebu.
2022-09-26 14:37:18 -05:00
Ross Thompson
8ed173a5f5
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-09-26 12:49:16 -05:00
Ross Thompson
0fcc314d06
Yesterday David and I found what is likely a bug in our AHB implementation. HTRANS was getting reset to 2 rather than 0 at the end of a burst transaction. This is fixed.
2022-09-26 12:48:26 -05:00
David Harris
713df785d1
changed always_ff to always in sram1p1rw to fix testbench complaint
2022-09-25 19:56:40 -07:00
Ross Thompson
38edbde966
Renamed RW signals through the caches, bus interfaces, and IFU/LSU.
...
CPU to $ is called LSURWM or IFURWF.
CPU to Bus is called BusRW
$ to Bus is called CacheBusRW.
2022-09-23 11:46:53 -05:00
Ross Thompson
2eaf3af6c7
Removed the write first sram model.
2022-09-22 16:12:08 -05:00
Ross Thompson
cec50ce208
The valid and dirty bits match the SRAM implementation now.
2022-09-22 16:09:09 -05:00
Ross Thompson
b48d6b5e1f
Solved the sram write first / read first issue. Works correctly with read first now.
2022-09-22 14:16:26 -05:00
Ross Thompson
89e6ddfa4e
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-09-21 18:24:06 -05:00
Ross Thompson
99e01dd31f
Cleaned up the IFU and LSU around dtim and irom address calculation.
2022-09-21 18:23:56 -05:00
David Harris
d6297a2f2e
For radix 4 division, fixed initial C and then could remove unexplained shift from divshiftcalc
2022-09-21 13:30:35 -07:00
David Harris
e49e99548a
Fixed testbench-fp to support all again
2022-09-21 13:19:48 -07:00
