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504 Commits

Author SHA1 Message Date
bbracker
76f50d7a69 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-04-15 09:06:03 -04:00
bbracker
da22308e60 csri lint improvement 2021-04-15 09:05:53 -04:00
Thomas Fleming
d281ecd067 Remove imem from testbenches 2021-04-14 20:20:34 -04:00
bbracker
ccff1e6c99 rv64 interrupt servicing 2021-04-14 10:19:42 -04:00
Noah Boorstin
3e0ed5a2b1 busybear: use (slightly) less terrible verilog 2021-04-14 00:18:44 -04:00
Noah Boorstin
18a4d5fc8d busybear testbench updates 
start speculative checking on CSR* satp, *
add some slight delays in some CSR checkings to make them deterministic

I realize this verilog is incredibly un-idiomatic. But I still don't
know of anything better. If you figure it out, please let me know
 2021-04-14 00:00:27 -04:00
Thomas Fleming
bb2d433971 Fix mmu lint errors 2021-04-13 19:19:58 -04:00
Thomas Fleming
a545dcb9ae Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-04-13 17:15:10 -04:00
Katherine Parry
e075dc2d13 Various bugs fixed in FMA 2021-04-13 18:27:13 +00:00
Thomas Fleming
ae888b5705 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 
Conflicts:
	wally-pipelined/src/ebu/pagetablewalker.sv
 2021-04-13 13:42:03 -04:00
Thomas Fleming
f0c926cf68 Move InstrPageFault to fetch stage 2021-04-13 13:39:22 -04:00
Thomas Fleming
08a84048b6 Add lru algorithm to TLB 2021-04-13 13:37:24 -04:00
Teo Ene
0bffac2c74 Various code syntax changes to bring HDL to a synthesizable level 2021-04-13 11:27:12 -05:00
Ross Thompson
cb52820249 Fixed minor bug in muldiv which corrects the lint error. 2021-04-09 10:56:31 -05:00
ushakya22
c8c2d63163 Latest IE tests with timer interupts 2021-04-08 17:53:39 -04:00
bbracker
0c85b1c201 integrated peripheral testing into existing workflow 2021-04-08 15:31:39 -04:00
bbracker
37bca569ff Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-04-08 14:28:25 -04:00
bbracker
c8c87bd0d8 merge testbench 2021-04-08 14:28:01 -04:00
Katherine Parry
6e4a22ec4b Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-04-08 18:06:51 +00:00
David Harris
5b262159cd Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-04-08 14:04:09 -04:00
David Harris
2a7dd37441 restored testbench-imperas.sv 2021-04-08 14:04:01 -04:00
Katherine Parry
21efd0cad9 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-04-08 18:03:57 +00:00
Katherine Parry
08f45eb076 fixed FPU lint warnings 2021-04-08 18:03:21 +00:00
Katherine Parry
ebf4915440 fixed FPU lint warnings 2021-04-08 17:55:25 +00:00
ushakya22
6dc982285c Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-04-08 13:55:23 -04:00
ushakya22
0dfeb76f10 Updates to WALLY-IE tests 2021-04-08 13:54:42 -04:00
David Harris
2203e64b65 merge conflict resolution 2021-04-08 13:53:56 -04:00
David Harris
aabebdb59f fixed sim-wally-32ic 2021-04-08 13:40:16 -04:00
Noah Boorstin
5f1cd43033 try to remove git-lfs stuff 2021-04-08 13:23:11 -04:00
Domenico Ottolia
d6949b5b81 Update privileged testgen & helper script 2021-04-08 05:14:07 -04:00
Domenico Ottolia
1bdfac6a77 Cause an Illegal Instruction Exception when attempting to write readonly CSRs 2021-04-08 05:12:54 -04:00
Thomas Fleming
bd310a55af Refactor TLB into multiple files 2021-04-08 03:24:10 -04:00
Thomas Fleming
b3795cef2e Provide attribution link for priority encoder 2021-04-08 03:05:06 -04:00
Thomas Fleming
e807f5d771 Implement support for superpages 2021-04-08 02:44:59 -04:00
ushakya22
7888eacc3f MIE privilege tests with working timer interupt 2021-04-07 04:09:09 -04:00
Domenico Ottolia
9b82fbff5a Add privileged tests to testbench 2021-04-07 02:22:08 -04:00
Domenico Ottolia
bbdd4e1467 Add passing mtval and mepc tests 2021-04-07 02:21:05 -04:00
Noah Boorstin
c820910b29 add busybear boot files with git-lfs 2021-04-05 19:38:43 -04:00
Noah Boorstin
ce22a1de04 busybear: reenable 'ruthless' CSR checking 2021-04-05 12:53:30 -04:00
bbracker
80a67dc906 declare memread signal 2021-04-05 08:13:01 -04:00
bbracker
eca92041e9 PLIC claim reg side effects now check for memread signal 2021-04-05 08:03:14 -04:00
bbracker
8f4da826fb plic subword access compliance 2021-04-04 23:10:33 -04:00
Katherine Parry
f41b5a2d38 Added missing files in FPU 2021-04-04 18:09:13 +00:00
bbracker
ce7b2314ef Yee hoo first draft of PLIC plus self-checking tests 2021-04-04 06:40:53 -04:00
Thomas Fleming
5946b860ca Comment out fpu from hart until module exists 2021-04-03 22:34:11 -04:00
Thomas Fleming
8f31e00f6a Merge branch 'mmu' into main 
Conflicts:
	wally-pipelined/src/wally/wallypipelinedhart.sv
 2021-04-03 22:12:52 -04:00
Thomas Fleming
ac89947e98 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-04-03 22:09:50 -04:00
Noah Boorstin
2f503ee6b9 busybear: temporary stop after 800k instrs 2021-04-03 21:37:57 -04:00
Thomas Fleming
e04ad8f304 Fix extraneous page fault stall 2021-04-03 21:28:24 -04:00
Katherine Parry
08b31f7b2a Integrated FPU 2021-04-03 20:52:26 +00:00
Ross Thompson
a743acd1fd Partial fix to the integer divide stall issue. 2021-04-02 15:32:15 -05:00
James E. Stine
e38e7aff8e Minor cleanup 2021-04-02 08:20:44 -05:00
James E. Stine
82cd900b65 Put back imperas testbench until figure out why m_supported is running for rv64ic 2021-04-02 08:19:25 -05:00
James E. Stine
9026357350 Added some updates to divider - still not working all the time. Still a bug with signals within muldiv - specificaly MultDivE being modified during Execute stage. Seems to be triggered by ahblite signal. 2021-04-02 06:27:37 -05:00
Thomas Fleming
14cf331265 Merge branch 'main' into mmu 2021-04-01 16:29:39 -04:00
Thomas Fleming
06032936bd Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-04-01 16:24:06 -04:00
Thomas Fleming
3f3d8f414d Merge branch 'mmu' of github.com:davidharrishmc/riscv-wally into mmu 2021-04-01 16:23:19 -04:00
Thomas Fleming
f9bf2fbc01 Implement sfence.vma and fix tlb writing 2021-04-01 15:55:05 -04:00
James E. Stine
59dee5580c Fixed some divide -still bug in AHB causing InstStall to deassert and next instruction to get into divide unit. Hope to fix soon. Divide seems to work if given enough time. 2021-04-01 12:30:37 -05:00
Teo Ene
6aed8eaea1 Updated MISA in coremark_bare config file 2021-03-31 20:39:02 -05:00
Noah Boorstin
4e62c7d5f5 busybear: temporarially stop checking CSRs 2021-03-31 14:14:32 -04:00
Noah Boorstin
679daeedf5 busybear: clean up questa warnings 2021-03-31 14:04:57 -04:00
Noah Boorstin
ddc56d8cd7 busybear: clean up questa warnings 2021-03-31 14:02:15 -04:00
Thomas Fleming
9388a9f28a Disable 'always-on' virtual memory 2021-03-30 22:49:47 -04:00
Thomas Fleming
e35020b7dc Extend lint-wally to lint both rv32 and rv64 2021-03-30 22:42:28 -04:00
Thomas Fleming
e3d548d452 Merge remote-tracking branch 'origin/main' into main 
Bring icache and MMU code together

Conflicts:
	wally-pipelined/src/ifu/ifu.sv
	wally-pipelined/testbench/testbench-imperas.sv
 2021-03-30 22:24:47 -04:00
Thomas Fleming
4b2765f8e2 Complete basic page table walker 2021-03-30 22:19:27 -04:00
Thomas Fleming
7f7cc73dd3 Update virtual memory tests and move to separate folder 2021-03-30 22:18:29 -04:00
Domenico Ottolia
d0a78b15b7 Add one more test to WALLY-CAUSE, and update privileged testgen 2021-03-30 19:44:58 -04:00
Domenico Ottolia
8c7e247b58 Add mcause tests to testbench 2021-03-30 17:17:59 -04:00
Domenico Ottolia
ae7868b166 Update privileged tests generator 2021-03-30 16:58:46 -04:00
Domenico Ottolia
47648dc721 Add all working mcause tests 2021-03-30 16:55:12 -04:00
ushakya22
ba01d57767 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-30 15:25:07 -04:00
ushakya22
2b99a7657a privilege tests 2021-03-30 15:23:47 -04:00
David Harris
9f0a58e193 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-26 13:04:52 -04:00
David Harris
aa0d0d50d8 Added fp test to testbench 2021-03-26 13:03:23 -04:00
Shreya Sanghai
edaf89e3d1 Merge branch 'PPA' into main 
Conflicts:
	wally-pipelined/testbench/testbench-privileged.sv
 2021-03-25 20:35:21 -04:00
Shreya Sanghai
d3e914f64b removed minor bugs 2021-03-25 20:29:50 -04:00
ShreyaSanghai
da4086db79 Removed PCW and InstrW from ifu 2021-03-26 01:53:19 +05:30
Noah Boorstin
ee3a53de7a regression: use busybear batch instead 2021-03-25 15:34:10 -04:00
Domenico Ottolia
9e9fe5e9d3 More bug fixes for privileged tests 2021-03-25 15:05:55 -04:00
Brett Mathis
aedc96cd04 FPU Pipeline completed - can begin integration 2021-03-25 13:29:03 -05:00
Domenico Ottolia
fb00d0f209 Fix bugs with privileged tests 2021-03-25 14:06:05 -04:00
Noah Boorstin
ed37e933e5 busybear: stop NOPing out atomics 
and bump regression to check for 800k instrs, up from 200k
 2021-03-25 13:29:56 -04:00
David Harris
dea2ec280e testgen-PIPELINE python startup 2021-03-25 13:12:18 -04:00
Shriya Nadgauda
e55a245948 adding PIPELINE tests 2021-03-25 13:07:25 -04:00
Teo Ene
7c3963547d Config file for ppa experiments 2021-03-25 10:23:21 -05:00
David Harris
1158b3aa73 Added PPA README 2021-03-25 11:21:31 -04:00
Thomas Fleming
89a2fe5741 Finish finite state machines for page table walker 2021-03-25 02:48:40 -04:00
Thomas Fleming
4f01aae844 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-03-25 02:35:21 -04:00
bbracker
d52c71086a added 1 tick delay to dtim flops 2021-03-25 02:23:30 -04:00
bbracker
5327dcfcc8 instrfaults not respecting stalls bugfix 2021-03-25 00:16:26 -04:00
bbracker
a8b7d7a248 upgraded gpio bus interface 2021-03-25 00:15:02 -04:00
bbracker
3e656fc035 future work comment about suspicious-looking verilog in csri.sv 2021-03-25 00:10:44 -04:00
Thomas Fleming
f2604797fb Add all PMP addr registers 2021-03-24 21:58:33 -04:00
Teo Ene
1e691e120b Fix typo from last commit 2021-03-24 17:09:58 -05:00
Teo Ene
9f44eb36ef Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-03-24 17:04:48 -05:00
Teo Ene
6a7b69ff2d Updated coremark_bare testbench for IM 2021-03-24 17:04:43 -05:00
Katherine Parry
123e63b440 fixed various bugs in the FMA 2021-03-24 21:51:17 +00:00
Teo Ene
07f7df82e3 Added BPTYPE to coremark_bare config 2021-03-24 16:38:29 -05:00