Thomas Fleming
6f23858609
Fix HSIZE and HBURST signal widths in PMA checker
2021-04-23 20:11:43 -04:00
Noah Boorstin
50df9d11e1
busybear
2021-04-23 17:32:37 -04:00
Shriya Nadgauda
2a5c243b0b
adding pipeline testing
2021-04-23 14:19:17 -04:00
Jarred Allen
9a88d83851
Remind people to run make allclean when a regression fails
2021-04-22 19:21:00 -04:00
Thomas Fleming
5bff582608
Write PCM to TVAL registers
2021-04-22 16:17:57 -04:00
Thomas Fleming
07770a46d8
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-04-22 15:37:19 -04:00
Thomas Fleming
74fb1dccad
Prepare to squash bad ahb accesses
2021-04-22 15:36:45 -04:00
Thomas Fleming
c055ab272d
Clean up lint errors in fpu and muldiv
...
booth.sv had an actual error where a signal was being assigned to too
many bits. muldiv has a lot of non blocking assignments, so I suppressed
those warnings so the linter output was readable.
2021-04-22 15:36:03 -04:00
Domenico Ottolia
787ae978d7
Fix misa synthesis bug (for real now)
2021-04-22 15:35:20 -04:00
Thomas Fleming
e7822ce20c
Implement first pass at the PMA checker
2021-04-22 15:34:02 -04:00
Thomas Fleming
848508530c
Pass lint-wally arguments to verilator
2021-04-22 13:39:20 -04:00
Jarred Allen
8baa2a350d
Add buildroot to regression test
2021-04-22 13:34:56 -04:00
Thomas Fleming
805ac5dbd7
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-04-22 13:20:12 -04:00
Thomas Fleming
f9e071baf8
Temporarily disable rv64 mmu test
...
Will restore once cache revamp is pushed
2021-04-22 13:19:18 -04:00
bbracker
c796547156
greatly improved PLIC register interface
2021-04-22 11:22:01 -04:00
Thomas Fleming
d22f0f9d63
Refactor tlb_ram to use flop primitives
2021-04-22 01:52:43 -04:00
Thomas Fleming
4d4ca24640
Extend stall on leaf page lookups
2021-04-22 01:51:38 -04:00
Domenico Ottolia
939e36a151
Fix misa bug
2021-04-22 00:59:07 -04:00
Thomas Fleming
88bd151d55
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
...
Conflicts:
wally-pipelined/src/ifu/ifu.sv
2021-04-21 20:01:08 -04:00
Thomas Fleming
70c801331a
Implement virtual memory protection
2021-04-21 19:58:36 -04:00
Teo Ene
6da8530104
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-04-21 16:06:33 -05:00
Teo Ene
008b308b79
Fixed most relevant remaining synthesis compilation warnings with Ben
2021-04-21 16:06:27 -05:00
Noah Boorstin
0afd5ae5f6
buildroot: add workaround for weird initial MSTATUS state
2021-04-21 16:03:42 -04:00
Domenico Ottolia
82320033d5
Add tests for stval and mtval
2021-04-21 02:31:32 -04:00
Domenico Ottolia
fed42ffe19
Add tests for scause, and improve tests for sepc. Also make improvements to privileged test generator run.sh file
2021-04-21 01:12:55 -04:00
Domenico Ottolia
d5f86fadac
Add tests for sepc register
2021-04-20 23:50:53 -04:00
Domenico Ottolia
e02ff60b07
Fix synthesis warnings for privileged unit (replace 'initial' settings)
2021-04-20 17:57:56 -04:00
Noah Boorstin
c7a09d2359
yay buildroot passes a decent amount of tests now
...
gets through the first 15k instructions, that's good enough for now
also slight change to string parsing in busybear testbench
2021-04-19 03:26:08 -04:00
Katherine Parry
204e5cb018
fixed synth bugs in fpu
2021-04-19 00:39:16 +00:00
Noah Boorstin
10c7ac7f73
slowly more buildroot progress
2021-04-18 18:18:07 -04:00
Noah Boorstin
d0a137ce0c
neat verilog thing
2021-04-18 17:48:51 -04:00
Noah Boorstin
5902637632
buildroot: sim is now running!
...
yes it only gets through 5 instructions right now. Yes that's my fault.
2021-04-17 14:44:32 -04:00
Noah Boorstin
541fb22dc9
start to add buildroot testbench
...
This still uses testbench-busybear.sv
I think it might be time to finally rename nearly 'busybear' thing to 'linux'
2021-04-16 23:27:29 -04:00
bbracker
11cf251378
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-04-15 21:09:27 -04:00
bbracker
195cead01c
working GPIO interrupt demo
2021-04-15 21:09:15 -04:00
Domenico Ottolia
b1cd107a00
Add tests for scause and ucause
2021-04-15 19:41:25 -04:00
Domenico Ottolia
a149f2f3d8
Add support for vectored interrupts
2021-04-15 19:13:42 -04:00
Domenico Ottolia
70b79ca301
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-04-15 16:57:27 -04:00
Domenico Ottolia
8c4cfa5f69
Add 32 bit privileged tests
2021-04-15 16:55:39 -04:00
Teo Ene
a9c6d357d8
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-04-15 15:29:09 -05:00
Teo Ene
7a40c27b59
Quick fix to ahblite missing default statement done in class :)
2021-04-15 15:29:04 -05:00
Thomas Fleming
e8770e3eac
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
...
Conflicts:
wally-pipelined/src/mmu/priority_encoder.sv
2021-04-15 16:20:43 -04:00
Thomas Fleming
e838f0bb3d
Change priority encoder to avoid extra assignment
2021-04-15 16:17:35 -04:00
Thomas Fleming
2c4682c4be
Connect tlb and icache properly
2021-04-15 14:48:39 -04:00
Teo Ene
cefc8ea22b
Temporary change to mmu/priority_encoder.sv
...
Necessary to get synth working
Original HDL is still there, just commented out
2021-04-15 13:37:12 -05:00
Katherine Parry
0bdd3efdd5
integraded the FMA into the FPU
2021-04-15 18:28:00 +00:00
Ross Thompson
534e3eaac8
Merge branch 'bpfixes' into main
2021-04-15 09:06:21 -05:00
Shreya Sanghai
75caa65df1
Cherry Pick merge of Shreya's localhistory predictor changes into main.
...
fixed minor bugs in localHistory
2021-04-15 09:04:36 -05:00
ShreyaSanghai
80fbd66113
added localHistoryPredictor
2021-04-15 08:58:22 -05:00
Shreya Sanghai
3696bf4f2c
fixed bugs in global history to read latest GHRE
...
Cherry pick Shreya's commits into main branch.
2021-04-15 08:55:22 -05:00
