Commit Graph

177 Commits

Author SHA1 Message Date
Kip Macsai-Goren
ac5c53a870 Added correct causing and handling of S time interrupts to test suite. 2023-03-04 15:04:17 -08:00
David Harris
f0c0111ab0 Renamed section 12.3 to 8.3 in MMU test definitions 2023-02-19 05:46:46 -08:00
David Harris
4883351bd2 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-01-28 18:18:53 -08:00
Kip Macsai-Goren
ee1bcf62ee Fixed regression test dependance on bp status by adding handling of UART tx empty interrupts. 2023-01-28 17:29:35 -08:00
David Harris
2af94bf283 Removed unused reference files 2023-01-27 07:21:55 -08:00
Kip Macsai-Goren
964084f0b3 added fs=00 to status fp enabled test 2022-12-22 15:15:53 -08:00
Kip Macsai-Goren
d25d699800 Added status.tvm bit test that passes make and regression 2022-12-22 14:43:22 -08:00
Kip Macsai-Goren
a37bde7452 updated trap handler alignemnts to 64 bytes in priv tests 2022-12-22 14:23:04 -08:00
David Harris
ca949f2110 Only delegated bits of SIP are readable 2022-12-21 12:32:49 -08:00
Ross Thompson
f6393d1288 Waiting on fix for wally64periph uart test.
would like to remove vectored interrupt adder.
2022-12-21 13:16:09 -06:00
Ross Thompson
c41d58bd29 Vectored interrupts now require 64 byte alignment.
Eliminates adder.
2022-12-21 12:05:49 -06:00
Kip Macsai-Goren
4c81b6fa5f added corrrect scr read out of uart to periph test 2022-12-05 20:16:02 -08:00
Kip Macsai-Goren
51e78d9e48 added copies of 64 bit tests to 32 bit periph and priv tests 2022-12-05 20:16:02 -08:00
Kip Macsai-Goren
540d6c2f41 added -01 to all WALLY tests 2022-12-05 20:16:02 -08:00
Kip Macsai-Goren
21e045eb7d added potential fix to overrun error and fifo interrupt error. test passes 2022-11-06 22:01:02 -08:00
Kip Macsai-Goren
90ef371abc fixed fifo timout handling. error now in data ready interrupt 2022-11-05 13:34:24 -07:00
Kip Macsai-Goren
c06da6e6fe fixed broken instructions so make works. 2022-11-03 23:06:20 +00:00
Ross Thompson
103514a8e0 More outline for uart timeout interrupt. 2022-10-28 13:53:56 -05:00
Ross Thompson
21eca47d2e Untested change to uart test for outline of how to handle rx fifo timeout. 2022-10-28 13:31:16 -05:00
Kip Macsai-Goren
6e45698b86 Added test for UART FIFO timeout. Does not pass regression 2022-10-25 05:35:56 +00:00
Kip Macsai-Goren
c18c181fc0 fixed endianness mstatush problem, passes make, not regression 2022-10-04 17:37:39 +00:00
Kip Macsai-Goren
e603973dff added xlen and endianness test edits. xlen passes but endinanness still won't make 2022-09-26 05:03:19 +00:00
Kip Macsai-Goren
0cc7f5719c ported endianness tests to 32 bits (not tested in regression yet) 2022-09-18 00:10:29 +00:00
David Harris
898dbc8e74 Completed PLIC-S tests. Regression working. This completes peripheral tests. 2022-08-03 09:33:56 -07:00
David Harris
4fb467ee8a Debugging plic-s test 2022-08-03 13:21:09 +00:00
David Harris
7e5b78f240 plic-s debug 2022-08-03 12:33:09 +00:00
David Harris
cab0349701 Started plic-s tests 2022-08-03 03:48:08 +00:00
David Harris
93d7d7179e Added parity and stop bit tests to UART 2022-07-28 04:35:51 +00:00
David Harris
429bdae1c4 Fixed UART reference output 2022-07-27 22:16:38 +00:00
David Harris
b08c87cb47 Finished UART test 2022-07-27 04:06:59 +00:00
slmnemo
7348af7fd5 Updated reference file for UART test 2022-07-26 09:39:31 -07:00
slmnemo
5218865a7f Committing changes made to UART test 2022-07-26 09:14:40 -07:00
slmnemo
bfced6bfe8 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-07-22 17:13:38 -07:00
slmnemo
ca4511b6dc Fixed UART FIFO bugs and added FIFO tests 2022-07-22 17:13:19 -07:00
Daniel Torres
4da96c5791 fixed 32priv tests, now passing 2022-07-22 15:35:20 -07:00
Daniel Torres
24828db612 changes to test.vh for compatability 2022-07-22 15:00:48 -07:00
Daniel Torres
4198145ce2 added changes to stvec of reference signatures, modified some tests to copy over reference file instead of running on sail 2022-07-22 14:58:55 -07:00
slmnemo
141f2a40e4 UART updates and PMA fix 2022-07-22 14:49:03 -07:00
slmnemo
9cca567136 Added test comments to reference output 2022-07-22 12:35:59 -07:00
Daniel Torres
0e75142ef4 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-07-22 11:16:09 -07:00
Daniel Torres
95fdd408ee commiting current changes to riscof wally tests 2022-07-22 11:14:04 -07:00
slmnemo
d38369e8bf Added new PLIC and UART tests 2022-07-22 07:12:55 -07:00
slmnemo
df568fd202 Added PLIC and UART tests and new functions to the test library 2022-07-22 07:10:39 -07:00
slmnemo
37bf837d48 fixed GPIO test by adding a new function to clear PLIC interrupts 2022-07-19 08:59:16 -07:00
slmnemo
e190aeb14b Fixed error in gpio test 2022-07-08 02:27:16 -07:00
Katherine Parry
7771f7b3eb added load and store test 2022-07-07 21:48:51 +00:00
slmnemo
6b2125ab0e Fixed discrepancies between GPIO tests and book and removed extra unused code from CLINT tests. 2022-07-05 18:21:17 -07:00
slmnemo
f21c3114fd Added termination line to CLINT test 2022-06-27 20:16:29 -07:00
slmnemo
228028c837 Add CLINT tests from book 2022-06-27 20:09:58 -07:00
slmnemo
033ec135f8 Added reset read testcodes to GPIO 2022-06-27 18:56:35 -07:00
slmnemo
cb8ae72326 Fixed error in GPIO signature 2022-06-23 14:12:28 -07:00
David Harris
db459c3380 GPIO tests 2022-06-23 21:06:11 +00:00
slmnemo
d86a65daf0 Updating new GPIO tests 2022-06-23 13:22:00 -07:00
slmnemo
80a57d0469 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-06-21 02:16:26 -07:00
slmnemo
b2cea45de0 Added rudimentary GPIO test according to testplans in chapter 15 2022-06-21 02:16:21 -07:00
Katherine Parry
03d823f5d7 added fld in rv32 - needs testing 2022-06-20 22:53:13 +00:00
DTowersM
b586e3af37 added some comments to help debuggers in the future 2022-06-10 01:44:52 +00:00
DTowersM
4e5d7ec3d6 changed DCACHE_LINELENINBITS and ICACHE_LINELENINBITS to 512, had to modigy the wfi test to increase timee before interupt to mantain compatability 2022-06-10 00:37:53 +00:00
Kip Macsai-Goren
553e7bfeb9 Fixed priv test reference outputs to have the right number of "DEADBEEF"s (1024) 2022-05-12 22:30:14 +00:00
David Harris
73a84f28b9 Moved some privileged tests to be simulated. 2022-05-12 04:45:41 +00:00
David Harris
c100c9893b wally32priv and wally64priv now passing WALLY-status-tw. Fixed privileged.sv to produce the correct EPC on timeouts 2022-05-05 14:37:21 +00:00
Kip Macsai-Goren
8f748c4014 clarified some trap causing functions to use zzero register rather than li [reg] 0x0. Also updated signatures' tvals 2022-05-04 23:01:23 +00:00
Kip Macsai-Goren
88173b8bb3 added explicit clears to mstatus.mie 2022-05-04 23:00:17 +00:00
Kip Macsai-Goren
6a182efe0f Updated test libraries to reflect variable name changes 2022-05-04 21:39:36 +00:00
Kip Macsai-Goren
6a372b1a1d renamed test_loop_setup to run_test_loop 2022-05-04 21:39:09 +00:00
Kip Macsai-Goren
393edc9fd8 renamed debug to extended signature 2022-05-04 21:38:37 +00:00
Kip Macsai-Goren
0f70e48b6b updated makefrag and tests.vh to reflect removed tests, new names 2022-05-04 21:20:25 +00:00
Kip Macsai-Goren
923cbc59a3 removed fp-diabled test and leftover mimpid test 2022-05-04 21:20:25 +00:00
Kip Macsai-Goren
3cab9f0234 removed instruction misaligned tests from trap tests, signatures 2022-05-04 21:20:25 +00:00
Kip Macsai-Goren
8c96672080 renamed all tests to have lower-case titles except for WALLY 2022-05-04 21:20:25 +00:00
Kip Macsai-Goren
208827502e general test cleanup of comments and old files 2022-04-29 19:55:29 +00:00
Kip Macsai-Goren
7148429f4a re-renamed status-mie-s to status-sie 2022-04-29 19:55:13 +00:00
Kip Macsai-Goren
e557e420b6 added missing SIE test 2022-04-29 19:54:29 +00:00
Kip Macsai-Goren
f50aa61994 renamed registers in test library to RISC-V ABI name rater than x2, etc.. 2022-04-29 18:52:42 +00:00
Kip Macsai-Goren
5df381e26f renamed PIE-stack tests to status-mie for clarity 2022-04-29 18:30:39 +00:00
Kip Macsai-Goren
562296c677 added missing output for sret 2022-04-28 18:14:08 +00:00
Kip Macsai-Goren
0e5cc40360 added 32 bit versions of new tests. all but timeout wait pass regression 2022-04-28 18:14:07 +00:00
Kip Macsai-Goren
7ca56fc033 added floating point instructions to privileged tests 2022-04-25 17:47:10 +00:00
Kip Macsai-Goren
b277d3cf19 Removed test cases irrelevant to this implementation, added explanatory comments. 2022-04-22 23:06:52 +00:00
Kip Macsai-Goren
3e62a8f974 Added testing for every bit field in MIE, rather than just one 2022-04-22 23:05:54 +00:00
Kip Macsai-Goren
2cc6d3ddb4 fixed timeouts on GPIO test by enabling pins as inputs as well as outputs. 2022-04-22 22:46:11 +00:00
Kip Macsai-Goren
b5b171372d added 32 bit tests to makefrag 2022-04-20 17:33:56 +00:00
Kip Macsai-Goren
43378ada56 updated 32 bit test lib to mirror 64 bit one in interrupt handling, trap stacks 2022-04-20 17:33:40 +00:00
Kip Macsai-Goren
e28c4ac680 Added 32 bit privilege tests that work but for one bug 2022-04-20 17:32:29 +00:00
Kip Macsai-Goren
7a660a58b6 Updated 32 bit PMA tests to reflect new clint rules 2022-04-20 17:31:08 +00:00
Kip Macsai-Goren
64afc99a02 added unfinished tests to 32 bit library 2022-04-02 19:15:07 +00:00
Kip Macsai-Goren
39c1fdb024 updated 32 bit tests to be in line with 64 bit test library 2022-04-02 19:14:12 +00:00
Kip Macsai-Goren
f7bbae8746 removed compressed instructions from privileged tests 2022-04-02 19:12:44 +00:00
bbracker
e994f70dab change main.config so that buildroot expects linux.config and busybox.config to be at $RISCV/buildroot 2022-03-02 17:46:33 +00:00
David Harris
91a593c020 Fixed march compiling privileged tests to support AMO tests. 2022-03-01 18:02:45 +00:00
Kip Macsai-Goren
f54ed94dbc Changed PMA tests to only allow native length accesses to CLINT 2022-02-28 19:22:44 +00:00
Kip Macsai-Goren
6ed010adda added minor sections to MMU tests that had been missing, global bits still need to be checked 2022-02-27 23:28:44 +00:00
Kip Macsai-Goren
1f516bb346 made sure program isn't passing the testwith a false posistive 2022-02-21 07:14:42 +00:00
Kip Macsai-Goren
d1578d8356 added scratch register tests for 64 and 32 bits 2022-02-21 07:03:12 +00:00
Kip Macsai-Goren
c3523dfa15 Added misa test for both 32 and 64 bits 2022-02-18 19:41:50 +00:00
Kip Macsai-Goren
53f392a62f light cleanup 2022-02-15 20:19:14 +00:00
Kip Macsai-Goren
225b38e793 added high bit registers to CSR permission tests 2022-02-15 20:19:14 +00:00
Kip Macsai-Goren
6c1383e2a0 added CSR permission and minfor to 32 bit tests 2022-02-15 20:19:14 +00:00
Kip Macsai-Goren
5df0a9531f merged test macros in with 32 bit tests 2022-02-15 20:19:14 +00:00
David Harris
9ad3f26365 Restored E tests to makefrag 2022-02-08 16:41:11 +00:00