Rose Thompson
9cd2e47783
Aligner is integrated and enabled in rv64gc and passes the regression test; however, there are no new tests.
2023-10-30 14:54:58 -05:00
Rose Thompson
569e3dc906
Finally lints cleanly.
2023-10-30 14:00:49 -05:00
Rose Thompson
dce3c85105
Progress.
2023-10-27 16:31:22 -05:00
Rose Thompson
747f453bb5
Passes lint with some exceptions. Still need to add misaligned store support.
2023-10-27 14:41:42 -05:00
Rose Thompson
36ca64c567
At least have the aligner integrated, but not tested.
2023-10-27 13:55:16 -05:00
Rose Thompson
657409aec5
Addec ZICCLSM to config files and started on lsu instance.
2023-10-27 13:07:23 -05:00
Rose Thompson
6041bf20b3
The misaligned load alignment lints.
2023-10-27 11:41:49 -05:00
Rose Thompson
834c0df697
Added file.
2023-10-27 09:49:44 -05:00
Rose Thompson
449abef823
Progress on misaligned load/stores.
2023-10-27 09:35:44 -05:00
Rose Thompson
12763b7297
begin implemenation of Zicclsm.
2023-10-26 11:51:20 -05:00
David Harris
3bb7539429
Fixed warnings of signed conversion and for Design Compiler
2023-10-24 14:01:43 -07:00
David Harris
d526d28804
Added MENVCFG.HADE bit and updated SVADU to depend on this bit
2023-10-04 09:34:28 -07:00
David Harris
bd6eef2a51
Initial implementation of SVNAPOT and SVPBMT does not break regression
2023-08-25 18:33:08 -07:00
Ross Thompson
4eeba9bed9
Added cbom test to custom. Needs to be moved to wally-riscv-arch-tests.
2023-08-18 15:59:39 -05:00
Ross Thompson
0eac74ac7b
Initial CMO implementation. Just adds control signals into the L1 caches.
2023-08-14 15:43:12 -05:00
Ross Thompson
7a196d3fa7
Cache cleanup.
2023-07-31 14:12:53 -05:00
Ross Thompson
15dc76310e
Fixed lint errors for issue #368 . Does not fix simulation errors. We made a design decision a long time ago to not support DTIM on the rv32gc config because LLEN was greater than XLEN.
2023-07-26 15:08:01 -05:00
Ross Thompson
f895898d22
Improved the critical path even more. The Arty A7 works upto 19Mhz easily. Testing out 22Mhz now.
2023-07-21 16:31:26 -05:00
Ross Thompson
d04d2afed2
Modified the LSU/IFU and caches to improve critical path. Arty A7 went from 15 to 17Mhz. I believe we can push all the way to 20+Mhz with relatively little effort. Along the way I'm fixing up the scripts build the linux images for the flash card.
2023-07-21 13:06:27 -05:00
David Harris
afe66d0ee4
Added prefetch instructions; sent cbo instructions to LSU
2023-07-02 10:55:35 -07:00
Ross Thompson
85567841eb
Merge branch 'testbench-params2'
2023-06-15 15:31:13 -05:00
Ross Thompson
009d8966e9
Got the srams parameterized correctly now.
2023-06-15 13:42:24 -05:00
Ross Thompson
b8a243827b
Found a whole bunch of files still using the old `define configurations.
2023-06-15 13:09:07 -05:00
Harshini Srinath
15928c5d7b
Update swbytemask.sv
...
Program clean up
2023-06-12 13:37:35 -07:00
Harshini Srinath
f3a7d9030c
Update subwordwrite.sv
...
Program clean up
2023-06-12 13:35:27 -07:00
Harshini Srinath
f1f21f0896
Update subwordread.sv
...
Program clean up
2023-06-12 13:31:54 -07:00
Harshini Srinath
4d0be994aa
Update lsu.sv
...
Program clean up
2023-06-12 13:29:18 -07:00
Harshini Srinath
a45f2fd044
Update lrsc.sv
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Program clean up
2023-06-12 13:14:36 -07:00
Harshini Srinath
d21fd3da44
Update dtim.sv
...
Program clean up
2023-06-12 13:11:24 -07:00
Harshini Srinath
048e100805
Update atomic.sv
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Program clean up
2023-06-12 13:08:54 -07:00
Harshini Srinath
ec1aa29edc
Update amoalu.sv
...
Program clean up
2023-06-12 12:54:50 -07:00
Ross Thompson
4d961bd080
Completed LSU parameterization based on Lim's changes.
2023-05-26 11:26:09 -05:00
Ross Thompson
d37e010aa4
Subwordread now parameterized.
2023-05-26 11:22:44 -05:00
Ross Thompson
0e1131d190
Progress on LSU.
2023-05-26 10:47:09 -05:00
Ross Thompson
fcb1c63f5f
Partial parameterization into mmu.
2023-05-24 16:12:41 -05:00
Ross Thompson
052bc95966
More parameterization. Copied Lim. Still no slow down.
2023-05-24 14:49:22 -05:00
David Harris
ee6a3f49f0
Added M suffix in atomic
2023-04-24 12:19:56 -07:00
Ross Thompson
394f2d65f2
Progress on bug 203.
2023-04-05 13:20:04 -05:00
David Harris
fd0c9e973d
Coverage improvements in ieu, hazard units
2023-03-31 08:33:46 -07:00
Ross Thompson
366a96a0fc
Possible fix for issue 148.
...
I found the problem. We use a Committed(F/M) signal to indicate the IFU or LSU has an ongoing cache or bus transaction and should not be interrupted. At the time of the mret, the IFU is fetching uncacheable invalid instructions asserting CommittedF. As the IFU finishes the request it unstalls the pipeline but continues to assert CommittedF. (This is not necessary for the IFU). In the same cycle the LSU d cache misses. Because CommittedF is blocking the interrupt the d cache submits a cache line fetch to the EBU.
I am thinking out loud here. At it's core the Committed(F/M) ensure memory operations are atomic and caches don't get into inconsistent states. Once the memory operation is completed the LSU/IFU removes the stall but continues to hold Committed(F/M) because the memory operation has completed and it would be wrong to allow an interrupt to occur with a completed load/store. However this is not true of the IFU. If we lower CommittedF once the operation is complete then this problem is solved. The interrupt won't be masked and the LSU will flush the d cache miss.
This requires a minor change in the cachebusfsm and cachefsm. I will report back after I've confirmed this works.
2023-03-28 14:47:08 -05:00
Ross Thompson
46b1bca4fc
Fixed all tap/space issue in RTL.
2023-03-24 17:32:25 -05:00
David Harris
a1eccf37dc
Fix Issue 145
2023-03-22 04:33:14 -07:00
David Harris
4c6f539449
Removed flq from LLEN=64
2023-03-19 10:25:04 -07:00
Ross Thompson
3cae6ca90f
Updated NextAdr to NextSet.
2023-03-13 14:54:13 -05:00
Ross Thompson
a5523400ae
Replaced DCACHE parameter with READ_ONLY_CACHE as the name was confusing in chapter 10.
2023-03-12 13:21:22 -05:00
Ross Thompson
31fcc0daf7
Renamed PCFSpill to PCSpillF.
2023-03-06 17:50:57 -06:00
Ross Thompson
aabb454d1c
Added the i and d cache cycle counters.
2023-03-02 23:54:56 -06:00
David Harris
21b28fd1bb
Renamed DAPageFault to UpdateDA
2023-02-26 17:51:45 -08:00
David Harris
5287c54278
Adjusted DTIM to always be 512B independent of XLEN
2023-02-19 16:14:38 -08:00
David Harris
97ee3732fe
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2023-02-03 08:36:11 -08:00
David Harris
78eb90715c
Removed pipelined level of hierarchy
2023-02-02 14:14:11 -08:00
