Rose Thompson
edc56c669e
Fixed bug 546. non-leaf non-zero PBMT bit raise page fault.
2024-01-05 17:10:14 -06:00
David Harris
680a014876
Finished LSU tlbcontrol coverage tests
2024-01-02 10:16:20 -08:00
David Harris
f4ee05e1ea
Coverage improvements
2024-01-01 08:31:09 -08:00
David Harris
e5ac2d5ef0
Modified align fsm to make coverage easier
2024-01-01 08:21:31 -08:00
Rose Thompson
730efefc41
Cleanup.
2023-12-29 16:18:30 -06:00
Rose Thompson
6a787981c2
Restored cache store delay hazard.
2023-12-29 16:10:27 -06:00
Rose Thompson
0264a17f77
Reverted dtim to use store delay stall, but only (load after store).
2023-12-29 16:06:30 -06:00
Rose Thompson
f59fa5089d
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-12-29 15:13:18 -06:00
Rose Thompson
8030b7d100
Added partial code for uncached amo operations.
...
Minor fix for Makefile so coverage tests build.
2023-12-29 15:07:20 -06:00
Rose Thompson
52dad4f130
cbo.zero works for uncached memory now!
2023-12-29 11:11:06 -06:00
David Harris
e8df856fdb
Renamed CMOp to CMOpM in mmu and cache
2023-12-25 05:57:41 -08:00
David Harris
29f57958a9
Fixed WALLY-lrsc in ImperasDV by setting reservation set size to native word size and adjusting imperas.ic lr_sc_grain=8 to match
2023-12-14 15:32:36 -08:00
Rose Thompson
9f4c32d49c
Merge branch 'main' of github.com:ross144/cvw
2023-12-13 20:32:59 -06:00
Rose Thompson
b69a5b59cd
DTIM works without the store delay stall. Still a bit of work remaining. The DTIM needs cleanup.
...
The cache needs a bit of clean up and the chapter needs updates.
The controller needs to be updated to remove the store delay hazard for cmo instructions.
2023-12-13 20:32:14 -06:00
David Harris
6c017141c5
Renamed HADE to ADUE for Svadu
2023-12-13 11:49:04 -08:00
Rose Thompson
13bb5d845b
On the way to solving the store delay hazard.
2023-12-13 10:39:01 -06:00
Rose Thompson
1ebc7aa95a
Optimized align.
2023-12-03 16:43:55 -06:00
Rose Thompson
d29b2b95f7
Additional cleanup.
2023-11-28 23:28:50 -06:00
Rose Thompson
4149ae6c11
More cleanup.
2023-11-28 23:05:47 -06:00
Rose Thompson
143c6ca4d1
Simplification to alignment.
2023-11-28 22:28:11 -06:00
Rose Thompson
a69a70ba7f
Removed unused hardware from alignment.
2023-11-28 19:54:25 -06:00
Rose Thompson
865ebf8b9b
cclsm cleanup.
2023-11-28 19:41:46 -06:00
Rose Thompson
f4e77e9669
Clean up.
2023-11-28 14:21:37 -06:00
Rose Thompson
df85428041
More optimizations for cclsm.
2023-11-28 14:19:30 -06:00
Rose Thompson
4d4790ecf9
Optimizations to cclsm.
2023-11-28 14:18:06 -06:00
Rose Thompson
195def5808
Extended the abhcacheinterface to zero a cacheline's worth of uncached memory on cbo.zero.
2023-11-27 21:24:30 -06:00
Rose Thompson
beb95dd592
Modified the pmachecker to correctly check the permissions for cmo instructions.
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However this isn't fully tested.
2023-11-27 17:44:11 -06:00
Rose Thompson
337903d8dd
More cache simplifications.
2023-11-27 14:59:42 -06:00
David Harris
1f57df7f8b
Fixed reference to deleted atomic signal in cache
2023-11-23 20:29:10 -08:00
David Harris
d3ce683e06
Removed other unused signals from Verilog
2023-11-20 23:37:56 -08:00
David Harris
f89fd8a7fe
removed unused cache signals
2023-11-20 23:16:35 -08:00
David Harris
acd8a63628
Merge pull request #489 from ross144/main
...
fixes issue #487
2023-11-18 19:22:33 -08:00
Rose Thompson
8cbd3de413
Fixed Zicclsm bug. Misalignment and spill detection were not masked by access type. Therefore a page table walk which always aligned could have had an IEUAdrM misaligned which erroneously caused a shift in the read data.
2023-11-18 19:01:39 -06:00
David Harris
eef39bd495
Fixed typo in lsu parameter
2023-11-15 08:30:48 -08:00
David Harris
817ddbc7c5
Adjusted LSU misaligned buffer to fix synthesis warning
2023-11-15 08:19:50 -08:00
Rose Thompson
a6995af91c
Fixed bug in uncore updates which broke SDC.
2023-11-13 16:15:23 -06:00
Rose Thompson
707b0c557c
Cleanup and optimization of Zicclsm.
2023-11-13 14:28:22 -06:00
Rose Thompson
cc7a0b211a
Cleanup.
2023-11-13 12:35:11 -06:00
Rose Thompson
c8cca8dfb8
Simplification.
2023-11-10 18:39:36 -06:00
Rose Thompson
c0e02ae190
Found another bug in the RTL's Zicclsm alignment.
2023-11-10 18:26:55 -06:00
Rose Thompson
02ab9fe99c
Fixed all the bugs associated with the signature and the store side of misaligned access. Load misaligned is still causing some issues.
2023-11-10 17:58:42 -06:00
Rose Thompson
84d86b1994
Fixed spill bugs in the aligner.
2023-11-10 17:18:45 -06:00
Rose Thompson
b74bfbeefd
Merge branch 'main' into Zicclsm
2023-11-10 16:15:32 -06:00
Rose Thompson
9abd26aad9
Fixed bug which broke the non Zicclsm configs.
2023-11-10 16:08:04 -06:00
David Harris
1f2899de14
Modified rams to take USE_SRAM rather than P to facilitate synthesis
2023-11-03 05:44:13 -07:00
Rose Thompson
0a4ed5515b
Merge branch 'main' into Zicclsm
2023-11-02 12:55:51 -05:00
Rose Thompson
13333d3e82
Finally the d$ spill works. At least until the next bug. Definitely needs a lot of cleanup.
2023-11-01 14:25:18 -05:00
Rose Thompson
5660eff57d
Working through issues with the psill logic.
2023-10-31 18:50:13 -05:00
Rose Thompson
f13b67b869
Preemptively fixed the bytemask bug before testing.
2023-10-30 15:47:46 -05:00
Rose Thompson
b5763e11e8
rv32gc now also works with the alignment module. Still not tested with misligned access.
2023-10-30 15:30:09 -05:00
