Corey Hickson
1570a6338e
Fixed fmvp.d.x bug
2024-11-06 03:32:53 -08:00
Jacob Pease
507c1dad1c
Removed impossible condition in receive register logic.
2024-11-04 16:15:42 -06:00
Jacob Pease
120b21d7d5
More SPI optimizations.
2024-11-04 15:38:12 -06:00
Jacob Pease
745e53adf7
Merge branch 'main' of github.com:openhwgroup/cvw
2024-11-04 11:56:15 -06:00
Corey Hickson
0c6e9dc770
Fixed rmm rounding mode bug
2024-11-03 14:21:55 -08:00
Jacob Pease
a9e6962cd4
Removed unused signals and renamed other signals. Removed a bunch of delay counters and simply reuse one counter for all delay types. Tested on FPGA and it also passes regression.
2024-11-03 00:35:40 -05:00
Jacob Pease
674d008f23
Added headers to files.
2024-11-02 14:31:05 -05:00
Jacob Pease
c197d4a3c6
Cleaned up some code. Still more work to do there.
2024-11-01 17:35:55 -05:00
Jacob Pease
e881bd3120
Changed the condition for TransmitStart fsm to avoid edge condition.
2024-11-01 17:04:07 -05:00
Jacob Pease
eddae8e1a6
Fixed ShiftEdge and SampleEdge to not always include PhaseOneOffset. Before, it worked in simulation, but not on the FPGA.
2024-11-01 13:02:17 -05:00
Jacob Pease
56a6ad3376
Fixed lint issues.
2024-10-31 15:56:16 -05:00
Jacob Pease
3ee5fffe02
Fixing latches.
2024-10-31 13:54:56 -05:00
Jacob Pease
72a854eb07
Refactored SPI passes regression save for hardware interlock tests.
2024-10-31 13:01:25 -05:00
Jacob Pease
419030bc33
Fixed FSM to continue transmitting after delay.
2024-10-31 10:41:38 -05:00
Jacob Pease
35c9fe7648
Added changed SPI controller module. New signal TransmitStartD that starts the FSM based on SCLKenable. TransmitStart is responsible for resetting SCLKenable and loading the Transmit Shift Register.
2024-10-30 18:45:54 -05:00
Jacob Pease
4e7e311b26
Fixed issues relating to SCLKenable and TransmitStart. Works at multiple dividers now, instead of just SckDiv = 0.
2024-10-30 18:39:04 -05:00
Jacob Pease
4f0723f236
Fixed enabling of TransmitFIFOReadIncrement and ReceiveFIFOWriteIncrement
2024-10-30 16:19:46 -05:00
Jacob Pease
ca1c09041a
Merge branch 'main' of github.com:openhwgroup/cvw
2024-10-30 10:37:02 -05:00
Corey Hickson
b1f340ba5c
formatting
2024-10-30 03:39:55 -07:00
Corey Hickson
b9317e7cd3
Fixed fround bug
2024-10-30 03:28:58 -07:00
Jacob Pease
b667581ffa
Refactored SPI peripheral based on SPI controller module. Works in tests/custom/spitest.
2024-10-29 17:50:36 -05:00
Jacob Pease
784630b945
Added wally header to spi_controller.
2024-10-29 10:53:33 -05:00
Jacob Pease
37d2f3220e
Added a new spi controller design. Designed as a proof of concept to see if timing issues can be fixed. I intend to work it into existing SPI peripheral.
2024-10-29 10:30:08 -05:00
David Harris
1c1acc467e
Tweaked SPI to avoid breaking VCS, but the SCLK divider still doesn't produce the right frequency and SCLKenableEarly looks like it wouldn't work for SckDiv = 0
2024-10-26 02:01:09 -07:00
David Harris
da2310fb3e
Merge conflict in coverage.svh
2024-10-22 04:48:57 -07:00
Rose Thompson
a4cda877ef
Fixed bit position of SPI fifo receive and transmit flags.
2024-10-21 14:52:40 -05:00
David Harris
aaa2edac18
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2024-10-16 13:26:51 -07:00
David Harris
150641e5d3
Implemented mhpmevent[3:31] as read-only zero rather than illegal
2024-10-15 09:08:25 -07:00
Rose Thompson
8fb1673ab3
Updated email address authorship for my files.
2024-10-15 10:27:53 -05:00
David Harris
de8a707361
Updated WARL field in senvcfg.CBIE to match ImperasDV
2024-10-14 15:28:56 -07:00
Rose Thompson
d8fe68b912
Merge pull request #1011 from davidharrishmc/dev
...
Fixed bug causing Issue 1010 and made some changes to Wally privileged fields to match ImperasDV
2024-10-14 11:10:21 -05:00
David Harris
43162aa088
Fixed handling writing reserved 10 value to mstatus.mpp
2024-10-14 08:42:52 -07:00
David Harris
5ef5633a62
Adjusted menvcfg.CBIE reserved 10 behavior to match ImperasDV; spec is ambiguous (riscv-isa-manual Issue #1682
2024-10-14 05:31:59 -07:00
Jordan Carlin
e7b9369f7f
Merge pull request #1008 from davidharrishmc/dev
...
Fix mcountinhibit bit 1 that should be hardwired to 0
2024-10-13 22:44:35 -07:00
David Harris
9ef211b40d
mcountinhibit bit 1 should be hardwired to 0. Discovered during functional coverage testing
2024-10-13 20:59:01 -07:00
Rose Thompson
5011084d40
Revert "This is a better solution. It's closer to the original book HPTW FSM,"
...
This actually adds to the critical path and it's more complex than I feel comfortable.
This reverts commit 1ded4a972f
2024-10-11 17:02:51 -05:00
Rose Thompson
1ded4a972f
This is a better solution. It's closer to the original book HPTW FSM,
...
but is slightly more complex in RTL. Instead it looks at ReadDataM
for the PTE for PBMT faults. I was worried this would cause critical
path issues but I think it is ok. ReadDataM is used only to created
PBMT and this directly controlls the enable to a flop and the state
inputs to the FSM.
2024-10-11 16:47:18 -05:00
Rose Thompson
4c7eb1d11f
Renamed IgnoreRequestTLB to HPTWFlushW and IgnoreRequest to LSUFlushW.
2024-10-11 15:41:40 -05:00
Rose Thompson
37d3db916b
Resolved the HPTW's not taking the PBMT fault on the right cycle by
...
having the fsm branch to fault on any cycle a HPTWFaultM occurs. This
of course changes the figure in the book but it really relevant to
PBMT. This appeared to work because the HPTW happened to also generate
an access fault at the end of the walk and the logic produced both
faults. I wrote new test which confirms just the one is generated.
2024-10-11 15:31:20 -05:00
Rose Thompson
7a92d41ef5
Simplified logic around IgnoreRequest and HPTWFaultM.
2024-10-11 14:41:52 -05:00
Rose Thompson
fe5f342d2f
Does not work. But there is a bug hiding the IgnoreRequest confusion.
2024-10-11 12:07:26 -05:00
Rose Thompson
6a905aa2f2
Possible start to resolution on issue #839 .
2024-10-10 17:14:27 -05:00
Rose Thompson
943f6b680e
LSU cleanup.
2024-10-02 17:38:22 -05:00
Rose Thompson
35693eb7cc
Fixed bug so AMO access faults only produce StoreAmoAccessFault and
...
not both LoadAccessFault adn StoreAmoAccessFault.
2024-10-02 14:04:01 -05:00
Rose Thompson
2112c705a4
Supress misaligned faults during a tlb miss. Still needs to be tested.
2024-09-30 15:55:46 -05:00
David Harris
7f0c2662b3
Merge pull request #966 from ross144/main
...
Updates wsim to fail with invalid --lockstep parameters
2024-09-26 08:48:42 -07:00
Rose Thompson
1345a0f315
Merge branch 'main' of https://github.com/openhwgroup/cvw
2024-09-24 10:13:50 -05:00
David Harris
468e48899a
Remove outdated code
2024-09-23 06:06:26 -07:00
Rose Thompson
32624bc6ee
Relocated a logic in a file to avoid a future merge conflict.
2024-09-05 12:50:09 -07:00
Rose Thompson
005ea52b72
Added missing signal declaration for SPI.
2024-09-05 12:20:06 -07:00
