David Harris
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5d8d82414b
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Coverage improvements
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2024-02-04 11:40:38 -08:00 |
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harshinisrinath
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c7b647bde7
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Wrote exclusions for ifu and lsu peripherals which were always supported
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2024-02-01 17:12:33 -08:00 |
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David Harris
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1c62c5e433
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Fixed logic to work with FLEN < XLEN
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2024-01-31 20:24:16 -08:00 |
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David Harris
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0abfe5cb55
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Fixed some lint errors in derived configs
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2024-01-31 11:39:59 -08:00 |
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David Harris
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06778088ab
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Merge pull request #603 from stineje/main
Update cvt bug that was caught with new testbench-fp
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2024-01-30 08:52:01 -08:00 |
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James E. Stine
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7e036e6f75
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Update cvt bug that was caught with new testbench-fp
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2024-01-30 10:51:07 -06:00 |
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David Harris
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3db5b6d9a9
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Fix FLI to support quads
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2024-01-29 14:51:21 -08:00 |
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David Harris
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45e2317636
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Added Wally github address to header comments
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2024-01-29 05:38:11 -08:00 |
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David Harris
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2449e06e55
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Fixed FPU coverage, solved Issue 596 by misaligned AMO throwing access fault when misaligned non-amo are supported
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2024-01-25 21:03:41 -08:00 |
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David Harris
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17f579d4ba
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Reenabled fmadd.h, which is really supported by Zfh
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2024-01-24 07:46:50 -08:00 |
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Rose Thompson
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117ff1828a
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Merge pull request #590 from openhwgroup/revert-589-shiftcorrectiondebug
Revert "more shiftcorrection bug fixes"
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2024-01-23 16:05:30 -06:00 |
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David Harris
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171430a695
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FPU and PMP tests
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2024-01-21 14:41:22 -08:00 |
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David Harris
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ff055c404c
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fpu coverage improvements
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2024-01-21 13:17:56 -08:00 |
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David Harris
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9d4a14b209
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coverage improvements
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2024-01-21 11:39:51 -08:00 |
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David Harris
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d801bf5d6c
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Revert "more shiftcorrection bug fixes"
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2024-01-21 10:41:14 -08:00 |
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David Harris
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9e6fa8076f
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2024-01-21 10:15:38 -08:00 |
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Kevin Kim
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1459943a75
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more shiftcorrection bug fixes
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2024-01-21 10:08:48 -08:00 |
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David Harris
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69218b4b86
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Coverage improvements
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2024-01-21 10:03:07 -08:00 |
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David Harris
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17c9be7695
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Cleanup typos, remove Zicond from riscof until it is working
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2024-01-18 21:36:52 -08:00 |
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David Harris
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74b242ce5c
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Partial implementation of fcvtmod.w.d; flags disagree in one case where Sail might be wrong, and result 134 is wrong because of overflow
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2024-01-17 12:25:06 -08:00 |
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David Harris
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4cfc86140c
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Zfa fmvh complete and passing tests:
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2024-01-17 06:18:00 -08:00 |
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David Harris
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07e7e02241
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Coded Zfa fmvp but no tests exist
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2024-01-16 21:26:42 -08:00 |
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David Harris
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8654375f26
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Zfa fminm/fmaxm/fltq/fleq implemented and tested
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2024-01-16 20:03:54 -08:00 |
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David Harris
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9d57002c07
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Zfa fli support working for F and D (add fli.sv module)
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2024-01-16 17:27:59 -08:00 |
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David Harris
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0588d611ea
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Zfa fli support working for F and D
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2024-01-16 17:27:40 -08:00 |
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David Harris
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846a0c4d50
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Check fma operations don't support H precision
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2024-01-16 11:12:06 -08:00 |
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David Harris
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1a77c08f6e
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Fixed issues 575 and 477 about FPU tests failing when Zfh = 1.
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2024-01-16 10:46:44 -08:00 |
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David Harris
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dcd40c6be7
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Fixed spelling of output
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2024-01-16 10:27:31 -08:00 |
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David Harris
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abecc98563
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Fixed spelling of precision
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2024-01-16 10:26:00 -08:00 |
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David Harris
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0235970313
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Optimized away unused support for fmv with quads
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2024-01-15 13:40:12 -08:00 |
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David Harris
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da4eca4854
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Tested Zfh support using unreleased version of risch-arch-test Zfh tests. Fixed two bugs in fmv to/from int.
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2024-01-15 13:24:57 -08:00 |
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David Harris
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9e78a7e290
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Incorporated jstine fixes of FPU special case and testbench for conversion
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2024-01-15 07:25:08 -08:00 |
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David Harris
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fd181169fe
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Corrected spelling of negative
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2024-01-15 07:15:23 -08:00 |
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James E. Stine
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b14cd67bef
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Values for IEEE 754 vs. RISC-V Table 11.4 in the RISC-V Unprivileged ISA
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2024-01-14 22:08:42 -06:00 |
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David Harris
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6226c3db96
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Revert "Fixes for Issue #541"
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2024-01-12 07:50:13 -08:00 |
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James E. Stine
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e707eeb7c8
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THis includes fix for special case when conversion from fp to int/long. The previous src did not test both the flags and result and so missed this subtle bug when an Invalid happens for this type of conversion. These results are indications of undefined behavior for these operations. All fp operations now passs when this update is fixed. Much of the information why these outputs should occur is somewhat alluded to by Pascal Cuoq originally from INSA in Lyon here: https://frama-c.com/2013/10/09/Overflow-float-integer.html
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2024-01-12 00:37:50 -06:00 |
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David Harris
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d3ce683e06
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Removed other unused signals from Verilog
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2023-11-20 23:37:56 -08:00 |
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David Harris
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121f685fa2
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Removed assign statement inside always block
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2023-11-13 07:23:15 -08:00 |
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David Harris
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c44ae93e22
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DivStickyM no longer mysteriously needs to be gated with SqrtM after divder improvemenst
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2023-11-12 20:23:27 -08:00 |
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David Harris
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065f3f3f6d
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DivStickyM no longer mysteriously needs to be gated with SqrtM after divder improvemenst
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2023-11-12 20:23:14 -08:00 |
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David Harris
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571c7d3be4
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Divider cleanup
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2023-11-12 19:41:12 -08:00 |
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David Harris
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f437336540
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Explained sqrt preshifting
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2023-11-12 10:05:54 -08:00 |
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David Harris
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7c50b2c571
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Renamed qsel to uslc and simplified radix2 uslc
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2023-11-12 06:36:57 -08:00 |
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David Harris
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002034845a
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fdivsqrt comment improvements
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2023-11-12 06:15:47 -08:00 |
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David Harris
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6ac83c776e
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Cleaned up number of bits in fdivsqrt
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2023-11-11 15:50:06 -08:00 |
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David Harris
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2bf5143163
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Bug fixes related to size of fpdivsqrt bit count and number of cycles
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2023-11-11 05:58:53 -08:00 |
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David Harris
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3cae2385ab
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Simplified out LOGRK parameter
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2023-11-10 18:19:41 -08:00 |
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David Harris
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7d0d9dcebe
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divider cleanup
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2023-11-10 18:01:13 -08:00 |
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David Harris
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03864642a7
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fdivsqrt cleanup
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2023-11-10 16:42:32 -08:00 |
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David Harris
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3108b58290
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Simplified integer postnormalization shift
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2023-11-10 14:55:36 -08:00 |
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