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114 Commits

Author SHA1 Message Date
David Harris
6c017141c5 Renamed HADE to ADUE for Svadu 2023-12-13 11:49:04 -08:00
David Harris
aff61ea97a Fixed Linux makefile; load branch predictor RAMs at startup for sim; fixed comment in trap; starting to make testbench more compatible with Verilator 2023-12-13 11:33:59 -08:00
David Harris
3f3c20a38f Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-11-21 14:04:02 -08:00
David Harris
b5f79c44f9 Reset STIMECMP to 0 to agree with ImperasDV 2023-11-21 13:43:51 -08:00
Rose Thompson
386cf3eb56 Merge pull request #493 from stineje/main 
marchid approved by RISC-V
 2023-11-21 08:33:07 -08:00
James E. Stine
141cbd3f9f Update marchid/mvendorid for CV-Wally 2023-11-21 09:23:02 -06:00
David Harris
d3ce683e06 Removed other unused signals from Verilog 2023-11-20 23:37:56 -08:00
David Harris
f6a7f707bd Fixed test cases for medeleg issue 444. Also added a COMPRESSED_SUPPORTED parameter true when C or Zca is supported, and use this to get compressed hardware such as the spill logic and the +2 adder. 2023-10-30 09:56:17 -07:00
David Harris
27b8ebb9bd Fix issue 444 by preventing delegation of misaligned instructions when compressed instructions are supported. 2023-10-30 07:06:34 -07:00
Rose Thompson
06b5a92eff Updated comments about Interrupt and wfi. 2023-10-26 12:24:36 -05:00
Rose Thompson
3322ff915e Cleaned up the implementation changes for wfi. 2023-10-24 23:11:48 -05:00
Rose Thompson
c58f04c901 This version passes the regression test and solves issue #200. wfi's implemenation is changed so that wfi does not take an interrupt in the Memory stage. Instead it advances to the Writeback stage then traps. 2023-10-24 22:58:26 -05:00
Rose Thompson
c61526d034 Possible fix for wfi. 2023-10-24 18:08:33 -05:00
David Harris
434d6b2c5c minfo test working again with mconfigptr for RV64 2023-10-15 06:41:52 -07:00
Ross Thompson
e02d3577ec Fixed issue #412 
The root cause was DTLB miss leads to page fault exception with concurrent I$ miss.  The HPTW hits all entries in the D$ and quickly faults.  However the I$ is still waiting on the main memory.
The trap then interrupts the atomimicity of the bus fetch and breaks the next several instructions.

The simplest solution is to use CommittedF to delay Exceptions like with Interrupts.  Note this cannot happen with CommittedM.  If the ITLB misses and the D$ also need to fetch a from the bus an ITLB page fault exception will not trigger the trap until a few stages later.
 2023-10-09 16:03:37 -05:00
David Harris
d526d28804 Added MENVCFG.HADE bit and updated SVADU to depend on this bit 2023-10-04 09:34:28 -07:00
David Harris
7a092a2275 Fixed merge conflict for ZICBOP 2023-08-25 18:41:57 -07:00
David Harris
bd6eef2a51 Initial implementation of SVNAPOT and SVPBMT does not break regression 2023-08-25 18:33:08 -07:00
David Harris
c6631ef808 Added N and PBMT bits to MMU PTE 2023-08-24 19:44:46 -07:00
David Harris
c45fbe1ffe Merge pull request #394 from harshinisrinath1001/main 
Improved testing of csri with priv.S!
 2023-08-24 19:16:50 -07:00
harshinisrinath
c9112ff18d Improved testing of csri with priv.S 2023-08-24 18:39:15 -07:00
David Harris
f5dab9f2fe Check for legal SATP mode values 2023-08-24 05:18:04 -07:00
Ross Thompson
00e65c4ae7 Oups there was a bug in the SATP fix. RV32GC was broken by the changes. 2023-08-23 09:42:46 -05:00
Jacob Pease
140d246fb5 Prevented writes to SATP enabling SV57. This follows the spec more accurately. Linux can now successfully probe SATP. 2023-08-22 16:25:56 -05:00
Ross Thompson
7e06775135 Fixed a very subtle combinational loop bug the SSTC implementation of csrs.sv. STIMCMPH did not assign all XLEN bits of CSRSReadValM so dc_shell produced d-latches and vivado created a combinational loop. 2023-07-28 11:20:29 -05:00
Ross Thompson
af0e33209f Removed QEMU from configurations. 2023-07-19 10:23:55 -05:00
Ross Thompson
50bc679fef Fixed bug with performance counters not tracking the correct number of requested icache and dcache memory operations. 2023-07-14 16:31:44 -05:00
David Harris
644afa16cd Clean up privilege rs1 decoding and implement svinval as sfence.vma 2023-07-13 02:41:17 -07:00
David Harris
e713ba8d3e MENVCFG only exists if U_SUPPORTED 2023-07-09 18:25:07 -07:00
David Harris
369e8fb5ec Removed outdated commment about endianness 2023-07-06 12:41:46 -07:00
David Harris
869a7cb827 Removed MTINST, which is not used in a system without a hypervisor 2023-07-06 12:40:53 -07:00
David Harris
c48283801a Fixed csr typos 2023-07-02 02:01:40 -07:00
David Harris
61208e486c Fixed ENVCFG to reply on both MENVCFG and SENVCFG when in user mode 2023-07-02 02:00:27 -07:00
David Harris
b6ae5661b4 Added environment configuration control (menvcfg/senvcfg) of cbo instructions 2023-07-02 01:52:25 -07:00
David Harris
15314a9c9a Gated floating-point load/stores with STATUS_FS and added initial decoding for Cache Management Operations 2023-07-02 00:34:30 -07:00
Harshini Srinath
3593762cfa Merge branch 'main' into main 2023-06-14 11:52:45 -07:00
Harshini Srinath
3f8cd8932c Update csrs.sv 
Program clean up
 2023-06-13 22:16:43 -07:00
Harshini Srinath
12af05da02 Update csrm.sv 
Program clean up
 2023-06-13 22:08:06 -07:00
Harshini Srinath
a213f7d5a4 Update csrc.sv 
Program clean up
 2023-06-13 21:54:47 -07:00
Harshini Srinath
6aba0187d7 Update csr.sv 
Program clean up
 2023-06-13 21:12:49 -07:00
Harshini Srinath
2c6322647f Update trap.sv 
Program clean up
 2023-06-12 20:31:44 -07:00
Harshini Srinath
dba1a77e5f Update privmode.sv 
Program clean up
 2023-06-12 20:27:48 -07:00
Harshini Srinath
63a7649179 Update privileged.sv 
Program clean up
 2023-06-12 20:26:07 -07:00
Harshini Srinath
d2a41a6422 Update csru.sv 
Program clean up
 2023-06-12 20:21:55 -07:00
Harshini Srinath
6866a9c541 Update csrsr.sv 
Program clean up
 2023-06-12 20:19:47 -07:00
Harshini Srinath
fbdf76629f Update csrsr.sv 
Program clean up
 2023-06-12 20:15:29 -07:00
Harshini Srinath
120cde2aea Update csrs.sv 
Program clean up
 2023-06-12 19:53:41 -07:00
Harshini Srinath
6305412d57 Update csrm.sv 
Program clean up
 2023-06-12 19:42:45 -07:00
Harshini Srinath
61d50a18da Update csri.sv 
Program clean up
 2023-06-12 19:32:04 -07:00
Harshini Srinath
02a11278fc Update csrc.sv 
Program clean up
 2023-06-12 19:03:34 -07:00