1038 Commits

Author	SHA1	Message	Date
David Harris	1a6fb2fad9	Forgot to save cacheway merge	2021-10-26 08:38:13 -07:00
David Harris	79c1395967	merging changes	2021-10-26 08:34:36 -07:00
David Harris	44de52a05a	Synchronous reset in non-flop blocks	2021-10-26 08:30:35 -07:00
Ross Thompson	09b3549efd	Fixed another critical path in the caches.	2021-10-25 22:05:11 -05:00
Ross Thompson	cb7015a690	Fixed the timing issue in the cache replacement polcy.	2021-10-25 18:00:23 -05:00
Ross Thompson	6c92d3267f	Fixed bug with the changes to sram1rw.	2021-10-25 16:11:41 -05:00
Ross Thompson	c963ea1a64	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-10-25 15:36:21 -05:00
Ross Thompson	694b3fbb6f	Possible fix for critical path timing in caches.	2021-10-25 15:33:33 -05:00
bbracker	2c9c9328a9	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-10-25 12:25:37 -07:00
David Harris	14e6d2c576	Converted flops to synchronous reset now that reset signal is synchronized	2021-10-25 11:49:20 -07:00
David Harris	47124f36c8	Added synchronizer to reset	2021-10-25 10:05:41 -07:00
Ross Thompson	ebef47b1c9	Modified the cache's sram model so if it used to synthesize flip flops it terminates the read critical path at the address's input rather than the output read data.	2021-10-24 21:21:49 -05:00
bbracker	eb9740bc31	manually resolved git merge conflicts in testbench linux after checkpointing	2021-10-24 15:02:19 -07:00
Ross Thompson	87aaec3b6c	Partial cleanup of unused signals in caches and bpred.	2021-10-24 15:04:20 -05:00
bbracker	dcd4d9dd9f	add checkpointing to linux testbench	2021-10-24 06:47:35 -07:00
David Harris	106982e493	more lsu/ifu lint cleanup	2021-10-23 12:10:13 -07:00
David Harris	8b1dc81d34	more lsu/ifu lint cleanup	2021-10-23 12:00:32 -07:00
David Harris	88b2d9e687	lsu/ifu lint cleanup	2021-10-23 11:41:20 -07:00
David Harris	d0aa6911ff	random lint cleanup	2021-10-23 11:24:36 -07:00
David Harris	bb4ad264ce	IEU cleanup	2021-10-23 11:13:28 -07:00
David Harris	b6bb33ecef	lint cleanup	2021-10-23 11:03:28 -07:00
David Harris	5e961973cb	IEU lint cleanup	2021-10-23 10:51:53 -07:00
David Harris	708b914a65	Lint cleanup from wallypipeliendhart	2021-10-23 10:29:52 -07:00
David Harris	817795f619	Lint cleanup: ahblite, ifu, hart	2021-10-23 10:12:33 -07:00
David Harris	2abec36221	Lint cleanup	2021-10-23 09:58:52 -07:00
David Harris	6ae9aa7d80	lint cleanup: FPU and privileged	2021-10-23 09:41:24 -07:00
David Harris	80d2b9bc0d	subword read and csrc lint cleanup	2021-10-23 09:29:15 -07:00
David Harris	0eabd0ecc2	FMA and CSRC lint cleanup	2021-10-23 09:20:24 -07:00
David Harris	5235e61d9e	Lint cleanup	2021-10-23 09:06:21 -07:00
David Harris	bf3eb7b814	update scripts for handling src/*/* subdirectories	2021-10-23 08:54:29 -07:00
David Harris	7732d38c36	lint cleaning and moved files into subdirectories	2021-10-23 08:53:32 -07:00
David Harris	ff409d4fe7	Lint cleanup	2021-10-23 08:39:21 -07:00
David Harris	8b854bb1c2	Cleaned up LINT erors	2021-10-23 06:28:49 -07:00
David Harris	5142bfd624	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-10-23 06:15:49 -07:00
David Harris	3407b63c8a	Added -lint flag to vsim. Cleaned some lint errors. Moved lint-wally to regression directory for convenience.	2021-10-23 06:15:26 -07:00
James E. Stine	a60e19dc3f	Modify register before fpdivsqrt to be synthesizable for FPGAs and better in tune for ASIC clocking	2021-10-22 13:41:50 -05:00
Katherine Parry	00cc1e0c5c	put the FMA priority encoders into their own module	2021-10-22 10:03:12 -07:00
James E. Stine	0e0a107a98	Get rid of lint warning - still need more testing though	2021-10-21 15:19:22 -05:00
James E. Stine	49721a169b	Clean up some FPU and add pipelined fpdivsqrt to fpu.sv	2021-10-21 13:52:12 -05:00
James E. Stine	129ef03b2d	Fix fpdivsqrt lint error on CPA for convergence	2021-10-20 17:46:13 -05:00
David Harris	687703f0d8	removed .* from wallypipeliendsoc	2021-10-20 13:49:18 -07:00
James E. Stine	7536e0a2ee	Added pipelined version of fpdivsqrt as well as analysis of fpdivsqrt to cut multiplier down to 60bits.	2021-10-20 12:00:41 -05:00
James E. Stine	ed179b0bd9	Some more sanitization but will pass to legal to determine if okay on version - it is substantially different in some ways but not a legal expert on this	2021-10-19 12:09:43 -05:00
James E. Stine	b65a4bd040	Modify DW02_multp to properly list the correct number of bits at the output (i.e., 2*WIDTH + 2).	2021-10-19 11:58:06 -05:00
David Harris	8d08ca6a1e	Changed some flops to settable	2021-10-18 17:05:29 -07:00
David Harris	df0b65e483	replaced flopenl with flopenr when clearing to 0	2021-10-18 16:53:18 -07:00
David Harris	d0b9ebd2ef	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-10-18 15:44:31 -07:00
David Harris	47f7a5db9c	Fixed multiplier and pointed arch tests to new path in addins	2021-10-18 15:43:59 -07:00
Ross Thompson	d8d414665c	fixed issues with dc shell not liking modules with parameters without default values.	2021-10-18 17:24:15 -05:00
James E. Stine	d895fd7ee5	Sanitization some more on mult_cs.sv	2021-10-18 05:24:16 -05:00