Jacob Pease
|
11ca2567b8
|
Merge branch 'main' of github.com:openhwgroup/cvw into spiboot
|
2024-08-06 17:09:39 -05:00 |
|
Jacob Pease
|
8b85a5c34a
|
SD card is now mountable on the fpga. The relevant files have been added. The most important changes are in the buildroot linux configuration and device tree.
|
2024-08-06 16:57:57 -05:00 |
|
Jacob Pease
|
bd07a60c07
|
Updated wally source files for zsbl testing.
|
2024-08-02 15:33:57 -05:00 |
|
Jacob Pease
|
02bb9b0b8b
|
Fixed SDCCLK name discrepency.
|
2024-07-24 22:48:31 -05:00 |
|
Rose Thompson
|
5381e1f395
|
Updated for a better ILA rvvi debugger.
|
2024-07-22 17:44:04 -05:00 |
|
Rose Thompson
|
3c06556833
|
Updated the verilog-ethernet repo to remove most of the warnings. Updated the fpga constraints so the ILA is more useful when using RVVI.
|
2024-07-22 16:12:06 -05:00 |
|
Jacob Pease
|
4585ad8891
|
Added new SDC clock constraint.
|
2024-07-22 13:05:16 -05:00 |
|
Rose Thompson
|
24609f0b7f
|
Now have configurations to switch between supporting RVVI over ethernet.
|
2024-07-22 10:51:13 -05:00 |
|
Rose Thompson
|
00840e4893
|
Made the fpga top level configurable between rvvi synth and not.
|
2024-07-19 17:35:30 -05:00 |
|
Rose Thompson
|
0d40b8c933
|
Cleanup in prep to merge the rvvi branch into main.
|
2024-07-19 15:48:20 -05:00 |
|
Ross Thompson
|
f0096f5a43
|
Yay. It's actually working! The FPGA/ImperasDV hybrid is working.
|
2024-07-10 15:10:37 -05:00 |
|
Ross Thompson
|
e6dc962d11
|
Yay! the trigger is correctly working now!
|
2024-07-10 12:05:10 -05:00 |
|
Ross Thompson
|
ccf4bb8ddc
|
Maybe have the incircuit trigger working.
|
2024-06-26 16:15:46 -07:00 |
|
Ross Thompson
|
612a281f62
|
Added module to receive ethernet frame and trigger the ila.
|
2024-06-26 11:05:31 -07:00 |
|
Ross Thompson
|
563980443a
|
Merge branch 'main' into rvvi
|
2024-06-10 18:10:23 -07:00 |
|
Rose Thompson
|
6a4c8667df
|
Added new signals to ILA to debug the RVVI tracer.
The tracer appears to be stuck and the CPU is never getting out of (into reset).
|
2024-05-30 16:43:25 -05:00 |
|
Jacob Pease
|
7ecd1c7d5f
|
The vcu108 works again. Added renumber.py script that renumbers probes in an xdc file.
|
2024-05-30 15:48:27 -05:00 |
|
Rose Thompson
|
9703055758
|
The FPGA is synthesizing with the rvvi and ethernet hardware.
|
2024-05-30 15:37:17 -05:00 |
|
Rose Thompson
|
26cd22c388
|
Replaced fpga's verilog top with system verilog.
|
2023-12-15 13:42:52 -06:00 |
|
Rose Thompson
|
34631c54d3
|
Get's the fpga building again after the git history rewrite.
|
2023-12-14 17:08:25 -06:00 |
|
Rose Thompson
|
cdd21d6635
|
Added menvcfg to debugger for checking what linux has configured.
|
2023-11-19 13:44:22 -06:00 |
|
Ross Thompson
|
055e00b8ac
|
Pushed vcu118 to 71MHz.
|
2023-08-25 17:04:50 -05:00 |
|
Jacob Pease
|
2bf6207919
|
Added help option to the flash-sd script.
|
2023-08-22 13:37:33 -05:00 |
|
Ross Thompson
|
a16cde3dc6
|
Removed unused file.
|
2023-08-21 15:12:59 -05:00 |
|
Ross Thompson
|
1e0f1aeeac
|
Updated artyA7 debugger to match book.
|
2023-08-21 14:35:42 -05:00 |
|
Ross Thompson
|
fb1c1a1832
|
Added new signals to the vcu118 debug4 ila to help figure out why the new linux build's hptw fails.
|
2023-08-02 16:14:04 -05:00 |
|
Ross Thompson
|
5790dafdce
|
Fixed constraint in VCU118.
|
2023-08-02 13:02:28 -05:00 |
|
Ross Thompson
|
c4ae856f92
|
Clean up vcu118 synth scripts.
|
2023-08-01 14:39:33 -05:00 |
|
Ross Thompson
|
06efd2cdde
|
Pushed performance of arty a7 to 23Mhz.
|
2023-07-31 14:13:09 -05:00 |
|
Ross Thompson
|
49b87d4550
|
Merge branch 'main' of github.com:ross144/cvw
|
2023-07-24 10:47:05 -05:00 |
|
Ross Thompson
|
065e5e98c9
|
Improved timing constraints for arty a7 to push clock speed to 20Mhz.
|
2023-07-24 10:46:49 -05:00 |
|
Ross Thompson
|
ab6ef5bb58
|
At least it simulates and gets through fpga elaboration.
|
2023-07-21 18:40:26 -05:00 |
|
Ross Thompson
|
a89a1e675c
|
Merge branch 'boot' into mergeBoot
Merges Jacob's new sdc controller into wally.
|
2023-07-21 17:43:45 -05:00 |
|
Ross Thompson
|
d04d2afed2
|
Modified the LSU/IFU and caches to improve critical path. Arty A7 went from 15 to 17Mhz. I believe we can push all the way to 20+Mhz with relatively little effort. Along the way I'm fixing up the scripts build the linux images for the flash card.
|
2023-07-21 13:06:27 -05:00 |
|
Jacob Pease
|
380d96b359
|
Working new boot process. Buildroot package for sdc.
|
2023-07-20 14:15:59 -05:00 |
|
Ross Thompson
|
2752e5de4c
|
Fixed a bunch of timing constraints for the arty a7 board.
|
2023-07-19 17:08:16 -05:00 |
|
Ross Thompson
|
7aecd72c35
|
Fpga does not correctly boot linux. I think the solution here is to revert out all substantive changes except for parameterization and then add them back in one at a time. This is necessary because the parameterization is not completed in one contiguous group of commits.
|
2023-06-22 12:55:49 -05:00 |
|
Ross Thompson
|
a8f11dcad0
|
FPGA updates.
|
2023-06-20 11:11:34 -05:00 |
|
Ross Thompson
|
0423d7df82
|
I think the fpga is building again, but the debugger script needs to be updated. For some reason the nets are not present despite being marked debug.
|
2023-06-16 17:00:27 -05:00 |
|
Jacob Pease
|
40f81d5da6
|
The Vivado-RISC-V SDC works. Wally is now booting through it.
|
2023-05-26 15:42:33 -05:00 |
|
Ross Thompson
|
b13fe870cf
|
Yeah We boot linux on the arty a7!
|
2023-04-19 11:17:33 -05:00 |
|
Ross Thompson
|
1fec535b32
|
Fixed the reset for Arty A7 and now partially boots. Copies flash card to dram.
but the data is wrong.
|
2023-04-19 10:35:18 -05:00 |
|
Ross Thompson
|
367bd0f8dc
|
More debug stuff.
|
2023-04-18 16:00:10 -05:00 |
|
Ross Thompson
|
668e69fdc9
|
Added more signals to debugger in hopes I can figure out why the mig is not responding.
|
2023-04-18 15:51:52 -05:00 |
|
Jacob Pease
|
2839f4f41a
|
AHB triggers write, but AXI side doesn't update.
|
2023-04-18 15:23:22 -05:00 |
|
Ross Thompson
|
3588c53e66
|
It's almost working.
|
2023-04-18 14:24:59 -05:00 |
|
Ross Thompson
|
deb0bfc24d
|
Improved constraints and set ddr3 voltage to correct 1.35V. This voltage is only for synthesis. However I'm concerned because the gui did not let me select 1.35V.
|
2023-04-17 20:05:59 -05:00 |
|
Ross Thompson
|
777bec2e24
|
Fixed timing constraint issue.
|
2023-04-17 19:53:43 -05:00 |
|
Ross Thompson
|
b2b30936be
|
Found the DDR3 memory is not ready when issuing the first store.
|
2023-04-17 19:33:13 -05:00 |
|
Ross Thompson
|
fbbba0e5c2
|
Finally we are building the fpga and can view the ila. we are getting out of reset, but we are stuck at PCM = 10b8.
|
2023-04-17 18:39:25 -05:00 |
|