mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
SD card is now mountable on the fpga. The relevant files have been added. The most important changes are in the buildroot linux configuration and device tree.
This commit is contained in:
Jacob Pease
parent
173562d6f4
commit
8b85a5c34a
@ -35,6 +35,7 @@ set_property IOSTANDARD LVCMOS33 [get_ports {GPO[2]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {GPO[1]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {GPO[0]}]
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set_max_delay -to [get_ports {GPO[*]}] 20.000
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set_output_delay -clock [get_clocks clk_out3_xlnx_mmcm] -min -add_delay 0.000 [get_ports {GPO[*]}]
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set_output_delay -clock [get_clocks clk_out3_xlnx_mmcm] -max -add_delay 0.000 [get_ports {GPO[*]}]
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@ -106,18 +107,21 @@ set_property -dict {PACKAGE_PIN F4 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {
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set_property -dict {PACKAGE_PIN F3 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCCLK}]
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set_property -dict {PACKAGE_PIN D3 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCCmd}]
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set_property -dict {PACKAGE_PIN H2 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCCD}]
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set_property -dict {PACKAGE_PIN G2 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCWP}]
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set_input_delay -clock [get_clocks SPISDCClock] -min -add_delay 2.500 [get_ports {SDCCS}]
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set_input_delay -clock [get_clocks SPISDCClock] -max -add_delay 21.000 [get_ports {SDCCS}]
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set_input_delay -clock [get_clocks SPISDCClock] -max -add_delay 10.000 [get_ports {SDCCS}]
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set_input_delay -clock [get_clocks SPISDCClock] -min -add_delay 2.500 [get_ports {SDCIn}]
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set_input_delay -clock [get_clocks SPISDCClock] -max -add_delay 21.000 [get_ports {SDCIn}]
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set_input_delay -clock [get_clocks SPISDCClock] -max -add_delay 10.000 [get_ports {SDCIn}]
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set_output_delay -clock [get_clocks SPISDCClock] -min -add_delay 2.000 [get_ports {SDCCmd}]
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set_output_delay -clock [get_clocks SPISDCClock] -max -add_delay 6.000 [get_ports {SDCCmd}]
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set_output_delay -clock [get_clocks SPISDCClock] 0.000 [get_ports SDCCLK]
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#set_multicycle_path -from [get_pins xlnx_ddr3_c0/u_xlnx_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/init_calib_complete_reg/C] -to [get_pins xlnx_proc_sys_reset_0/U0/EXT_LPF/lpf_int_reg/D] 10
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set_max_delay -datapath_only -from [get_pins xlnx_ddr3_c0/u_xlnx_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/init_calib_complete_reg/C] -to [get_pins xlnx_proc_sys_reset_0/U0/EXT_LPF/lpf_int_reg/D] 20.000
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@ -47,6 +47,7 @@ module fpgaTop
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output SDCCmd,
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output SDCCS,
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input SDCCD,
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input SDCWP,
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// Memory signals
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inout [15:0] ddr3_dq,
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@ -194,7 +195,7 @@ module fpgaTop
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wire mmcm1_locked;
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assign GPIOIN = {28'b0, GPI};
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assign GPIOIN = {25'b0, SDCCD, SDCWP, 1'b0, GPI};
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assign GPO = GPIOOUT[4:0];
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assign ahblite_resetn = peripheral_aresetn;
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assign cpu_reset = bus_struct_reset;
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@ -159,7 +159,7 @@ void copyFlash(QWORD address, QWORD * Dst, DWORD numBlocks) {
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/* print_uart("\r\n"); */
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// Intialize the SD card
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init_sd(SYSTEMCLOCK, 3000000);
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init_sd(SYSTEMCLOCK, 5000000);
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ret = gpt_load_partitions();
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}
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@ -102,7 +102,7 @@ $(IMAGES)/busybox:
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# Generating new Buildroot directories --------------------------------
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# This directive should be run as: make install BUILDROOT=path/to/buildroot
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download: $(BUILDROOT)/package/fpga-axi-sdc $(WALLYBOARD)
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download: $(WALLYBOARD)
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cp $(WALLYBOARD)/main.config $(BUILDROOT)/.config
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# CONFIG DEPENDENCIES 2023.05.1 ---------------------------------------
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@ -2,7 +2,7 @@
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# Automatically generated file; DO NOT EDIT.
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# Linux/riscv 6.6.0 Kernel Configuration
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#
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CONFIG_CC_VERSION_TEXT="riscv64-buildroot-linux-gnu-gcc.br_real (Buildroot 2023.05.3-dirty) 12.3.0"
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CONFIG_CC_VERSION_TEXT="riscv64-buildroot-linux-gnu-gcc.br_real (Buildroot 2023.05.3) 12.3.0"
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CONFIG_CC_IS_GCC=y
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CONFIG_GCC_VERSION=120300
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CONFIG_CLANG_VERSION=0
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@ -1042,7 +1042,7 @@ CONFIG_MMC_BLOCK_MINORS=8
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#
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# CONFIG_MMC_DEBUG is not set
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# CONFIG_MMC_SDHCI is not set
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# CONFIG_MMC_SPI is not set
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CONFIG_MMC_SPI=y
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# CONFIG_MMC_DW is not set
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# CONFIG_MMC_USDHI6ROL0 is not set
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# CONFIG_MMC_CQHCI is not set
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@ -1455,7 +1455,7 @@ CONFIG_CRYPTO_HASH2=y
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# CONFIG_CRYPTO_POLY1305 is not set
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# CONFIG_CRYPTO_RMD160 is not set
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# CONFIG_CRYPTO_SHA1 is not set
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# CONFIG_CRYPTO_SHA256 is not set
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CONFIG_CRYPTO_SHA256=y
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# CONFIG_CRYPTO_SHA512 is not set
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# CONFIG_CRYPTO_SHA3 is not set
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# CONFIG_CRYPTO_SM3_GENERIC is not set
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@ -1527,13 +1527,14 @@ CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
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CONFIG_CRYPTO_LIB_POLY1305_RSIZE=1
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# CONFIG_CRYPTO_LIB_POLY1305 is not set
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# CONFIG_CRYPTO_LIB_CHACHA20POLY1305 is not set
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CONFIG_CRYPTO_LIB_SHA256=y
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# end of Crypto library routines
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# CONFIG_CRC_CCITT is not set
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CONFIG_CRC16=y
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# CONFIG_CRC_T10DIF is not set
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# CONFIG_CRC64_ROCKSOFT is not set
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# CONFIG_CRC_ITU_T is not set
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CONFIG_CRC_ITU_T=y
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CONFIG_CRC32=y
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# CONFIG_CRC32_SELFTEST is not set
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CONFIG_CRC32_SLICEBY8=y
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@ -1542,7 +1543,7 @@ CONFIG_CRC32_SLICEBY8=y
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# CONFIG_CRC32_BIT is not set
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# CONFIG_CRC64 is not set
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# CONFIG_CRC4 is not set
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# CONFIG_CRC7 is not set
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CONFIG_CRC7=y
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# CONFIG_LIBCRC32C is not set
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# CONFIG_CRC8 is not set
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# CONFIG_RANDOM32_SELFTEST is not set
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@ -1599,7 +1600,7 @@ CONFIG_PRINTK_TIME=y
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# CONFIG_STACKTRACE_BUILD_ID is not set
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CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7
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CONFIG_CONSOLE_LOGLEVEL_QUIET=4
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CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
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CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7
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# CONFIG_BOOT_PRINTK_DELAY is not set
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# CONFIG_DYNAMIC_DEBUG is not set
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# CONFIG_DYNAMIC_DEBUG_CORE is not set
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@ -5,11 +5,11 @@
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#size-cells = <0x02>;
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compatible = "wally-virt";
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model = "wally-virt,qemu";
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chosen {
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linux,initrd-end = <0x85c43a00>;
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linux,initrd-start = <0x84200000>;
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bootargs = "root=/dev/vda ro console=ttyS0,115200";
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bootargs = "root=/dev/vda ro console=ttyS0,115200 loglevel=7";
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stdout-path = "/soc/uart@10000000";
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};
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@ -51,6 +51,25 @@
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compatible = "simple-bus";
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ranges;
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refclk: refclk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <0x1312D00>;
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clock-output-names = "xtal";
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};
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gpio0: gpio@10060000 {
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compatible = "sifive,gpio0";
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interrupt-parent = <0x03>;
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interrupts = <3>;
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reg = <0x00 0x10060000 0x00 0x1000>;
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reg-names = "control";
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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uart@10000000 {
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interrupts = <0x0a>;
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interrupt-parent = <0x03>;
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@ -70,18 +89,24 @@
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#address-cells = <0x00>;
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};
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mmc@13000 {
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interrupts = <0x14>;
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compatible = "riscv,axi-sd-card-1.0";
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reg = <0x00 0x13000 0x00 0x7F>;
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fifo-depth = <256>;
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bus-width = <4>;
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spi@13000 {
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compatible = "sifive,spi0";
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interrupt-parent = <0x03>;
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clock = <0x1312D00>;
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max-frequency = <0x1312D00>;
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cap-sd-highspeed;
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cap-mmc-highspeed;
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no-sdio;
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interrupts = <0x14>;
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reg = <0x0 0x13000 0x0 0x1000>;
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reg-names = "control";
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clocks = <&refclk>;
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#address-cells = <1>;
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#size-cells = <0>;
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mmc@0 {
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compatible = "mmc-spi-slot";
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reg = <0>;
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spi-max-frequency = <5000000>;
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voltage-ranges = <3300 3300>;
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disable-wp;
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// gpios = <&gpio0 6 1>;
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};
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};
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clint@2000000 {
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