Ross Thompson 612a281f62 Added module to receive ethernet frame and trigger the ila.		2024-06-26 11:05:31 -07:00
..
artyddr3.ucf
constraints-ArtyA7.xdc	The FPGA is synthesizing with the rvvi and ethernet hardware.	2024-05-30 15:37:17 -05:00
constraints-vcu108.xdc
constraints-vcu118.xdc	Pushed vcu118 to 71MHz.	2023-08-25 17:04:50 -05:00
debug2.xdc
debug4.xdc	Added help option to the flash-sd script.	2023-08-22 13:37:33 -05:00
debug6.xdc	The vcu108 works again. Added renumber.py script that renumbers probes in an xdc file.	2024-05-30 15:48:27 -05:00
marked_debug_all.txt	The vcu108 works again. Added renumber.py script that renumbers probes in an xdc file.	2024-05-30 15:48:27 -05:00
marked_debug_small.txt	Updated artyA7 debugger to match book.	2023-08-21 14:35:42 -05:00
marked_debug.txt	Get's the fpga building again after the git history rewrite.	2023-12-14 17:08:25 -06:00
small-debug.xdc	Added module to receive ethernet frame and trigger the ila.	2024-06-26 11:05:31 -07:00
vcu-small-debug.xdc