David Harris
db5f3c15a4
FPU divider working with execute stage stall
2022-12-02 11:11:53 -08:00
Ross Thompson
3442b04f9e
Properly flush cacheLRU.
2022-12-01 17:32:58 -06:00
Ross Thompson
e403800ce8
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-12-01 11:47:54 -06:00
Ross Thompson
5025664cb0
Removed unused port on cacheway.
2022-12-01 11:47:48 -06:00
David Harris
28996d0b12
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-12-01 08:15:51 -08:00
David Harris
1bd639be6d
code cleanup
2022-12-01 08:15:48 -08:00
Ross Thompson
e6bd86f4fa
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-11-30 17:19:04 -06:00
David Harris
4ddc8fd603
signal sufixes in integer division
2022-11-30 15:15:37 -08:00
Ross Thompson
a6355b1dcb
More optimization.
2022-11-30 11:26:48 -06:00
Ross Thompson
0aa7ce0b24
Removed reset on dirty cache bits.
2022-11-30 11:04:37 -06:00
Ross Thompson
cedb234013
Turns out the merge of dirty and tag bits is complicated by the need to have byte write enables rather than bit write enables. Putting on hold for now.
2022-11-30 11:01:25 -06:00
Ross Thompson
0454eb95ad
Preparing to merge dirty and tag srams.
2022-11-30 10:40:48 -06:00
Ross Thompson
de538d1c2f
Intermediate commit. Replaced flip flop dirty bit array with sram.
2022-11-30 00:08:31 -06:00
Ross Thompson
453ea36512
Optimization of cacheway.
2022-11-29 18:30:47 -06:00
Ross Thompson
fbf543bf57
Updated HPTW to route access faults generated by the HPTW to the original access type either instruction access fault, load access fault or store access fault.
2022-11-29 17:19:31 -06:00
Ross Thompson
b5718c9baa
Fixed a bug with the replacement policy. It was updating the wrong set on load hits.
2022-11-29 14:51:09 -06:00
Ross Thompson
96cc4c7ebe
Cleaned up the wavefile and added logic to linearly populate the LRU before all ways are filled.
2022-11-29 14:09:48 -06:00
Ross Thompson
78acd40424
Renamed signals in the cache.
2022-11-29 10:52:40 -06:00
Ross Thompson
6dd5668d21
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-11-22 18:07:32 -06:00
cturek
bdb9e24a66
Almost done with Int division
2022-11-22 22:22:59 +00:00
Ross Thompson
279f5bc615
Cleanup cacheLRU.
2022-11-22 14:59:01 -06:00
Ross Thompson
e1dbe58632
File name change for cachereplacement policy to cacheLRU
2022-11-20 22:35:02 -06:00
Ross Thompson
4e926ba4cf
Signal name changes for LRU.
2022-11-20 22:31:36 -06:00
Ross Thompson
00218d559f
Missing a file. Last commit will fail.
2022-11-17 17:45:41 -06:00
Ross Thompson
0106777f02
Finally have the correct replacement policy implementation.
2022-11-17 17:36:37 -06:00
Ross Thompson
faa13a96e0
I found the issue with the cache changes. FlushW is not asserted for all TrapM. Ecall and Ebreak don't flush the W stage. However the ifu's bus controllable must disable the BusRW for all traps.
2022-11-16 15:38:37 -06:00
Ross Thompson
22ad49eef2
Progress on the cache replacement policy implementation.
2022-11-16 15:35:34 -06:00
Ross Thompson
0796cd92fc
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-11-16 12:42:29 -06:00
Ross Thompson
42111db671
Oups found a bug with my cache changes. I took TrapM out of the logic path for selecting the cache's address CAdr (previously RAdr) to improve the critical path. This is fine for the dcache because both the E and M stages are flushed. However for the ICache only F is flushed. PCNextF is valid and points to XTVEC so the cache must take NextAdr rather than PAdr as CAdr.
2022-11-16 12:36:58 -06:00
David Harris
59335ac70f
comment cleanup
2022-11-16 10:23:20 -08:00
David Harris
be9c618c94
Renamed DivBusy to FDivBusyE in FPU
2022-11-16 10:13:27 -08:00
David Harris
128cc86254
Moved DivStartE to fdivsqrtfsm
2022-11-16 10:00:07 -08:00
Ross Thompson
1f21a2bab1
Created improved cache replacement policy implementation. This version is generic and works for any number of ways. Not fully tested and is currently commented out.
2022-11-16 11:15:34 -06:00
cturek
ffd03e9548
Attempt to fix FPGA synth errors
2022-11-15 20:34:28 +00:00
cturek
98b66aab9f
Fixed lint errors in postprocessing
2022-11-15 20:31:23 +00:00
Ross Thompson
3df51716b1
Fixed a bug with the hptw configuration not correctly avoiding UPDATE_PTE state.
2022-11-14 16:02:20 -06:00
Ross Thompson
b53f8eceef
Renamed Flush to FlushStage in the cache.
2022-11-14 14:11:05 -06:00
Ross Thompson
284b97aff6
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-11-14 13:48:56 -06:00
David Harris
6372139af4
Removed comment about nonexistent possible bug
2022-11-14 09:56:33 -08:00
David Harris
06dbed92c8
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-11-14 09:52:24 -08:00
David Harris
f9202187ba
Removed comment about nonexistent possible bug
2022-11-14 09:52:21 -08:00
Ross Thompson
13e6f7d80b
Changed names of cache signals.
2022-11-13 21:36:12 -06:00
cturek
abaa33b92a
Added majority of combinational logic
2022-11-14 00:06:38 +00:00
cturek
6740d77b63
Added Quotient/Remainder calcs to normal termination
2022-11-13 23:44:34 +00:00
cturek
12e3646153
Added flops for n and m, added B=0 signal
2022-11-13 23:02:43 +00:00
cturek
f10700e666
Added A<B signal to fdivsqrt, started postprocessing merge
2022-11-13 22:40:26 +00:00
Ross Thompson
9d7ba19fe1
Changed IMWriteDataM to IHWriteDataM.
2022-11-13 12:27:48 -06:00
Ross Thompson
421c6f9c48
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
...
hazard was not a straight forward merge. I changed the way the LSU and IFU generate IFUStallF and LSUStallM. They need to be suppressed by TrapM now.
2022-11-13 12:25:22 -06:00
David Harris
84c4558641
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-11-13 04:23:26 -08:00
David Harris
879e62912b
HPTW cleanup
2022-11-13 04:23:23 -08:00
David Harris
2ebdfa3f68
Comments about division hazards
2022-11-13 04:17:37 -08:00
Ross Thompson
54544ae251
Moved all remaining bus logic from the LSU into ahbcacheinterface.
2022-11-11 14:30:32 -06:00
cturek
4a8661649c
Added integer step counter to fsm
2022-11-11 00:23:25 +00:00
Ross Thompson
c028306ba3
Fixed name change in hptw.
2022-11-10 16:13:31 -06:00
Ross Thompson
40367eaf45
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-11-10 15:46:25 -06:00
Ross Thompson
8658a25218
Renamed Word to Beat for ahbcacheinterface.
2022-11-09 17:52:50 -06:00
Ross Thompson
028e2b0f91
Renamed CACHE_EVICT to CACHE_WRITEBACK.
2022-11-09 17:43:06 -06:00
cturek
b723e16893
Fixed asign and bsign
2022-11-09 18:41:26 +00:00
Ross Thompson
be8e0eee1b
Removed TrapM from the LSU and IFU. TrapM is replaced with FlushW for both. (Don't like this for the IFU).
...
FlushW prevents writting the cache, dtim, and bus state. FlushW still gates HTRANS.
FlushW does not impact the mealy outputs of the cache and bus FSMs and hazard is updated to
not stall W if we get a trap.
2022-11-07 15:50:55 -06:00
David Harris
f7b94c12fc
Moved lsuvirtmem muxes into hptw
2022-11-07 11:13:34 -08:00
Ross Thompson
d4f4950d2c
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-11-07 09:10:51 -06:00
cturek
d571b5f9a5
propagated otfc swap to Rad2 and 4 qslc
2022-11-06 23:32:38 +00:00
Ross Thompson
e7d24609cd
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-11-06 17:22:25 -06:00
cturek
54f09f3616
Added conditional OTFC swap for simplified int postprocessing
2022-11-06 23:09:09 +00:00
cturek
c3e635c788
Finished Int Preprocessinggit add ../src/fpu/fdivsqrt/fdivsqrtpreproc.sv
2022-11-06 22:40:21 +00:00
cturek
a49ea2a16d
Added n and rightshiftx
2022-11-06 22:31:48 +00:00
cturek
350d4d254f
p calculation
2022-11-06 22:24:21 +00:00
cturek
83051a5351
Changed lzc names, started int/fp size merge in preproc
2022-11-06 22:21:35 +00:00
cturek
2cbe2fd70b
Added n, p, and m signals between fdivsqrt submodules. Added w64 and mdue to divsqrt testbench.
2022-11-06 22:08:18 +00:00
cturek
6bc4c1318e
Added new macros for int div preprocessing, added p, n, and rightshiftx logic
2022-11-06 21:53:48 +00:00
David Harris
60cfa0d69c
HPTW cleanup
2022-11-04 15:21:09 -07:00
Ross Thompson
44ee31a7f6
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-11-04 13:30:08 -05:00
cturek
06a9305766
renamed remOp to RemOp
2022-11-03 22:37:25 +00:00
cturek
e37f564e84
Added rem/div operation to postprocessor
2022-11-02 17:49:40 +00:00
Ross Thompson
44171c342d
Reduced complexity of logic supressing cache operations.
2022-11-01 15:23:24 -05:00
cturek
e8d7607e87
Added buffered signals for int/fp
2022-10-28 21:47:24 +00:00
cturek
9f41e57f03
Config Cleanup
2022-10-27 22:38:56 +00:00
Ross Thompson
dc3a9f2342
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-10-26 14:48:50 -05:00
Ross Thompson
403434580d
Fixed the uart transmit fifo overrun bug.
2022-10-26 14:48:09 -05:00
cturek
7301fc7f18
small signal cleanup
2022-10-26 18:42:49 +00:00
cturek
6caf7bb7e2
abs for int inputs
2022-10-26 16:18:05 +00:00
cturek
ec4646b412
Added signed division to fdivsqrt
2022-10-26 16:13:41 +00:00
Jacob Pease
160ca366c8
Added PLIC signals for debugging on FPGA.
2022-10-25 13:57:09 -05:00
cturek
ff7d6b2932
Started Integer Preprocessing
2022-10-25 17:48:43 +00:00
Ross Thompson
9ba487c323
Setup to run with both the vcu108 and vcu118 boards. Set the parameters in the Makefile.
2022-10-24 15:38:39 -05:00
Ross Thompson
7244ca1e7b
Bit width error.
2022-10-24 13:48:47 -05:00
Ross Thompson
51408c620e
Found a way to remove the interlock fsm. Dramatically reducing the complexity of virtual memory and page table walks.
2022-10-23 13:46:50 -05:00
Ross Thompson
775309165b
Small cleanup of interlockfsm.
2022-10-22 16:29:51 -05:00
Ross Thompson
6696624971
comment updates.
2022-10-22 16:28:44 -05:00
Ross Thompson
12c5525807
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-10-22 16:27:30 -05:00
Ross Thompson
4db912678d
Changed FDivBusyE to stall the whole pipeline. Any instruction in the Executation which depended on the output of an instruction in the writeback stage would be lost if the back end of the pipelined advanced. The solution is to stall the whole pipeline.
2022-10-22 16:27:20 -05:00
Jacob Pease
b1170ec7a2
Extended rxfifotimeout count to actually be 4 characters long.
2022-10-20 17:35:49 -05:00
Ross Thompson
2c5847b01f
Moving interlockfsm changes to a temporary branch.
...
reduced complexity of cache mux controls.
2022-10-19 15:08:23 -05:00
Ross Thompson
9cadd4c6ec
Broken don't use this state.
2022-10-19 14:31:22 -05:00
Ross Thompson
c6a9b17918
Noted possible bug with endianness during hptw.
...
Minor complexity reduction in interlockfsm. I think there is a lot of room to simplify.
2022-10-19 12:20:19 -05:00
Ross Thompson
d4c5440f25
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-10-18 15:06:09 -05:00
Ross Thompson
92accfb1a6
Updated uart settings and fpga wave config.
2022-10-18 15:05:33 -05:00
Ross Thompson
47608df73e
Possible fix for interrupt during a floating point divide.
2022-10-18 15:04:21 -05:00
Ross Thompson
65c2fe294a
Merged cacheable with seluncachedadr.
2022-10-17 13:29:21 -05:00
amaiuolo
56455bb9ad
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
2022-10-13 22:36:57 +00:00
