Ross Thompson 775309165b Small cleanup of interlockfsm.		2022-10-22 16:29:51 -05:00
..
cache	comment updates.	2022-10-22 16:28:44 -05:00
ebu	Merged cacheable with seluncachedadr.	2022-10-17 13:29:21 -05:00
fpu	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally	2022-10-13 22:36:57 +00:00
generic	changed always_ff to always in sram1p1rw to fix testbench complaint	2022-09-25 19:56:40 -07:00
hazard	Changed FDivBusyE to stall the whole pipeline. Any instruction in the Executation which depended on the output of an instruction in the writeback stage would be lost if the back end of the pipelined advanced. The solution is to stall the whole pipeline.	2022-10-22 16:27:20 -05:00
ieu	Eliminated store after store stall when no cache; simplified divshiftcalc logic.	2022-09-21 13:02:34 -07:00
ifu	Moving interlockfsm changes to a temporary branch.	2022-10-19 15:08:23 -05:00
lsu	Small cleanup of interlockfsm.	2022-10-22 16:29:51 -05:00
mmu	Modified the LSU and IFU to allow concurrent DTIM/DCACHE+BUS and IROM/ICACHE+BUS.	2022-10-05 14:51:02 -05:00
muldiv	Clean up unused signals	2022-05-12 14:49:58 +00:00
ppa	cleanup, plots for paper	2022-06-15 18:28:36 +00:00
privileged	Moving interlockfsm changes to a temporary branch.	2022-10-19 15:08:23 -05:00
uncore	Extended rxfifotimeout count to actually be 4 characters long.	2022-10-20 17:35:49 -05:00
wally	Removed unnecessary configuration conditions from subwordread sign extension/NaN boxing	2022-10-10 07:12:37 -07:00
sdc	piplined directory cleanup	2022-01-07 12:43:50 +00:00