Jacob Pease
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baad4e0fd2
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With Naiche's help, we fixed the SPI controllers clock polarity and phase settings. Added conditions to the SPI regression tests.
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2024-08-20 16:24:37 -05:00 |
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Jacob Pease
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11ca2567b8
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Merge branch 'main' of github.com:openhwgroup/cvw into spiboot
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2024-08-06 17:09:39 -05:00 |
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Jacob Pease
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8b85a5c34a
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SD card is now mountable on the fpga. The relevant files have been added. The most important changes are in the buildroot linux configuration and device tree.
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2024-08-06 16:57:57 -05:00 |
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Jacob Pease
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bd07a60c07
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Updated wally source files for zsbl testing.
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2024-08-02 15:33:57 -05:00 |
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Jacob Pease
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02bb9b0b8b
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Fixed SDCCLK name discrepency.
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2024-07-24 22:48:31 -05:00 |
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Rose Thompson
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5381e1f395
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Updated for a better ILA rvvi debugger.
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2024-07-22 17:44:04 -05:00 |
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Rose Thompson
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3c06556833
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Updated the verilog-ethernet repo to remove most of the warnings. Updated the fpga constraints so the ILA is more useful when using RVVI.
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2024-07-22 16:12:06 -05:00 |
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Jacob Pease
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4585ad8891
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Added new SDC clock constraint.
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2024-07-22 13:05:16 -05:00 |
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Rose Thompson
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24609f0b7f
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Now have configurations to switch between supporting RVVI over ethernet.
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2024-07-22 10:51:13 -05:00 |
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Rose Thompson
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00840e4893
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Made the fpga top level configurable between rvvi synth and not.
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2024-07-19 17:35:30 -05:00 |
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Rose Thompson
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0d40b8c933
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Cleanup in prep to merge the rvvi branch into main.
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2024-07-19 15:48:20 -05:00 |
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Ross Thompson
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f0096f5a43
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Yay. It's actually working! The FPGA/ImperasDV hybrid is working.
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2024-07-10 15:10:37 -05:00 |
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Ross Thompson
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e6dc962d11
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Yay! the trigger is correctly working now!
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2024-07-10 12:05:10 -05:00 |
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Ross Thompson
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ccf4bb8ddc
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Maybe have the incircuit trigger working.
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2024-06-26 16:15:46 -07:00 |
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Ross Thompson
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612a281f62
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Added module to receive ethernet frame and trigger the ila.
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2024-06-26 11:05:31 -07:00 |
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Ross Thompson
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563980443a
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Merge branch 'main' into rvvi
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2024-06-10 18:10:23 -07:00 |
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Rose Thompson
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6a4c8667df
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Added new signals to ILA to debug the RVVI tracer.
The tracer appears to be stuck and the CPU is never getting out of (into reset).
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2024-05-30 16:43:25 -05:00 |
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Jacob Pease
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7ecd1c7d5f
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The vcu108 works again. Added renumber.py script that renumbers probes in an xdc file.
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2024-05-30 15:48:27 -05:00 |
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Rose Thompson
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9703055758
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The FPGA is synthesizing with the rvvi and ethernet hardware.
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2024-05-30 15:37:17 -05:00 |
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Rose Thompson
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26cd22c388
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Replaced fpga's verilog top with system verilog.
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2023-12-15 13:42:52 -06:00 |
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Rose Thompson
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34631c54d3
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Get's the fpga building again after the git history rewrite.
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2023-12-14 17:08:25 -06:00 |
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Rose Thompson
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cdd21d6635
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Added menvcfg to debugger for checking what linux has configured.
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2023-11-19 13:44:22 -06:00 |
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Ross Thompson
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055e00b8ac
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Pushed vcu118 to 71MHz.
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2023-08-25 17:04:50 -05:00 |
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Jacob Pease
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2bf6207919
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Added help option to the flash-sd script.
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2023-08-22 13:37:33 -05:00 |
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Ross Thompson
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a16cde3dc6
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Removed unused file.
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2023-08-21 15:12:59 -05:00 |
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Ross Thompson
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1e0f1aeeac
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Updated artyA7 debugger to match book.
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2023-08-21 14:35:42 -05:00 |
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Ross Thompson
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fb1c1a1832
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Added new signals to the vcu118 debug4 ila to help figure out why the new linux build's hptw fails.
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2023-08-02 16:14:04 -05:00 |
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Ross Thompson
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5790dafdce
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Fixed constraint in VCU118.
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2023-08-02 13:02:28 -05:00 |
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Ross Thompson
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c4ae856f92
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Clean up vcu118 synth scripts.
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2023-08-01 14:39:33 -05:00 |
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Ross Thompson
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06efd2cdde
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Pushed performance of arty a7 to 23Mhz.
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2023-07-31 14:13:09 -05:00 |
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Ross Thompson
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49b87d4550
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Merge branch 'main' of github.com:ross144/cvw
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2023-07-24 10:47:05 -05:00 |
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Ross Thompson
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065e5e98c9
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Improved timing constraints for arty a7 to push clock speed to 20Mhz.
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2023-07-24 10:46:49 -05:00 |
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Ross Thompson
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ab6ef5bb58
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At least it simulates and gets through fpga elaboration.
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2023-07-21 18:40:26 -05:00 |
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Ross Thompson
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a89a1e675c
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Merge branch 'boot' into mergeBoot
Merges Jacob's new sdc controller into wally.
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2023-07-21 17:43:45 -05:00 |
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Ross Thompson
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d04d2afed2
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Modified the LSU/IFU and caches to improve critical path. Arty A7 went from 15 to 17Mhz. I believe we can push all the way to 20+Mhz with relatively little effort. Along the way I'm fixing up the scripts build the linux images for the flash card.
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2023-07-21 13:06:27 -05:00 |
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Jacob Pease
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380d96b359
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Working new boot process. Buildroot package for sdc.
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2023-07-20 14:15:59 -05:00 |
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Ross Thompson
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2752e5de4c
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Fixed a bunch of timing constraints for the arty a7 board.
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2023-07-19 17:08:16 -05:00 |
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Ross Thompson
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7aecd72c35
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Fpga does not correctly boot linux. I think the solution here is to revert out all substantive changes except for parameterization and then add them back in one at a time. This is necessary because the parameterization is not completed in one contiguous group of commits.
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2023-06-22 12:55:49 -05:00 |
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Ross Thompson
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a8f11dcad0
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FPGA updates.
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2023-06-20 11:11:34 -05:00 |
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Ross Thompson
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0423d7df82
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I think the fpga is building again, but the debugger script needs to be updated. For some reason the nets are not present despite being marked debug.
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2023-06-16 17:00:27 -05:00 |
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Jacob Pease
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40f81d5da6
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The Vivado-RISC-V SDC works. Wally is now booting through it.
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2023-05-26 15:42:33 -05:00 |
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Ross Thompson
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b13fe870cf
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Yeah We boot linux on the arty a7!
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2023-04-19 11:17:33 -05:00 |
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Ross Thompson
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1fec535b32
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Fixed the reset for Arty A7 and now partially boots. Copies flash card to dram.
but the data is wrong.
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2023-04-19 10:35:18 -05:00 |
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Ross Thompson
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367bd0f8dc
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More debug stuff.
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2023-04-18 16:00:10 -05:00 |
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Ross Thompson
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668e69fdc9
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Added more signals to debugger in hopes I can figure out why the mig is not responding.
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2023-04-18 15:51:52 -05:00 |
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Jacob Pease
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2839f4f41a
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AHB triggers write, but AXI side doesn't update.
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2023-04-18 15:23:22 -05:00 |
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Ross Thompson
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3588c53e66
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It's almost working.
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2023-04-18 14:24:59 -05:00 |
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Ross Thompson
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deb0bfc24d
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Improved constraints and set ddr3 voltage to correct 1.35V. This voltage is only for synthesis. However I'm concerned because the gui did not let me select 1.35V.
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2023-04-17 20:05:59 -05:00 |
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Ross Thompson
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777bec2e24
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Fixed timing constraint issue.
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2023-04-17 19:53:43 -05:00 |
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Ross Thompson
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b2b30936be
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Found the DDR3 memory is not ready when issuing the first store.
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2023-04-17 19:33:13 -05:00 |
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