Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity
5,265 Commits 5 Branches 2 Tags 53 MiB
3d67e48bef
Commit Graph

2173 Commits

Author SHA1 Message Date
Ross Thompson
3652673487 Fixed compressed branch class decode. 2023-01-26 11:07:47 -06:00
Ross Thompson
2ee6ffe74b Improved no class prediction mode. 2023-01-26 10:54:43 -06:00
Ross Thompson
29d4cd7ffa Modified the RAS to correctly repair itself. 2023-01-25 23:33:03 -06:00
Ross Thompson
43d4ac1c7b Intermediate commit. Passes regression tests, but RAS is not correct. 2023-01-25 19:39:18 -06:00
Ross Thompson
4e858199e5 Fixed typos. 2023-01-25 18:51:09 -06:00
Ross Thompson
e1d0be5c61 RAS is now compliant with our header and documentation guide. 2023-01-25 17:18:07 -06:00
Ross Thompson
0b9f787635 Improved RAS again. 2023-01-25 17:10:52 -06:00
Ross Thompson
172c40d44b Improved RAS. 2023-01-25 17:06:25 -06:00
Ross Thompson
56aa798d5c More branch predictor improvements. 2023-01-25 16:03:02 -06:00
Ross Thompson
3d285312f0 Cleaned up branch predictor. 2023-01-25 15:29:55 -06:00
Ross Thompson
bb89bf82bf Fixed subtle bug in btb. 2023-01-25 15:16:53 -06:00
Ross Thompson
d4004c2c22 Added logic to forward btb prediction results. 2023-01-25 13:02:20 -06:00
Ross Thompson
541524a754 More btb cleanup. 2023-01-25 12:14:18 -06:00
Ross Thompson
85e015d61e Found minor bug in gshare. 2023-01-25 12:08:54 -06:00
Ross Thompson
a0bca35b50 BTB cleanup. 2023-01-25 12:05:13 -06:00
Ross Thompson
5030a56f57 Optomized gshare. 2023-01-25 11:41:16 -06:00
Ross Thompson
a5bd78a622 Renamed file missed from last commit. 2023-01-25 10:17:43 -06:00
Ross Thompson
1e7fda6410 Fixed wrong header on optgshare.sv. Somehow it still had the old MIT license. 
Renamed ram2p1rwbefix.sv to ram2p1rwbe.sv
 2023-01-25 10:14:30 -06:00
Ross Thompson
42553d1d94 Removed old versions of gshare. 2023-01-24 17:26:54 -06:00
Ross Thompson
0d7653f1c7 Removed the old two port ram and replaced it with the fixed version. 
The fixed version is renamed to ram2p1r1wb.sv
 2023-01-24 17:25:16 -06:00
Ross Thompson
3d07f7a3a2 Moved and ranamed btb to btb.sv 
Fixed btb to use the fixed port 2 sram.
 2023-01-24 17:19:51 -06:00
Ross Thompson
7ae6b1868e Partial BTB cleanup. 2023-01-24 16:12:35 -06:00
Ross Thompson
879cb77b90 Moved branch predictor files into separate sub-directory. 2023-01-24 16:00:27 -06:00
David Harris
7d015151bb Merge remote-tracking branch 'upstream/main' into dev 2023-01-24 09:40:07 -08:00
David Harris
0e5ea5f51d bpred input spacing cleanup 2023-01-24 06:14:31 -08:00
David Harris
30b085911a bpred tab cleanup 2023-01-24 05:42:34 -08:00
Ross Thompson
89698a929e Moved ebufsmarb into its own module. 2023-01-23 23:10:10 -06:00
Ross Thompson
d495d7b04d Added comments about needing move ebufsm into a new module. 2023-01-23 22:03:49 -06:00
Ross Thompson
45094fc7bb Added comments to lrsc module. 2023-01-23 17:49:47 -06:00
Ross Thompson
e1c121fe0d Oups fixed bug from the last commit. 2023-01-23 17:38:30 -06:00
Ross Thompson
bb11de0f4c Another round of cleanup in the LSU. 2023-01-23 17:27:39 -06:00
David Harris
678a879415 formatting 2023-01-23 10:54:06 -08:00
David Harris
b6b67516eb Repo cleanup 2023-01-23 10:37:33 -08:00
Ross Thompson
07308e2c14 Removed mark_debug from all source code. 2023-01-20 18:47:36 -06:00
David Harris
c2f7f7324d test 2023-01-20 15:23:38 -08:00
David Harris
b173112f86 Continued framework for B instructions 2023-01-20 14:27:13 -08:00
David Harris
1933ea39fa Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2023-01-20 14:19:10 -08:00
David Harris
0f68fccf82 Started adding bit manipulation unit 2023-01-20 14:19:07 -08:00
Ross Thompson
3d71d0196c Updated figure cache references. 2023-01-20 15:01:54 -06:00
Ross Thompson
5b740fbf60 Removed SDC from repo due to copy right issue. 
Modified fpga build flow to reference it outside the repo.
 2023-01-20 14:57:06 -06:00
Ross Thompson
b1f3bd566c Formatting. 2023-01-20 13:13:05 -06:00
Ross Thompson
f78bfc4940 Formatting. 2023-01-20 13:09:42 -06:00
Ross Thompson
c7f4970597 Formatting. 2023-01-20 13:05:10 -06:00
Ross Thompson
6142c96946 Reformatting cachefsm. 2023-01-20 12:49:55 -06:00
Ross Thompson
7e96f3e8f7 Formatting. 2023-01-20 12:41:57 -06:00
Ross Thompson
95de716a17 Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2023-01-20 12:37:12 -06:00
Ross Thompson
b8a699270e More cleanup and formatting. 2023-01-20 12:34:40 -06:00
David Harris
032332ebae renamed comparator module 2023-01-20 10:13:47 -08:00
Ross Thompson
f1049be6c1 More cleanup and formatting. 2023-01-20 12:09:21 -06:00
Ross Thompson
4a2d02ab28 Formatting. 2023-01-20 11:51:10 -06:00
Ross Thompson
11c44006c4 Integrated the missing zifence tests into the regression test. 2023-01-20 10:34:49 -06:00
Ross Thompson
eb19b1b499 Imperas found a bug with the Fence.I instruction. 
If a fence.i directly followed a store miss, the d$ would release Stall during the cache line write.
Then transition to ReadHold.  This cause the d$ flush to go high while in ReadHold.  The solution is
to ensure the cache continues to assert Stall while in WriteLine state.

There was a second issue also.  The D$ flush asserted FlushD which flushed the I$ invalidate.
Finally the third issue was CacheEn from the FSM needs to be asserted on an InvalidateCache.
 2023-01-20 10:17:21 -06:00
Ross Thompson
6f3b8680d5 Imperas found a bug with the Fence.I instruction. 
If a fence.i directly followed a store miss, the d$ would release Stall during the cache line write.
Then transition to ReadHold.  This cause the d$ flush to go high while in ReadHold.  The solution is
to ensure the cache continues to assert Stall while in WriteLine state.

There was a second issue also.  The D$ flush asserted FlushD which flushed the I$ invalidate.
Finally the third issue was CacheEn from the FSM needs to be asserted on an InvalidateCache.
 2023-01-20 09:41:18 -06:00
Ross Thompson
63dbebcb5a Improved comment. 2023-01-19 17:41:57 -06:00
Ross Thompson
91bd55d9ba ram uses always rather than always_ff due to modelsim issue. 2023-01-19 17:41:15 -06:00
Ross Thompson
30935fd2b7 Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2023-01-19 17:28:53 -06:00
Ross Thompson
78e8598ec8 Added comment about needed changes in BTB. 2023-01-19 17:28:00 -06:00
David Harris
aed6f79d1e Removed study versions from comparator 2023-01-19 15:13:35 -08:00
David Harris
ad3b528b5d Moved unused study files to studies directory 2023-01-19 15:13:11 -08:00
David Harris
264362ce17 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2023-01-19 14:47:54 -08:00
David Harris
a1b25e1039 RAM declaration cleanup: 2023-01-19 14:47:51 -08:00
Ross Thompson
75391f4b56 Formatting. 2023-01-19 15:06:37 -06:00
Ross Thompson
40d62ec0d1 Formatting. 2023-01-19 14:18:46 -06:00
Ross Thompson
999477bb02 Formatting and name changes. 2023-01-19 14:16:29 -06:00
eroom1966
43d5769bd9 update 2023-01-19 13:29:46 +00:00
Ross Thompson
0bbf6e4ae2 Formatting. 2023-01-18 19:26:20 -06:00
Ross Thompson
21b2b10e78 Formatting spillsupport. 2023-01-18 19:25:54 -06:00
Ross Thompson
db48e547f0 Formatting. 2023-01-18 19:11:30 -06:00
Ross Thompson
9170827c98 Reduced complexity of spill logic by ensuring the irom outputs offset instrutions on a spill. 2023-01-18 19:10:34 -06:00
Ross Thompson
e79c403fe1 More IROM cleanup. 2023-01-18 18:47:02 -06:00
Ross Thompson
63577cbf4a Cleanup dtim and irom. 2023-01-18 18:44:30 -06:00
Ross Thompson
2d945963e6 Added comments to decompress.sv. May want to consider additional documentation. 2023-01-18 18:26:51 -06:00
Ross Thompson
f34c67722d Formatted subword* and bytemask. 2023-01-18 18:20:22 -06:00
Ross Thompson
f288b9ca14 Formatting. 2023-01-18 18:17:48 -06:00
Ross Thompson
cc186d0f3b Formatting. 2023-01-18 18:16:56 -06:00
Ross Thompson
a8549f26f2 Formatting. 2023-01-18 18:16:20 -06:00
Ross Thompson
cca6146dab Renamed signals in amoalu. 2023-01-18 18:13:18 -06:00
Ross Thompson
b223e22642 Formatting. 2023-01-18 18:05:11 -06:00
Ross Thompson
a5450c27ab Formatting. 2023-01-18 17:56:47 -06:00
Ross Thompson
87f2133d91 Formatting. 2023-01-18 17:49:19 -06:00
Ross Thompson
4e882e0769 Formating. 2023-01-18 17:30:08 -06:00
Ross Thompson
92f04f055c Formatting 2023-01-18 17:14:37 -06:00
Ross Thompson
520209363d Formatting 2023-01-18 17:03:45 -06:00
Ross Thompson
c5c4a3c011 Formatting 2023-01-18 16:58:03 -06:00
Ross Thompson
edc4630742 Formating. 2023-01-18 16:52:46 -06:00
Ross Thompson
32589a5efc Formating. 2023-01-18 16:47:40 -06:00
David Harris
d1ad6b464d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2023-01-18 13:07:03 -08:00
David Harris
a96d8dcec0 removed fma directory, improved plic comments 2023-01-18 13:06:54 -08:00
eroom1966
8dea3491a3 Partial fix for misaligned LD/ST 2023-01-18 17:11:39 +00:00
eroom1966
0ccab9accc changes made with Ross 2023-01-18 16:46:48 +00:00
sarah-harris
75038c279d Minor fixes in datapath.sv and ieu.sv (comments, putting signals in correct grouping) 2023-01-18 07:26:08 -08:00
eroom1966
247879e7c7 add im flags for compressed disass 2023-01-18 13:37:28 +00:00
eroom1966
52ebac59b8 remove volatile for FFLAGS and FCSR 2023-01-18 13:33:57 +00:00
eroom1966
68af12ece1 refer to correct path 2023-01-18 13:26:07 +00:00
Ross Thompson
c02195301b More comments added to abhfsm. 2023-01-17 22:58:06 -06:00
Ross Thompson
36acc91b67 formating ahbinterface. 2023-01-17 22:54:42 -06:00
Ross Thompson
93fb8db9bb Moved amoalu to lsu. 2023-01-17 22:45:46 -06:00
Ross Thompson
cd5e62119a Added commenets and formating to abhcachefsm and abhcacheinterface. 2023-01-17 22:22:23 -06:00
Ross Thompson
c3096eea2a Cleaned up ahbcacheinterface. 2023-01-17 22:13:56 -06:00
Ross Thompson
4720b28272 Formatting progress. 2023-01-17 22:10:31 -06:00
Ross Thompson
d21eef40d7 Added comments to dtim and ahbcacheinterface. 2023-01-17 21:56:55 -06:00
Ross Thompson
42d0e1f8d2 Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2023-01-17 21:54:55 -06:00
Ross Thompson
374f95ebf3 Fixed the rvvi CSR write enable not synchronized with a valid instruction in the Writeback stage. 2023-01-17 18:24:46 -06:00
Ross Thompson
8f5b5e0989 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2023-01-17 15:44:44 -06:00
David Harris
fd52915f3c Clean up warnings from Questa 2023-01-17 13:43:39 -08:00
Ross Thompson
b2676e1dd4 Somehow the imperas files spilled into the main branch. 2023-01-17 15:39:34 -06:00
Ross Thompson
01f3432f6e Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2023-01-17 14:50:45 -06:00
David Harris
4a01ebd4d9 IEU comment cleanup 2023-01-17 10:51:44 -08:00
David Harris
e0dbbb60c9 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2023-01-17 06:47:06 -08:00
David Harris
cd281996a0 IEU signal comment cleanup 2023-01-17 06:47:02 -08:00
sarah-harris
9fb7c8132a Changing signal name to ImmExtD/E to match figures 
Changing signal name:
ExtImmD/E -> ImmExtD/E

to match figures.
 2023-01-17 06:33:58 -08:00
David Harris
2c00ac5254 pipelined/src/ieu/ieu.sv 2023-01-17 06:08:26 -08:00
sarah-harris
3124ebc3e1 IEU cleanup 
IEU cleanup
 2023-01-17 06:02:26 -08:00
eroom1966
cf3223df22 refactor all rvvi into single initial block 2023-01-17 13:01:01 +00:00
eroom1966
2ead2cdaf4 Code refactor and addition of rvvi interface 2023-01-17 12:47:38 +00:00
Ross Thompson
79c9e4df12 Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2023-01-16 14:03:05 -06:00
Ross Thompson
1680f89ef3 Found a potential issue with mstatush when XLEN = 64. 2023-01-16 13:57:28 -06:00
Ross Thompson
7984194c2a Fixed issue with rvvi tracer so it reports call csr changes, not just instrutions which write the CSRs. 2023-01-16 13:35:06 -06:00
David Harris
3e17bfbc53 Removed Imperas tests from regression 2023-01-16 07:01:07 -08:00
David Harris
fdb839edcb Makefile and setup cleanup 2023-01-15 20:27:12 -08:00
David Harris
dc74bcff5b Clean up tabs 2023-01-15 18:23:09 -08:00
Ross Thompson
4e1e10a729 Fixed bug with gshare repair from branch class miss prediction. 2023-01-15 14:39:48 -06:00
David Harris
364cf97c34 cache cleanup 2023-01-14 19:43:29 -08:00
David Harris
94d01d292e ebu cleanup 2023-01-14 19:29:45 -08:00
David Harris
17fd2d2a3b ebu cleanup 2023-01-14 19:19:34 -08:00
David Harris
b4dd7b21e6 generic cleanup 2023-01-14 19:02:38 -08:00
David Harris
fa61c9c4a5 generic cleanup 2023-01-14 18:56:46 -08:00
David Harris
21acb5e4e8 mmu cleanup 2023-01-14 18:27:53 -08:00
David Harris
894fdb8863 mmu cleanup 2023-01-14 18:20:47 -08:00
David Harris
316690c929 mmu cleanup 2023-01-14 18:14:38 -08:00
David Harris
00500c6685 mmu cleanup 2023-01-14 17:49:10 -08:00
David Harris
bba08c3202 mmu cleanup 2023-01-14 17:35:21 -08:00
David Harris
be029deb07 uncore cleanup 2023-01-14 17:21:07 -08:00
David Harris
16ff590a8c uncore cleanup 2023-01-14 17:09:11 -08:00
David Harris
b302f66baf uncore cleanup 2023-01-14 17:07:36 -08:00
David Harris
ae7e7b57ec uncore cleanup 2023-01-14 17:00:58 -08:00
David Harris
9ac905b5c0 sdc cleanup 2023-01-14 16:49:44 -08:00
David Harris
41c7d5c510 uncore cleanup 2023-01-14 06:15:35 -08:00
David Harris
da9f29b874 Wallypipeliendcore/soc cleanup 2023-01-14 05:57:50 -08:00
David Harris
50fae76207 csr & wally cleanup 2023-01-13 22:25:19 -08:00
David Harris
53d0d28828 csr cleanup 2023-01-13 22:12:06 -08:00
David Harris
b7f579a146 csr cleanup 2023-01-13 21:29:03 -08:00
David Harris
c5358da771 csr cleanup 2023-01-13 21:25:55 -08:00
David Harris
97bddf0d54 csr cleanup 2023-01-13 21:09:29 -08:00
David Harris
e4f4b31896 csr cleanup 2023-01-13 21:00:06 -08:00
David Harris
7358402bc0 csr cleanup 2023-01-13 20:55:21 -08:00
David Harris
9da2fae1f3 csr comments 2023-01-13 20:49:34 -08:00
David Harris
a9008cb293 trap comments 2023-01-13 19:50:44 -08:00
David Harris
370678f730 trap comments 2023-01-13 19:44:38 -08:00
David Harris
27f81b09ce privileged comments 2023-01-13 17:57:38 -08:00