mirror of
https://github.com/openhwgroup/cvw
synced 2025-01-24 05:24:49 +00:00
Improved RAS again.
This commit is contained in:
Ross Thompson
parent
172c40d44b
commit
0b9f787635
@ -41,12 +41,12 @@ add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/PostSpi
|
||||
add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrD
|
||||
add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrE
|
||||
add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrM
|
||||
add wave -noupdate -expand -group PCS /testbench/dut/core/ifu/PCNextF
|
||||
add wave -noupdate -expand -group PCS /testbench/dut/core/PCF
|
||||
add wave -noupdate -expand -group PCS /testbench/dut/core/ifu/PCD
|
||||
add wave -noupdate -expand -group PCS /testbench/dut/core/PCE
|
||||
add wave -noupdate -expand -group PCS /testbench/dut/core/PCM
|
||||
add wave -noupdate -expand -group PCS /testbench/PCW
|
||||
add wave -noupdate -group PCS /testbench/dut/core/ifu/PCNextF
|
||||
add wave -noupdate -group PCS /testbench/dut/core/PCF
|
||||
add wave -noupdate -group PCS /testbench/dut/core/ifu/PCD
|
||||
add wave -noupdate -group PCS /testbench/dut/core/PCE
|
||||
add wave -noupdate -group PCS /testbench/dut/core/PCM
|
||||
add wave -noupdate -group PCS /testbench/PCW
|
||||
add wave -noupdate -group {Decode Stage} /testbench/dut/core/ifu/PCD
|
||||
add wave -noupdate -group {Decode Stage} /testbench/dut/core/ifu/InstrD
|
||||
add wave -noupdate -group {Decode Stage} /testbench/InstrDName
|
||||
@ -55,15 +55,15 @@ add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/c/RegWriteD
|
||||
add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/RdD
|
||||
add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs1D
|
||||
add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs2D
|
||||
add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ifu/PCE
|
||||
add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ifu/InstrE
|
||||
add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName
|
||||
add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ieu/c/InstrValidE
|
||||
add wave -noupdate -expand -group {Execution Stage} /testbench/FunctionName/FunctionName/FunctionName
|
||||
add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/PCM
|
||||
add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/InstrM
|
||||
add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName
|
||||
add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/lsu/IEUAdrM
|
||||
add wave -noupdate -group {Execution Stage} /testbench/dut/core/ifu/PCE
|
||||
add wave -noupdate -group {Execution Stage} /testbench/dut/core/ifu/InstrE
|
||||
add wave -noupdate -group {Execution Stage} /testbench/InstrEName
|
||||
add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/c/InstrValidE
|
||||
add wave -noupdate -group {Execution Stage} /testbench/FunctionName/FunctionName/FunctionName
|
||||
add wave -noupdate -group {Memory Stage} /testbench/dut/core/PCM
|
||||
add wave -noupdate -group {Memory Stage} /testbench/dut/core/InstrM
|
||||
add wave -noupdate -group {Memory Stage} /testbench/InstrMName
|
||||
add wave -noupdate -group {Memory Stage} /testbench/dut/core/lsu/IEUAdrM
|
||||
add wave -noupdate -group {WriteBack stage} /testbench/PCW
|
||||
add wave -noupdate -group {WriteBack stage} /testbench/InstrW
|
||||
add wave -noupdate -group {WriteBack stage} /testbench/InstrWName
|
||||
@ -85,25 +85,18 @@ add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SEPC_REGW
|
||||
add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SSTATUS_REGW
|
||||
add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/STVEC_REGW
|
||||
add wave -noupdate -group Bpred -group {branch update selection inputs} -divider {class check}
|
||||
add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/BTBValidF
|
||||
add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/BPInstrClassF
|
||||
add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/BTBPredPCF
|
||||
add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/RASPCF
|
||||
add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/LookUpPCIndex
|
||||
add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/TargetPC
|
||||
add wave -noupdate -group Bpred -expand -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/PCSrcE
|
||||
add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdatePCIndex
|
||||
add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdateTarget
|
||||
add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdateEN
|
||||
add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdatePC
|
||||
add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdateTarget
|
||||
add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/TargetWrongE
|
||||
add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/FallThroughWrongE
|
||||
add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/PredictionPCWrongE
|
||||
add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/InstrClassE
|
||||
add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/PredictionInstrClassWrongE
|
||||
add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/BPPredClassNonCFIWrongE
|
||||
add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE
|
||||
add wave -noupdate -group Bpred -group prediction /testbench/dut/core/ifu/bpred/bpred/BTBValidF
|
||||
add wave -noupdate -group Bpred -group prediction /testbench/dut/core/ifu/bpred/bpred/BTBPredPCF
|
||||
add wave -noupdate -group Bpred -group prediction /testbench/dut/core/ifu/bpred/bpred/RASPCF
|
||||
add wave -noupdate -group Bpred -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/PCSrcE
|
||||
add wave -noupdate -group Bpred -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdateEN
|
||||
add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/TargetWrongE
|
||||
add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/FallThroughWrongE
|
||||
add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/PredictionPCWrongE
|
||||
add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/InstrClassE
|
||||
add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/PredictionInstrClassWrongE
|
||||
add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/BPPredClassNonCFIWrongE
|
||||
add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE
|
||||
add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE
|
||||
add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNextF
|
||||
add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCF
|
||||
@ -148,20 +141,15 @@ add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RdW
|
||||
add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/ALUResultE
|
||||
add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcAE
|
||||
add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcBE
|
||||
add wave -noupdate -group AHB -expand -group multicontroller -color Gold /testbench/dut/core/ebu/ebu/CurrState
|
||||
add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/IFUReq
|
||||
add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/LSUReq
|
||||
add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/both
|
||||
add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/IFUSave
|
||||
add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/IFURestore
|
||||
add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/IFUDisable
|
||||
add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/LSUDisable
|
||||
add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/IFUSelect
|
||||
add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/LSUSelect
|
||||
add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/BeatCount
|
||||
add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/FinalBeat
|
||||
add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HTRANS
|
||||
add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/Threshold
|
||||
add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HBURST
|
||||
add wave -noupdate -group AHB -expand -group IFU /testbench/dut/core/ebu/ebu/IFUHTRANS
|
||||
add wave -noupdate -group AHB -expand -group IFU /testbench/dut/core/ebu/ebu/IFUHADDR
|
||||
@ -463,10 +451,6 @@ add wave -noupdate -group {debug trace} -expand -group mem /testbench/dut/core/P
|
||||
add wave -noupdate -group {debug trace} -expand -group mem -color Brown /testbench/dut/core/hzu/TrapM
|
||||
add wave -noupdate -group {debug trace} -expand -group wb /testbench/PCW
|
||||
add wave -noupdate -group {pc selection} /testbench/dut/core/ifu/PCNext2F
|
||||
add wave -noupdate -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/SpillF
|
||||
add wave -noupdate -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/CurrState
|
||||
add wave -noupdate -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/SpillDataLine0
|
||||
add wave -noupdate -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/SelSpillF
|
||||
add wave -noupdate -group ifu /testbench/dut/core/ifu/InstrRawF
|
||||
add wave -noupdate -group ifu /testbench/dut/core/ifu/PostSpillInstrRawF
|
||||
add wave -noupdate -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HSIZE
|
||||
@ -484,7 +468,6 @@ add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/PCPF
|
||||
add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/cachefsm/AnyMiss
|
||||
add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/bus/icache/icache/HitWay
|
||||
add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/ICacheStallF
|
||||
add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/FinalInstrRawF
|
||||
add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/CacheBusAdr
|
||||
add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CacheBusAck
|
||||
add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/VictimWay
|
||||
@ -571,7 +554,6 @@ add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/FRD3E
|
||||
add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/ForwardedSrcAE
|
||||
add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/ForwardedSrcBE
|
||||
add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/Funct3E
|
||||
add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/MDUE
|
||||
add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/W64E
|
||||
add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/unpack/X
|
||||
add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/unpack/Y
|
||||
@ -603,8 +585,15 @@ add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/Br
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrM
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/NewDirPredictionF
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/NewDirPredictionW
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/memory/ra1
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/memory/rd1
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/PCE
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/IEUAdrE
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdateEN
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PredictionInstrClassWrongE
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/WrongPredInstrClassD
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {219681 ns} 1} {{Cursor 4} {341201 ns} 1} {{Cursor 5} {116741 ns} 0}
|
||||
WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {219681 ns} 1} {{Cursor 4} {341201 ns} 1} {{Cursor 5} {125611 ns} 0}
|
||||
quietly wave cursor active 5
|
||||
configure wave -namecolwidth 250
|
||||
configure wave -valuecolwidth 194
|
||||
@ -620,4 +609,4 @@ configure wave -griddelta 40
|
||||
configure wave -timeline 0
|
||||
configure wave -timelineunits ns
|
||||
update
|
||||
WaveRestoreZoom {118528 ns} {128752 ns}
|
||||
WaveRestoreZoom {79760 ns} {171462 ns}
|
||||
|
||||
@ -32,15 +32,13 @@ module RASPredictor
|
||||
#(parameter int StackSize = 16
|
||||
)
|
||||
(input logic clk,
|
||||
input logic reset, StallF, StallD, StallE,
|
||||
input logic reset, StallF, StallD, StallE, StallM, FlushD, FlushE, FlushM,
|
||||
output logic [`XLEN-1:0] RASPCF,
|
||||
input logic [3:0] WrongPredInstrClassD,
|
||||
input logic [3:0] InstrClassD, InstrClassE, PredInstrClassF,
|
||||
input logic [`XLEN-1:0] PCLinkE
|
||||
);
|
||||
|
||||
// *** need to update so it either doesn't push until the memory stage
|
||||
// or need to repair flushed push.
|
||||
// *** need to repair popped and then flushed returns.
|
||||
logic CounterEn;
|
||||
localparam Depth = $clog2(StackSize);
|
||||
@ -50,19 +48,20 @@ module RASPredictor
|
||||
integer index;
|
||||
logic PopF;
|
||||
logic PushE;
|
||||
logic RepairD;
|
||||
|
||||
|
||||
|
||||
assign PopF = PredInstrClassF[2] & ~StallF;
|
||||
assign PushE = InstrClassE[3] & ~StallE;
|
||||
assign PopF = PredInstrClassF[2] & ~StallD & ~FlushD;
|
||||
assign RepairD = InstrClassD[2] & ~StallE & ~FlushE;
|
||||
assign PushE = InstrClassE[3] & ~StallM & ~FlushM;
|
||||
|
||||
assign CounterEn = PopF | PushE | WrongPredInstrClassD[2];
|
||||
|
||||
assign PtrD = PopF | InstrClassD[2] ? PtrM1 : PtrP1;
|
||||
assign PtrD = PopF | RepairD ? PtrM1 : PtrP1;
|
||||
|
||||
assign PtrM1 = PtrQ - 1'b1;
|
||||
assign PtrP1 = PtrQ + 1'b1;
|
||||
// may have to handle a PushE and an incr at the same time.
|
||||
// *** what happens if jal is executing and there is a return being flushed in Decode?
|
||||
|
||||
flopenr #(Depth) PTR(.clk(clk),
|
||||
@ -75,7 +74,7 @@ module RASPredictor
|
||||
always_ff @ (posedge clk) begin
|
||||
if(reset) begin
|
||||
for(index=0; index<StackSize; index++)
|
||||
memory[index] <= {`XLEN{1'b0}};
|
||||
memory[index] <= {`XLEN{1'b0}};
|
||||
end else if(PushE) begin
|
||||
memory[PtrP1] <= #1 PCLinkE;
|
||||
end
|
||||
|
||||
@ -147,7 +147,7 @@ module bpred (
|
||||
// Part 3 RAS
|
||||
// *** need to add the logic to restore RAS on flushes. We will use incr for this.
|
||||
// *** needs to include flushX
|
||||
RASPredictor RASPredictor(.clk, .reset, .StallF, .StallD, .StallE,
|
||||
RASPredictor RASPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM,
|
||||
.PredInstrClassF, .InstrClassD, .InstrClassE,
|
||||
.WrongPredInstrClassD, .RASPCF, .PCLinkE);
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user