David Harris
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2b50b30f23
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Updated extractSummary to read synthesis outputs in new form
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2024-04-27 07:18:26 -07:00 |
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David Harris
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06e34b7be4
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Fixed byte enables for synthesis
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2024-04-27 06:25:24 -07:00 |
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David Harris
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6cb554960c
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Updated README about installation
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2024-04-26 16:34:31 -07:00 |
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Rose Thompson
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585f3b5950
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Merge pull request #757 from davidharrishmc/dev
Functional coverage locations and synthesis fixes
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2024-04-26 18:16:59 -05:00 |
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David Harris
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1274ec55af
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Resolved merge conflict
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2024-04-26 16:15:23 -07:00 |
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David Harris
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bed31fd112
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Merge pull request #756 from quswarabid/fix_regression_flow_riscvdv
FIXED: Regression flow based on tests generated by RISCV-DV and coverage captured by RISCVISACOV is fixed
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2024-04-26 16:13:33 -07:00 |
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David Harris
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c7c2e94e26
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Fixes for synthesis with derived configurations
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2024-04-26 15:58:36 -07:00 |
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Quswar Abid
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f999ccadf4
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/cad/mentor/questa_sim-2023.4/questasim is fixed, relative paths to design and testbench files are fixed, and RISCV-DV submodule is updated back to the latest commit on master branch
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2024-04-26 15:55:39 -07:00 |
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David Harris
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4faf44c4c6
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Named zknde block in bitmanipalu
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2024-04-25 17:24:00 -07:00 |
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David Harris
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a249f6f2d7
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Merge pull request #755 from ross144/main
Bug fix: correct record the number of cache misses in the performance counters.
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2024-04-24 17:15:13 -07:00 |
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Rose Thompson
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6c0b860742
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Fixed the cache miss counter.
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2024-04-24 16:14:51 -05:00 |
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David Harris
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5d97858806
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Moved functional coverage files to sim/questa and to tests/riscvdv
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2024-04-24 11:46:38 -07:00 |
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Rose Thompson
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85eda21dfe
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Merge pull request #754 from davidharrishmc/dev
Integrating riscv-dv
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2024-04-24 12:35:39 -05:00 |
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David Harris
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160c11d786
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Integrating riscv-dv coverage
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2024-04-24 10:17:49 -07:00 |
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David Harris
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eb7e5d4bc2
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2024-04-24 09:47:56 -07:00 |
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David Harris
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5f3676dfd7
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Merge pull request #753 from quswarabid/riscvdv_bringup
RISCVDV bringup - Coverage Collection on RISCVISACOV
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2024-04-24 09:47:34 -07:00 |
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David Harris
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d11de0f28a
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Added nobpred case to nightly regression
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2024-04-24 08:46:06 -07:00 |
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David Harris
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e52409e916
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Hard-coded NUM_THREADS in tool-chain-install to make it easier to paste code
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2024-04-24 08:45:07 -07:00 |
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David Harris
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235a3dcfca
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ROM preload compatible with Verilator lint, sim, and Design Compiler
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2024-04-24 08:44:37 -07:00 |
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David Harris
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3950588b8c
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Brought subrepos up to date
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2024-04-24 07:36:42 -07:00 |
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Rose Thompson
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195d9539bb
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Merge pull request #747 from davidharrishmc/dev
Zcb tests & other cleanup
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2024-04-24 08:45:31 -05:00 |
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David Harris
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32b6e6a8ab
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fround progress
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2024-04-24 04:42:47 -07:00 |
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David Harris
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e2894ed278
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derived nobpred_rv32gc config for coremark test
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2024-04-24 04:41:25 -07:00 |
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Quswar Abid
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f45efea9c9
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Bringup of RISCV-DV to collect functional coverage - ADDED the Make flow to run a regression of tests (RV64GC) from RISCV-DV on seed 0 and collect functional coverage
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2024-04-23 18:23:34 -07:00 |
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Quswar Abid
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c0a0c1e9e5
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Bringup of RISCV-DV to collect functional coverage - sample the .bashrc file to export environmental variables that RISCV-DV uses
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2024-04-23 18:21:54 -07:00 |
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Quswar Abid
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7b441d2881
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Bringup of RISCV-DV to collect functional coverage - Update to track RV64IMAFDC_Zicsr related coverpoints from riscvISACOV
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2024-04-23 18:20:29 -07:00 |
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David Harris
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a722c7cd08
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Ignoring vcd output
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2024-04-23 10:19:53 -07:00 |
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David Harris
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0dc2c7d16a
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Fixed deriv path in Verilator makefile
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2024-04-23 10:19:08 -07:00 |
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David Harris
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2dd54b3612
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adding ssmtp for nightly regression emails
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2024-04-23 10:18:28 -07:00 |
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David Harris
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2f5680b7a6
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Silencing new version of Verilator in lint
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2024-04-23 10:18:00 -07:00 |
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David Harris
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6415bfc3c2
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Code and testbench cleanup
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2024-04-23 10:17:44 -07:00 |
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David Harris
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f9eec8c43f
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Merged wsim changes
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2024-04-22 13:11:35 -07:00 |
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David Harris
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7586ecd317
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Merge pull request #751 from Karl-Han/vcd
Add support for dumping vcd.
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2024-04-22 13:09:58 -07:00 |
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Kunlin Han
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9be0303493
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Add support for dumping vcd.
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2024-04-22 13:03:51 -07:00 |
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David Harris
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bd1afa53f8
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simulation cleanup
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2024-04-22 12:28:16 -07:00 |
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David Harris
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cc236bdb25
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Resolved merge conflicts
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2024-04-22 12:16:06 -07:00 |
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David Harris
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750fb6bfce
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Merge pull request #750 from Karl-Han/verilator
Run verilator configurations and testsuites in different folders.
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2024-04-22 11:36:32 -07:00 |
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Kunlin Han
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c134b712c4
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Merge branch 'main' into verilator
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2024-04-22 11:35:18 -07:00 |
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Kunlin Han
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c383bef1ad
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Run verilator configurations and testsuites in different folders.
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2024-04-22 11:32:46 -07:00 |
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David Harris
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76367822bf
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Merge pull request #749 from Karl-Han/docker
Replace spaces of Makefile and Add some helper targets
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2024-04-22 11:09:12 -07:00 |
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Kunlin Han
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d4fa95910a
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Add some helper targets.
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2024-04-22 10:49:02 -07:00 |
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David Harris
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7944459fc9
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Merge pull request #748 from ross144/main
FPGA fixex required after regress updates and added compatiblity for cygwin.
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2024-04-22 08:53:50 -07:00 |
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Rose Thompson
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8123695831
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Maded insert_debug_comment.sh compatible with cygwin.
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2024-04-22 10:48:34 -05:00 |
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Rose Thompson
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3bed733301
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Fixed fpga to work with the updated regression changes.
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2024-04-22 10:42:01 -05:00 |
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David Harris
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26711083df
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Flushing uart.out file to observe progress
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2024-04-21 20:08:35 -07:00 |
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David Harris
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45196a9959
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ignore VCS junk files
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2024-04-21 19:49:55 -07:00 |
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David Harris
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03f49dea3f
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regression printing improvements
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2024-04-21 19:45:09 -07:00 |
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David Harris
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3f195884e9
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Defined bit sizes more precisely to help VCS lint and conform to coding style
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2024-04-21 08:40:11 -07:00 |
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David Harris
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1759c920bb
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improved regression comments
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2024-04-21 08:38:59 -07:00 |
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David Harris
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be15a11622
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Fixed conflicts on getenv
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2024-04-21 08:38:13 -07:00 |
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