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Merge pull request #755 from ross144/main

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Bug fix: correct record the number of cache misses in the performance counters.
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David Harris 2024-04-24 17:15:13 -07:00 committed by GitHub
commit a249f6f2d7
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2
src/cache/cachefsm.sv vendored
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@ -102,7 +102,7 @@ module cachefsm import cvw::*; #(parameter cvw_t P,
// outputs for the performance counters.
assign CacheAccess = (|CacheRW) & ((CurrState == STATE_ACCESS & ~Stall & ~FlushStage) | (CurrState == STATE_ADDRESS_SETUP & ~Stall & ~FlushStage)); // exclusion-tag: icache CacheW
assign CacheMiss = CacheAccess & ~Hit;
assign CacheMiss = CurrState == STATE_ADDRESS_SETUP & ~Stall & ~FlushStage;
// special case on reset. When the fsm first exists reset twayhe
// PCNextF will no longer be pointing to the correct address.