mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Merge pull request #757 from davidharrishmc/dev
Functional coverage locations and synthesis fixes
This commit is contained in:
Rose Thompson
GitHub
commit
585f3b5950
14
.gitignore
vendored
14
.gitignore
vendored
@ -117,10 +117,10 @@ tests/wally-riscv-arch-test/riscv-test-suite/rv*i_m/I/src/*.S
|
||||
tests/wally-riscv-arch-test/riscv-test-suite/rv*i_m/I/Makefrag
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sim/branch_BP_GSHARE10.log
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sim/branch_BP_GSHARE16.log
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sim/imperas.log
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sim/questa/imperas.log
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sim/results-error/
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sim/test1.rep
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sim/vsim.log
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sim/questa/vsim.log
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tests/coverage/*.elf
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*.elf.memfile
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sim/*Cache.log
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@ -211,3 +211,13 @@ sim/vcs/simprofile_dir
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sim/vcs/ucli.key
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sim/vcs/verdi_config_file
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sim/*/testbench.vcd
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sim/questa/imperas.log
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sim/questa/regression.log
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sim/questa/regression_logs/*
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sim/questa/regression_ucdbs/*
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sim/questa/riscv.ucdb
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sim/questa/riscv.ucdb.log
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sim/questa/riscv.ucdb.summary.log
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sim/questa/riscv.ucdb.testdetails.log
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tests/riscvdv
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104
Makefile
104
Makefile
@ -2,6 +2,8 @@
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# Top-level Makefile for CORE-V-Wally
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# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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SIM = ${WALLY}/sim
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all:
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make install
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make riscof
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@ -31,8 +33,8 @@ testfloat:
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cd ${WALLY}/tests/fp; ./create_all_vectors.sh
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verify:
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cd ${WALLY}/sim; ./regression-wally
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cd ${WALLY}/sim; ./sim-testfloat-batch all
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cd ${SIM}; ./regression-wally
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cd ${SIM}/sim; ./sim-testfloat-batch all
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make imperasdv
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imperasdv:
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@ -40,13 +42,13 @@ imperasdv:
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iter-elf.bash --search ${WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m
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imperasdv_cov:
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touch ${WALLY}/sim/seed0.txt
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echo "0" > ${WALLY}/sim/seed0.txt
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touch ${SIM}/seed0.txt
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echo "0" > ${SIM}/seed0.txt
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# /opt/riscv/ImperasDV-OpenHW/scripts/cvw/run-elf-cov.bash --verbose --seed 0 --search ${WALLY}/tests/riscof/work/wally-riscv-arch-test/rv64i_m
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# /opt/riscv/ImperasDV-OpenHW/scripts/cvw/run-elf-cov.bash --elf ${WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/I/src/add-01.S/dut/my.elf --seed ${WALLY}/sim/seed0.txt --coverdb ${WALLY}/sim/cov/rv64gc_arch64i.ucdb --verbose
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# /opt/riscv/ImperasDV-OpenHW/scripts/cvw/run-elf-cov.bash --elf ${WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/I/src/add-01.S/dut/my.elf --seed ${WALLY}/sim/seed0.txt --coverdb riscv.ucdb --verbose
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run-elf-cov.bash --elf ${WALLY}/tests/output_folder/asm_test/riscv_arithmetic_basic_test_0.elf --seed ${WALLY}/sim/seed0.txt --coverdb riscv.ucdb --verbose
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vcover report -details -html sim/riscv.ucdb
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# /opt/riscv/ImperasDV-OpenHW/scripts/cvw/run-elf-cov.bash --elf ${WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/I/src/add-01.S/dut/my.elf --seed ${SIM}/seed0.txt --coverdb ${SIM}/cov/rv64gc_arch64i.ucdb --verbose
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# /opt/riscv/ImperasDV-OpenHW/scripts/cvw/run-elf-cov.bash --elf ${WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/I/src/add-01.S/dut/my.elf --seed ${SIM}/seed0.txt --coverdb ${SIM}/questa/riscv.ucdb --verbose
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run-elf-cov.bash --elf ${WALLY}/tests/riscvdv/asm_test/riscv_arithmetic_basic_test_0.elf --seed ${SIM}/questa/seed0.txt --coverdb ${SIM}/questa/riscv.ucdb --verbose
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vcover report -details -html ${SIM}/questa/riscv.ucdb
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funcovreg:
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#iter-elf.bash --search ${WALLY}/tests/riscof/work/wally-riscv-arch-test/rv64i_m --cover
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@ -55,58 +57,58 @@ funcovreg:
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#iter-elf.bash --search ${WALLY}/tests/riscof/work/wally-riscv-arch-test/rv64i_m/Q --cover
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rm -f ${WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/*/src/*/dut/my.elf
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iter-elf.bash --search ${WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/I --cover
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vcover report -details -html sim/riscv.ucdb
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vcover report -details -html ${SIM}/questa/riscv.ucdb
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# test_name=riscv_arithmetic_basic_test
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rvdv:
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python3 ${WALLY}/addins/riscv-dv/run.py --test ${test_name} --target rv64gc --output tests/output_folder --iterations 1 -si questa --iss spike --verbose --cov --seed 0 --steps gen >> sim/regression_logs/${test_name}.log 2>&1
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python3 ${WALLY}/addins/riscv-dv/run.py --test ${test_name} --target rv64gc --output tests/output_folder --iterations 1 -si questa --iss spike --verbose --cov --seed 0 --steps gcc_compile >> sim/regression_logs/${test_name}.log 2>&1
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python3 ${WALLY}/addins/riscv-dv/run.py --test ${test_name} --target rv64gc --output tests/output_folder --iterations 1 -si questa --iss spike --verbose --cov --seed 0 --steps iss_sim >> sim/regression_logs/${test_name}.log 2>&1
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# run-elf.bash --seed ${WALLY}/sim/seed0.txt --verbose --elf ${WALLY}/tests/output_folder/asm_test/${test_name}_0.o >> sim/regression_logs/${test_name}.log 2>&1
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run-elf-cov.bash --seed ${WALLY}/sim/seed0.txt --verbose --coverdb sim/riscv.ucdb --elf ${WALLY}/tests/output_folder/asm_test/${test_name}_0.o >> sim/regression_logs/${test_name}.log 2>&1
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cp sim/riscv.ucdb sim/regression_ucdbs/${test_name}.ucdb
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python3 ${WALLY}/addins/riscv-dv/run.py --test ${test_name} --target rv64gc --output tests/riscvdv --iterations 1 -si questa --iss spike --verbose --cov --seed 0 --steps gen >> ${SIM}/questa/regression_logs/${test_name}.log 2>&1
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python3 ${WALLY}/addins/riscv-dv/run.py --test ${test_name} --target rv64gc --output tests/riscvdv --iterations 1 -si questa --iss spike --verbose --cov --seed 0 --steps gcc_compile >> ${SIM}/questa/regression_logs/${test_name}.log 2>&1
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python3 ${WALLY}/addins/riscv-dv/run.py --test ${test_name} --target rv64gc --output tests/riscvdv --iterations 1 -si questa --iss spike --verbose --cov --seed 0 --steps iss_sim >> ${SIM}/questa/regression_logs/${test_name}.log 2>&1
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# run-elf.bash --seed ${SIM}/questa/seed0.txt --verbose --elf ${WALLY}/tests/riscvdv/asm_test/${test_name}_0.o >> ${SIM}/questa/regression_logs/${test_name}.log 2>&1
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run-elf-cov.bash --seed ${SIM}/questa/seed0.txt --verbose --coverdb ${SIM}/questa/riscv.ucdb --elf ${WALLY}/tests/riscvdv/asm_test/${test_name}_0.o >> ${SIM}/questa/regression_logs/${test_name}.log 2>&1
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cp ${SIM}/questa/riscv.ucdb ${SIM}/questa/regression_ucdbs/${test_name}.ucdb
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rvdv_regression:
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mkdir -p sim/regression_logs
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mkdir -p sim/regression_ucdbs
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cd sim/regression_logs && rm -rf *
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cd sim/regression_ucdbs && rm -rf *
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make rvdv test_name=riscv_arithmetic_basic_test >> sim/regression.log 2>&1
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make rvdv test_name=riscv_amo_test >> sim/regression.log 2>&1
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make rvdv test_name=riscv_ebreak_debug_mode_test >> sim/regression.log 2>&1
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make rvdv test_name=riscv_ebreak_test >> sim/regression.log 2>&1
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make rvdv test_name=riscv_floating_point_arithmetic_test >> sim/regression.log 2>&1
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make rvdv test_name=riscv_floating_point_mmu_stress_test >> sim/regression.log 2>&1
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make rvdv test_name=riscv_floating_point_rand_test >> sim/regression.log 2>&1
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make rvdv test_name=riscv_full_interrupt_test >> sim/regression.log 2>&1
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make rvdv test_name=riscv_hint_instr_test >> sim/regression.log 2>&1
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make rvdv test_name=riscv_illegal_instr_test >> sim/regression.log 2>&1
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make rvdv test_name=riscv_invalid_csr_test >> sim/regression.log 2>&1
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make rvdv test_name=riscv_jump_stress_test >> sim/regression.log 2>&1
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make rvdv test_name=riscv_loop_test >> sim/regression.log 2>&1
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make rvdv test_name=riscv_machine_mode_rand_test >> sim/regression.log 2>&1
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make rvdv test_name=riscv_mmu_stress_test >> sim/regression.log 2>&1
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make rvdv test_name=riscv_no_fence_test >> sim/regression.log 2>&1
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make rvdv test_name=riscv_non_compressed_instr_test >> sim/regression.log 2>&1
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make rvdv test_name=riscv_pmp_test >> sim/regression.log 2>&1
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make rvdv test_name=riscv_privileged_mode_rand_test >> sim/regression.log 2>&1
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make rvdv test_name=riscv_rand_instr_test >> sim/regression.log 2>&1
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make rvdv test_name=riscv_rand_jump_test >> sim/regression.log 2>&1
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make rvdv test_name=riscv_sfence_exception_test >> sim/regression.log 2>&1
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make rvdv test_name=riscv_unaligned_load_store_test >> sim/regression.log 2>&1
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mkdir -p ${SIM}/questa/regression_logs
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mkdir -p ${SIM}/questa/regression_ucdbs
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cd ${SIM}/questa/regression_logs && rm -rf *
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cd ${SIM}/questa/regression_ucdbs && rm -rf *
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make rvdv test_name=riscv_arithmetic_basic_test >> ${SIM}/questa/regression.log 2>&1
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make rvdv test_name=riscv_amo_test >> ${SIM}/questa/regression.log 2>&1
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make rvdv test_name=riscv_ebreak_debug_mode_test >> ${SIM}/questa/regression.log 2>&1
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make rvdv test_name=riscv_ebreak_test >> ${SIM}/questa/regression.log 2>&1
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make rvdv test_name=riscv_floating_point_arithmetic_test >> ${SIM}/questa/regression.log 2>&1
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make rvdv test_name=riscv_floating_point_mmu_stress_test >> ${SIM}/questa/regression.log 2>&1
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make rvdv test_name=riscv_floating_point_rand_test >> ${SIM}/questa/regression.log 2>&1
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make rvdv test_name=riscv_full_interrupt_test >> ${SIM}/questa/regression.log 2>&1
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make rvdv test_name=riscv_hint_instr_test >> ${SIM}/questa/regression.log 2>&1
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make rvdv test_name=riscv_illegal_instr_test >> ${SIM}/questa/regression.log 2>&1
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make rvdv test_name=riscv_invalid_csr_test >> ${SIM}/questa/regression.log 2>&1
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||||
make rvdv test_name=riscv_jump_stress_test >> ${SIM}/questa/regression.log 2>&1
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make rvdv test_name=riscv_loop_test >> ${SIM}/questa/regression.log 2>&1
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make rvdv test_name=riscv_machine_mode_rand_test >> ${SIM}/questa/regression.log 2>&1
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make rvdv test_name=riscv_mmu_stress_test >> ${SIM}/questa/regression.log 2>&1
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make rvdv test_name=riscv_no_fence_test >> ${SIM}/questa/regression.log 2>&1
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||||
make rvdv test_name=riscv_non_compressed_instr_test >> ${SIM}/questa/regression.log 2>&1
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||||
make rvdv test_name=riscv_pmp_test >> ${SIM}/questa/regression.log 2>&1
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||||
make rvdv test_name=riscv_privileged_mode_rand_test >> ${SIM}/questa/regression.log 2>&1
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||||
make rvdv test_name=riscv_rand_instr_test >> ${SIM}/questa/regression.log 2>&1
|
||||
make rvdv test_name=riscv_rand_jump_test >> ${SIM}/questa/regression.log 2>&1
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make rvdv test_name=riscv_sfence_exception_test >> ${SIM}/questa/regression.log 2>&1
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||||
make rvdv test_name=riscv_unaligned_load_store_test >> ${SIM}/questa/regression.log 2>&1
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||||
|
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rvdv_combine_coverage:
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mkdir -p sim/regcov
|
||||
cd sim/regcov && rm -rf *
|
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vcover merge sim/regcov/regcov.ucdb sim/regression_ucdbs/* -suppress 6854 -64
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||||
vcover report -details -html sim/regcov/regcov.ucdb
|
||||
vcover report sim/regcov/regcov.ucdb -details -cvg > sim/regcov/regcov.ucdb.log
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||||
vcover report sim/regcov/regcov.ucdb -testdetails -cvg > sim/regcov/regcov.ucdb.testdetails.log
|
||||
vcover report sim/regcov/regcov.ucdb -details -cvg -below 100 | egrep "Coverpoint|Covergroup|Cross" | grep -v Metric > sim/regcov/regcov.ucdb.summary.log
|
||||
grep "Total Coverage By Instance" sim/regcov/regcov.ucdb.log
|
||||
mkdir -p ${SIM}/questa/regcov
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||||
cd ${SIM}/questa/regcov && rm -rf *
|
||||
vcover merge ${SIM}/questa/regcov/regcov.ucdb ${SIM}/questa/regression_ucdbs/* -suppress 6854 -64
|
||||
vcover report -details -html ${SIM}/questa/regcov/regcov.ucdb
|
||||
vcover report ${SIM}/questa/regcov/regcov.ucdb -details -cvg > ${SIM}/questa/regcov/regcov.ucdb.log
|
||||
vcover report ${SIM}/questa/regcov/regcov.ucdb -testdetails -cvg > ${SIM}/questa/regcov/regcov.ucdb.testdetails.log
|
||||
vcover report ${SIM}/questa/regcov/regcov.ucdb -details -cvg -below 100 | egrep "Coverpoint|Covergroup|Cross" | grep -v Metric > ${SIM}/questa/regcov/regcov.ucdb.summary.log
|
||||
grep "Total Coverage By Instance" ${SIM}/questa/regcov/regcov.ucdb.log
|
||||
|
||||
remove_rvdv_artifacts:
|
||||
rm sim/riscv.ucdb sim/regression.log covhtmlreport/ sim/regression_logs/ sim/regression_ucdbs/ sim/regcov/ -rf
|
||||
rm ${SIM}/questa/riscv.ucdb ${SIM}/questa/regression.log covhtmlreport/ ${SIM}/questa/regression_logs/ ${SIM}/questa/regression_ucdbs/ ${SIM}/questa/regcov/ -rf
|
||||
|
||||
collect_riscvdv_regression_coverage: remove_rvdv_artifacts rvdv_regression rvdv_combine_coverage
|
||||
coverage:
|
||||
|
||||
@ -71,7 +71,7 @@ BTB_SIZE 32'd5
|
||||
# The other syn configurations have the same trimming
|
||||
deriv syn_rv32i rv32i syn_rv32e
|
||||
deriv syn_rv32imc rv32imc syn_rv32e
|
||||
deriv syn_rv32gc syn_rv32e
|
||||
deriv syn_rv32gc rv32gc syn_rv32e
|
||||
deriv syn_rv64i rv64i syn_rv32e
|
||||
deriv syn_rv64gc rv64gc syn_rv32e
|
||||
|
||||
@ -84,7 +84,7 @@ USE_SRAM 1
|
||||
# The other syn configurations have the same trimming
|
||||
deriv syn_sram_rv32i rv32i syn_sram_rv32e
|
||||
deriv syn_sram_rv32imc rv32imc syn_sram_rv32e
|
||||
deriv syn_sram_rv32gc syn_sram_rv32e
|
||||
deriv syn_sram_rv32gc rv32gc syn_sram_rv32e
|
||||
deriv syn_sram_rv64i rv64i syn_sram_rv32e
|
||||
deriv syn_sram_rv64gc rv64gc syn_sram_rv32e
|
||||
|
||||
|
||||
@ -25,6 +25,7 @@ vlib work
|
||||
# remove +acc flag for faster sim during regressions if there is no need to access internal signals
|
||||
# *** modelsim won't take `PA_BITS, but will take other defines for the lengths of DTIM_RANGE and IROM_LEN. For now just live with the warnings.
|
||||
vlog +incdir+$env(WALLY)/config/$1 \
|
||||
+incdir+$env(WALLY)/config/deriv/$1 \
|
||||
+incdir+$env(WALLY)/config/shared \
|
||||
+define+USE_IMPERAS_DV \
|
||||
+define+IDV_INCLUDE_TRACE2COV \
|
||||
@ -62,7 +63,7 @@ eval vsim workopt +nowarn3829 -fatal 7 \
|
||||
-sv_lib $env(IMPERAS_HOME)/lib/Linux64/ImperasLib/imperas.com/verification/riscv/1.0/model \
|
||||
+testDir=$env(TESTDIR) $env(OTHERFLAGS) +TRACE2COV_ENABLE=1
|
||||
|
||||
coverage save -onexit ./riscv.ucdb
|
||||
coverage save -onexit $env(WALLY)/sim/questa/riscv.ucdb
|
||||
|
||||
|
||||
view wave
|
||||
@ -72,7 +73,7 @@ view wave
|
||||
|
||||
run -all
|
||||
|
||||
# noview ../testbench/testbench-imperas.sv
|
||||
# view wave
|
||||
noview $env(WALLY)/testbench/testbench-imperas.sv
|
||||
view wave
|
||||
|
||||
quit -f
|
||||
|
||||
@ -112,9 +112,10 @@ module bitmanipalu import cvw::*; #(parameter cvw_t P) (
|
||||
end else assign ZBKXResult = '0;
|
||||
|
||||
// ZKND and ZKNE AES decryption and encryption
|
||||
if (P.ZKND_SUPPORTED | P.ZKNE_SUPPORTED)
|
||||
if (P.ZKND_SUPPORTED | P.ZKNE_SUPPORTED) begin: zknde
|
||||
if (P.XLEN == 32) zknde32 #(P) ZKN32(.A(ABMU), .B(BBMU), .Funct7, .round(Rs2E[3:0]), .ZKNSelect(ZBBSelect[3:0]), .ZKNDEResult);
|
||||
else zknde64 #(P) ZKN64(.A(ABMU), .B(BBMU), .Funct7, .round(Rs2E[3:0]), .ZKNSelect(ZBBSelect[3:0]), .ZKNDEResult);
|
||||
end else assign ZKNDEResult = '0;
|
||||
|
||||
// ZKNH Unit
|
||||
if (P.ZKNH_SUPPORTED) begin: zknh
|
||||
|
||||
@ -40,80 +40,11 @@ DIRS32 = rv32e rv32gc rv32imc rv32i
|
||||
DIRS64 = rv64i rv64gc
|
||||
DIRS = $(DIRS32) $(DIRS64)
|
||||
|
||||
# k = 3 6
|
||||
# bpred:
|
||||
# @$(foreach kval, $(k), rm -rf $(CONFIGDIR)/rv64gc_bpred_$(kval);)
|
||||
# @$(foreach kval, $(k), cp -r $(CONFIGDIR)/rv64gc $(CONFIGDIR)/rv64gc_bpred_$(kval);)
|
||||
# @$(foreach kval, $(k), sed -i 's/BPRED_SIZE.*/BPRED_SIZE $(kval)/g' $(CONFIGDIR)/rv64gc_bpred_$(kval)/config.vh;)
|
||||
# @$(foreach kval, $(k), make synth DESIGN=wallypipelinedcore CONFIG=rv64gc_bpred_$(kval) TECH=sky90 FREQ=500 MAXCORES=4 --jobs;)
|
||||
|
||||
configs: $(CONFIG)
|
||||
$(CONFIG):
|
||||
@echo $(CONFIG)
|
||||
cp -r $(OLDCONFIGDIR)/shared/*.vh $(CONFIGDIR)
|
||||
# cp -r $(OLDCONFIGDIR)/$(CONFIG)/* $(CONFIGDIR)
|
||||
cp -r $(OLDCONFIGDIR)/deriv/$(CONFIG)/* $(CONFIGDIR)
|
||||
|
||||
# adjust DTIM and IROM to reasonable values depending on config
|
||||
ifneq ($(filter $(CONFIG), $(DIRS32)),)
|
||||
sed -i "s/DTIM_RANGE.*/DTIM_RANGE = 34\'h01FF;/g" $(CONFIGDIR)/config.vh
|
||||
sed -i "s/IROM_RANGE.*/IROM_RANGE = 34\'h01FF;/g" $(CONFIGDIR)/config.vh
|
||||
else ifneq ($(filter $(CONFIG), $(DIRS64)),)
|
||||
sed -i "s/DTIM_RANGE.*/DTIM_RANGE = 56\'h01FF;/g" $(CONFIGDIR)/config.vh
|
||||
sed -i "s/IROM_RANGE.*/IROM_RANGE = 56\'h01FF;/g" $(CONFIGDIR)/config.vh
|
||||
else
|
||||
$(info $(CONFIG) does not exist in $(DIRS32) or $(DIRS64))
|
||||
@echo "Config not in list, RAM_RANGE will be unmodified"
|
||||
endif
|
||||
|
||||
# if USESRAM = 1, set that in the config file, otherwise reduce sizes
|
||||
ifeq ($(USESRAM), 1)
|
||||
sed -i 's/USE_SRAM.*/USE_SRAM = 1;/g' $(CONFIGDIR)/config.vh
|
||||
else
|
||||
sed -i "s/WAYSIZEINBYTES.*/WAYSIZEINBYTES = 32\'d512;/g" $(CONFIGDIR)/config.vh
|
||||
sed -i "s/NUMWAYS.*/NUMWAYS =32\'d1;/g" $(CONFIGDIR)/config.vh
|
||||
sed -i "s/BPRED_SIZE.*/BPRED_SIZE =32\'d5;/g" $(CONFIGDIR)/config.vh
|
||||
sed -i "s/BTB_SIZE.*/BTB_SIZE = 32\'d5;/g" $(CONFIGDIR)/config.vh
|
||||
ifneq ($(filter $(CONFIG), $(DIRS32)),)
|
||||
sed -i "s/BOOTROM_RANGE.*/BOOTROM_RANGE = 34\'h01FF;/g" $(CONFIGDIR)/config.vh
|
||||
sed -i "s/UNCORE_RAM_RANGE.*/UNCORE_RAM_RANGE = 34\'h01FF;/g" $(CONFIGDIR)/config.vh
|
||||
else ifneq ($(filter $(CONFIG), $(DIRS64)),)
|
||||
sed -i "s/BOOTROM_RANGE.*/BOOTROM_RANGE = 56\'h01FF;/g" $(CONFIGDIR)/config.vh
|
||||
sed -i "s/UNCORE_RAM_RANGE.*/UNCORE_RAM_RANGE = 56\'h01FF;/g" $(CONFIGDIR)/config.vh
|
||||
endif
|
||||
endif
|
||||
|
||||
# adjust config if synthesizing with any modifications
|
||||
# This code is subtle with ifneq. It successively turns off a larger
|
||||
# set of features in order of cycle time limiting.
|
||||
# When mod = orig, all features are ON
|
||||
# When mod = PMP0, the number of PMP entries is set to 0
|
||||
# when mod = noPriv, the privileged unit and PMP are disabled
|
||||
# when mod = noFPU, the FPU, privileged unit, and PMP are disabled
|
||||
# when mod = noMulDiv, the MDU, FPU, privileged unit, and PMP are disabled.
|
||||
# when mod = noAtomic, the Atomic, MDU, FPU, privileged unit, and PMP are disabled
|
||||
|
||||
ifneq ($(MOD), orig)
|
||||
# PMP 0
|
||||
sed -i 's/PMP_ENTRIES.*\(64\|16\)/PMP_ENTRIES = 0;/' $(CONFIGDIR)/config.vh
|
||||
ifneq ($(MOD), PMP0)
|
||||
# no priv
|
||||
sed -i 's/ZICSR_SUPPORTED.*1/ZICSR_SUPPORTED = 0;/' $(CONFIGDIR)/config.vh
|
||||
ifneq ($(MOD), noPriv)
|
||||
# turn off FPU
|
||||
sed -i 's/1 *<< *3/0 << 3/' $(CONFIGDIR)/config.vh
|
||||
sed -i 's/1 *<< *5/0 << 5/' $(CONFIGDIR)/config.vh
|
||||
ifneq ($(MOD), noFPU)
|
||||
# no muldiv
|
||||
sed -i 's/1 *<< *12/0 << 12/' $(CONFIGDIR)/config.vh
|
||||
ifneq ($(MOD), noMulDiv)
|
||||
# no atomic
|
||||
sed -i 's/1 *<< *0/0 << 0/' $(CONFIGDIR)/config.vh
|
||||
endif
|
||||
endif
|
||||
endif
|
||||
endif
|
||||
endif
|
||||
cp -rf $(OLDCONFIGDIR)/deriv/$(CONFIG)/config.vh $(CONFIGDIR) | true
|
||||
|
||||
ifeq ($(SAIFPOWER), 1)
|
||||
cp -f ../sim/power.saif .
|
||||
|
||||
@ -7,7 +7,14 @@ import argparse
|
||||
|
||||
def runSynth(config, mod, tech, freq, maxopt, usesram):
|
||||
global pool
|
||||
command = "make synth DESIGN=wallypipelinedcore CONFIG={} MOD={} TECH={} DRIVE=FLOP FREQ={} MAXOPT={} USESRAM={} MAXCORES=1".format(config, mod, tech, freq, maxopt, usesram)
|
||||
if (usesram):
|
||||
prefix = "syn_sram_"
|
||||
else:
|
||||
prefix = "syn_"
|
||||
if (mod != "orig"):
|
||||
prefix = prefix+mod+"_"
|
||||
cfg = prefix + config
|
||||
command = "make synth DESIGN=wallypipelinedcore CONFIG={} MOD={} TECH={} DRIVE=FLOP FREQ={} MAXOPT={} USESRAM={} MAXCORES=1".format(cfg, mod, tech, freq, maxopt, usesram)
|
||||
pool.map(mask, [command])
|
||||
|
||||
def mask(command):
|
||||
|
||||
Loading…
Reference in New Issue
Block a user