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Merge pull request #754 from davidharrishmc/dev

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Integrating riscv-dv
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Rose Thompson 2024-04-24 12:35:39 -05:00 committed by GitHub
commit 85eda21dfe
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9 changed files with 34 additions and 29 deletions
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4
Makefile
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@ -58,12 +58,12 @@ funcovreg:
vcover report -details -html sim/riscv.ucdb
# test_name=riscv_arithmetic_basic_test
rvdv: sim/regression_logs sim/regression_ucdbs
rvdv:
python3 ${WALLY}/addins/riscv-dv/run.py --test ${test_name} --target rv64gc --output tests/output_folder --iterations 1 -si questa --iss spike --verbose --cov --seed 0 --steps gen >> sim/regression_logs/${test_name}.log 2>&1
python3 ${WALLY}/addins/riscv-dv/run.py --test ${test_name} --target rv64gc --output tests/output_folder --iterations 1 -si questa --iss spike --verbose --cov --seed 0 --steps gcc_compile >> sim/regression_logs/${test_name}.log 2>&1
python3 ${WALLY}/addins/riscv-dv/run.py --test ${test_name} --target rv64gc --output tests/output_folder --iterations 1 -si questa --iss spike --verbose --cov --seed 0 --steps iss_sim >> sim/regression_logs/${test_name}.log 2>&1
# run-elf.bash --seed ${WALLY}/sim/seed0.txt --verbose --elf ${WALLY}/tests/output_folder/asm_test/${test_name}_0.o >> sim/regression_logs/${test_name}.log 2>&1
/home/qabid/scripts/run-elf-cov.bash --seed ${WALLY}/sim/seed0.txt --verbose --coverdb sim/riscv.ucdb --elf ${WALLY}/tests/output_folder/asm_test/${test_name}_0.o >> sim/regression_logs/${test_name}.log 2>&1
run-elf-cov.bash --seed ${WALLY}/sim/seed0.txt --verbose --coverdb sim/riscv.ucdb --elf ${WALLY}/tests/output_folder/asm_test/${test_name}_0.o >> sim/regression_logs/${test_name}.log 2>&1
cp sim/riscv.ucdb sim/regression_ucdbs/${test_name}.ucdb
rvdv_regression:

4
README.md
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@ -53,10 +53,6 @@ Edit setup.sh and change the following lines to point to the path and license se
export SNPSLMD_LICENSE_FILE=27020@zircon.eng.hmc.edu # Change this to your Synopsys license server
export QUESTAPATH=/cad/mentor/questa_sim-2021.2_1/questasim/bin # Change this for your path to Questa
export SNPSPATH=/cad/synopsys/SYN/bin # Change this for your path to Design Compiler
export RISCV_TOOLCHAIN=/opt/riscv # Change this for your path to RISCV GNU toolchain
export RISCV_GCC="$RISCV_TOOLCHAIN/bin/riscv64-unknown-elf-gcc" # Copy this as it is
export RISCV_OBJCOPY="$RISCV_TOOLCHAIN/bin/riscv64-unknown-elf-objcopy" # Copy this as it is
export SPIKE_PATH=/usr/bin # Change this for your path to riscv-isa-sim (spike)
If the tools are not yet installed on your server, follow the Toolchain Installation instructions in the section below.

2
addins/riscv-arch-test

@ -1 +1 @@
Subproject commit 59ae6e7073ff40c7e1a1556547b2e8b2ba03ea04
Subproject commit 1498e95cc6163ef1649028c7addf5a514b17e30c

2
addins/riscv-dv

@ -1 +1 @@
Subproject commit f0c570d11236f94f9c5449870223a5ac717cc580
Subproject commit a7e27bc046405f0dbcde091be99f5a5d564e2172

2
bin/regression-wally
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@ -135,6 +135,8 @@ derivconfigtests = [
]
bpredtests = [
["nobpred_rv32gc", ["rv32i"]],
["bpred_TWOBIT_6_16_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
["bpred_TWOBIT_8_16_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
["bpred_TWOBIT_10_16_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],

17
bin/wally-tool-chain-install.sh
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@ -68,7 +68,7 @@ cd $RISCV
git clone https://github.com/riscv/riscv-gnu-toolchain
cd riscv-gnu-toolchain
./configure --prefix=${RISCV} --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;"
make -j ${NUM_THREADS}
make -j 8
# elf2hex (https://github.com/sifive/elf2hex)
#The elf2hex utility to converts executable files into hexadecimal files for Verilog simulation.
@ -92,7 +92,7 @@ cd $RISCV
git clone --recurse-submodules https://github.com/qemu/qemu
cd qemu
./configure --target-list=riscv64-softmmu --prefix=$RISCV
make -j ${NUM_THREADS}
make -j 8
make install
# Spike (https://github.com/riscv-software-src/riscv-isa-sim)
@ -103,7 +103,7 @@ git clone https://github.com/riscv-software-src/riscv-isa-sim
mkdir -p riscv-isa-sim/build
cd riscv-isa-sim/build
../configure --prefix=$RISCV
make -j ${NUM_THREADS}
make -j 8
make install
@ -121,7 +121,7 @@ git pull # Make sure git repository is up-to-date
git checkout master
autoconf # Create ./configure script
./configure # Configure and create Makefile
make -j ${NUM_THREADS} # Build Verilator itself (if error, try just 'make')
make -j 8 # Build Verilator itself (if error, try just 'make')
sudo make install
# Sail (https://github.com/riscv/sail-riscv)
@ -158,7 +158,7 @@ sudo make install
#cd z3
#python scripts/mk_make.py
#cd build
#make -j ${NUM_THREADS}
#make -j 8
#make install
#cd ../..
#pip3 install chardet==3.0.4
@ -177,11 +177,8 @@ cd sail-riscv
# For now, use checkout that is stable for Wally
#git checkout 72b2516d10d472ac77482fd959a9401ce3487f60 # not new enough for Zicboz?
export OPAMCLI=2.0 # Sail is not compatible with opam 2.1 as of 4/16/24
# It is faster to just build c_emulator/riscv_sim_RV* than to build all of Sail
#make -j ${NUM_THREADS}
#ARCH=RV32 make -j ${NUM_THREADS}
make -j ${NUM_THREADS} c_emulator/riscv_sim_RV64
ARCH=RV32 make -j ${NUM_THREADS} c_emulator/riscv_sim_RV32
ARCH=RV64 make -j 8 c_emulator/riscv_sim_RV64
ARCH=RV32 make -j 8 c_emulator/riscv_sim_RV32
sudo ln -sf $RISCV/sail-riscv/c_emulator/riscv_sim_RV64 /usr/bin/riscv_sim_RV64
sudo ln -sf $RISCV/sail-riscv/c_emulator/riscv_sim_RV32 /usr/bin/riscv_sim_RV32

10
site-setup.sh
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@ -11,13 +11,13 @@
# Must edit these based on your local environment.
export MGLS_LICENSE_FILE=27002@zircon.eng.hmc.edu # Change this to your Siemens license server for Questa
export SNPSLMD_LICENSE_FILE=27020@zircon.eng.hmc.edu # Change this to your Synopsys license server for Design Compiler
export QUESTA_HOME=/cad/mentor/questa_sim-2023.4/questasim # Change this for your path to Questa, excluding bin
export QUESTA_HOME=/cad/mentor/questa_sim-2023.4 # Change this for your path to Questa, excluding bin
export DC_HOME=/cad/synopsys/SYN # Change this for your path to Synopsys Design Compiler, excluding bin
export VCS_HOME=/cad/synopsys/vcs/U-2023.03-SP2-4 # Change this for your path to Synopsys VCS, exccluding bin
# Tools
# Questa and Synopsys
export PATH=$QUESTA_HOME/bin:$DC_HOME/bin:$VCS_HOME/bin:$PATH
export PATH=$QUESTA_HOME/questasim/bin:$DC_HOME/bin:$VCS_HOME/bin:$PATH
# GCC
export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:$RISCV/riscv-gnu-toolchain/lib:$RISCV/riscv-gnu-toolchain/riscv64-unknown-elf/lib
@ -29,6 +29,11 @@ export PATH=$PATH:$RISCV/bin
# Verilator
export PATH=/usr/local/bin/verilator:$PATH # Change this for your path to Verilator
# environment variables needed for RISCV-DV
export RISCV_GCC=`which riscv64-unknown-elf-gcc` # Copy this as it is
export RISCV_OBJCOPY=`which riscv64-unknown-elf-objcopy` # Copy this as it is
export SPIKE_PATH=/usr/bin # Change this for your path to riscv-isa-sim (spike)
# Imperas OVPsim; put this in if you are using it
#export PATH=$RISCV/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64:$PATH
#export LD_LIBRARY_PATH=$RISCV/imperas_riscv_tests/riscv-ovpsim-plus/bin/Linux64:$LD_LIBRARY_PATH
@ -44,3 +49,4 @@ if [ -e "$IDV" ]; then
export PATH=$IDV/scripts/cvw:$PATH
fi

21
src/generic/mem/rom1p1r.sv
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@ -33,12 +33,6 @@ module rom1p1r #(parameter ADDR_WIDTH = 8, DATA_WIDTH = 32, PRELOAD_ENABLED = 0)
output logic [DATA_WIDTH-1:0] dout
);
`ifdef VERILATOR
import "DPI-C" function string getenvval(input string env_name);
string WALLY_DIR = getenvval("WALLY");
`else
string WALLY_DIR = "$WALLY";
`endif
// Core Memory
bit [DATA_WIDTH-1:0] ROM [(2**ADDR_WIDTH)-1:0];
@ -53,10 +47,21 @@ module rom1p1r #(parameter ADDR_WIDTH = 8, DATA_WIDTH = 32, PRELOAD_ENABLED = 0)
end else begin */
`ifdef VERILATOR
import "DPI-C" function string getenvval(input string env_name);
`endif
initial
if (PRELOAD_ENABLED) begin
if (DATA_WIDTH == 64) $readmemh({WALLY_DIR,"/fpga/src/boot.mem"}, ROM, 0); // load boot ROM for FPGA
else begin // put something in the ROM so it is not optimized away
if (DATA_WIDTH == 64) begin
`ifdef VERILATOR
// because Verilator doesn't automatically accept $WALLY from shell
string WALLY_DIR = getenvval("WALLY");
$readmemh({WALLY_DIR,"/fpga/src/boot.mem"}, ROM, 0); // load boot ROM for FPGA
`else
$readmemh({"$WALLY/fpga/src/boot.mem"}, ROM, 0); // load boot ROM for FPGA
`endif
end else begin // put something in the ROM so it is not optimized away
ROM[0] = 'h00002197;
end
end

1
testbench/testbench-imperas.sv
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@ -324,7 +324,6 @@ module testbench;
((dut.core.lsu.IEUAdrM == ProgramAddrLabelArray["tohost"]) & InstrMName == "SW" );
DCacheFlushFSM #(P) DCacheFlushFSM(.clk(clk),
.reset(reset),
.start(DCacheFlushStart),
.done(DCacheFlushDone));