Ross Thompson
a04aa283cb
partial ifu cleanup.
2022-01-31 16:08:53 -06:00
Ross Thompson
b05abc1795
cleanup.
2022-01-31 13:29:04 -06:00
Ross Thompson
c1311ca56a
Fixed modelsim warning with linux simulation.
2022-01-31 12:57:02 -06:00
Ross Thompson
d2ab17e1af
Repaired linux-wave.do
2022-01-31 12:54:18 -06:00
Ross Thompson
3475e142a5
Repaired wavefile and fixed modelsim warning.
2022-01-31 12:34:17 -06:00
Ross Thompson
1476a79ea2
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-01-31 12:17:37 -06:00
Ross Thompson
fa8914a830
Cleanup busdp.
2022-01-31 12:17:07 -06:00
Ross Thompson
7c3d6bbdb4
Moved lsu virtual memory logic into separate module.
2022-01-31 11:56:03 -06:00
Ross Thompson
e35a8299ec
Encapsulated dtim.
2022-01-31 11:23:55 -06:00
Ross Thompson
dbe40856a2
Removed unused signals in the LSU.
2022-01-31 10:35:35 -06:00
Ross Thompson
bfbc31d184
Moved atomic logic to own module.
2022-01-31 10:28:12 -06:00
Ross Thompson
ef770fd183
Encapsulated the bus data path into a separate module.
2022-01-31 10:15:48 -06:00
Kip Macsai-Goren
1077cf08b0
added machine info test that uses new test library
2022-01-31 05:54:43 +00:00
David Harris
2d112698b7
Replaced || and && with | and &
2022-01-31 01:07:35 +00:00
Ross Thompson
d52c5b0393
LSU and IFU cleanup.
2022-01-28 15:26:06 -06:00
Ross Thompson
de0bef4f5b
Updated wave.do to match the ifu/lsu changes.
2022-01-28 14:37:15 -06:00
Ross Thompson
147d71fd46
Clean up of mmu instances in IFU and LSU.
2022-01-28 14:02:05 -06:00
Ross Thompson
4a8d0cb981
Moved spills to own module.
2022-01-28 13:40:35 -06:00
Ross Thompson
7fedc6b878
Cleaned up the InstrMisalignedFault.
2022-01-28 13:19:24 -06:00
Ross Thompson
1bb8d36308
Moved all instr/load/storeamo faults to mmu with the exception of instr misaligned fault.
2022-01-27 17:11:27 -06:00
Ross Thompson
d7d7c1cb7d
Relocated the misalignment faults.
2022-01-27 16:03:00 -06:00
David Harris
87aa0724a2
IFU cleanup
2022-01-27 17:18:55 +00:00
David Harris
218ff3e25d
IFU cleanup
2022-01-27 16:41:57 +00:00
David Harris
1c22077841
Optimized out second adder from IFU for PC+2
2022-01-27 16:06:24 +00:00
David Harris
62e5c7fd13
Comments in LSU code about restructuring
2022-01-27 15:53:59 +00:00
Ross Thompson
9a9dfcae40
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-01-27 08:45:33 -06:00
Ross Thompson
d38ab9d2d7
Increased number of concurrent tests.
2022-01-27 08:45:25 -06:00
David Harris
975c0e72c8
Set up rv32emc config
2022-01-27 14:37:58 +00:00
Ross Thompson
75c33bc6c9
BPPredWrongM needs to be 0 when there is no branch predictor. BPPredWRongM is only used when there is an icacheflush.
2022-01-27 07:59:59 -06:00
Ross Thompson
b961b104e0
Added colors to regression script to make it easy to pick out success from fail.
2022-01-26 22:40:32 -06:00
Ross Thompson
c3a78553be
Removed mux in PCNextF logic. Minor IFU improvements.
2022-01-26 22:33:26 -06:00
Ross Thompson
23c4ba2777
1. Modified the cache so it can handle the reset delay internally. This removes the mux from the IFU.
...
2. Removed the write address delay from simpleram.sv
3. Fixed rv32tim and rv32ic mode to handle missalignment correctly.
4. Added imperas32i and imperas32c to rv32tim mode.
2022-01-26 18:23:39 -06:00
Ross Thompson
2c982dca03
IFU simplifications.
2022-01-26 13:54:59 -06:00
David Harris
c6adb7b6b1
Updated configs to fix GPIO address to match FU540
2022-01-26 18:16:34 +00:00
David Harris
c60bb68bff
Testgen working for Lab 2
2022-01-26 18:01:51 +00:00
Ross Thompson
728e46a794
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-01-25 19:21:04 -06:00
David Harris
22c84dcd80
simpleram simplification
2022-01-25 19:46:13 +00:00
David Harris
8bf73d0eb3
simpleram simplification
2022-01-25 19:40:07 +00:00
David Harris
f07123ff0f
simpleram simplification
2022-01-25 18:26:31 +00:00
David Harris
7ac44cb3fc
simpleram address simplification
2022-01-25 18:17:33 +00:00
David Harris
5eb71a3bbe
simpleram address simplification
2022-01-25 18:00:50 +00:00
David Harris
d9888c91a6
simpleram clk and reset simplification
2022-01-25 17:34:15 +00:00
David Harris
5cb879129e
Start of IFU cleanup
2022-01-25 17:31:53 +00:00
Ross Thompson
4d4d9ac8cf
Added spill support back into the IROM IFU.
2022-01-21 15:50:54 -06:00
Ross Thompson
4ecc2d029a
Changed the IROM and DTIM memories to behave like edge-triggered srams.
2022-01-21 15:42:54 -06:00
David Harris
c2c7351b24
erge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-01-21 00:12:18 +00:00
David Harris
0bb63e9ad1
Fixed path to riscvOVPsimPlus
2022-01-21 00:12:14 +00:00
Ross Thompson
ec44774c77
Factored out InstrValidNotFlushedM from each csr*.sv to csr.sv
2022-01-20 16:39:54 -06:00
David Harris
ca1f7ce5d3
Renamed wallypipelinedhart to wallypipelinedcore
2022-01-20 16:02:08 +00:00
David Harris
0d0aa59e48
Removed imperas tests from makefile for now
2022-01-20 14:51:56 +00:00
David Harris
f420e63ed0
Added top-level make clean
2022-01-20 14:17:26 +00:00
David Harris
537cb1d1e1
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-01-20 00:04:27 +00:00
Ross Thompson
05ebadacad
Added PCNextF and PostSpillInstrRawF to ila.
2022-01-19 14:05:14 -06:00
David Harris
f966d98e56
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-01-19 00:26:34 +00:00
Ross Thompson
5cf686429d
Merged in the debug ila updates.
2022-01-18 17:29:21 -06:00
Ross Thompson
2508b9d35a
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-01-18 17:19:59 -06:00
Ross Thompson
fdc17f5017
Updated CSR modules to prevent writting the registers when flushing. This only effects architecture writes not side effect writes.
2022-01-18 17:19:33 -06:00
David Harris
1a21e7f011
riscvsingle reparittioned to match Ch4
2022-01-17 16:57:32 +00:00
David Harris
de7b9c127e
Added E extension, and downloaded riscv-dv and embench-iot to addins
2022-01-17 14:42:59 +00:00
David Harris
5842d780a7
Defined rv32e and rv32emc configs
2022-01-17 14:01:01 +00:00
David Harris
8b62130070
lsu cleanup down to 346 lines
2022-01-15 01:19:44 +00:00
David Harris
b967bcede2
LSU Cleanup
2022-01-15 01:11:17 +00:00
David Harris
f7f3882cb8
Moved Dcache into bus block
2022-01-15 00:39:07 +00:00
David Harris
d9e8d16bbe
Renamed LSUStall to LSUStallM
2022-01-15 00:24:16 +00:00
David Harris
b0263012e8
LSU cleanup
2022-01-15 00:11:30 +00:00
David Harris
4c5962095e
LSU cleanup
2022-01-15 00:03:03 +00:00
David Harris
37bf5347cf
LSU cleanup
2022-01-14 23:55:27 +00:00
Ross Thompson
dd1ebb75f0
Fixed spillthreshold warning.
2022-01-14 17:23:39 -06:00
Ross Thompson
9d2a79f180
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-01-14 17:16:53 -06:00
David Harris
380e990def
moved fp to tests
2022-01-14 23:05:59 +00:00
David Harris
291deb5c39
LSU partitioning
2022-01-14 23:02:28 +00:00
David Harris
36d49a8a74
Moved fp tests from testbench to tests/fp
2022-01-14 23:00:46 +00:00
Ross Thompson
db519a0dca
Cleanup IFU comments.
2022-01-14 15:06:30 -06:00
Ross Thompson
a70e12ad75
Optimization in the ifu. Please note this optimization is not strictly correct,
...
but is possible. See comments in the ifu source code for details.
2022-01-14 12:16:48 -06:00
Ross Thompson
a549079672
More ifu cleanup.
2022-01-14 11:19:12 -06:00
Ross Thompson
ce937a35a8
Added tim only test to regression-wally. Minor cleanup to ifu.
2022-01-14 11:13:06 -06:00
James E. Stine
115ea7dbb0
Update to TestFloat for scripts so can run automatically once
...
TestFloat/Softfloat is compiled. Slight change to the README as well.
2022-01-14 09:25:37 -06:00
Ross Thompson
5726b5b640
Added support for logic memory in the IFU and LSU. This disables the bus interface. Peripherals do not work. Also requires using testbench-harvard.sv. I hope to merge this testbench with the main testbench.sv soon.
2022-01-13 22:21:43 -06:00
Ross Thompson
9f7e3f147b
Partial local dtim in lsu configuration.
2022-01-13 17:50:31 -06:00
David Harris
d356a0d29f
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-01-13 21:46:00 +00:00
David Harris
e3f6c398b5
Mixed C and assembly language test cases; SRT initial version passing tests
2022-01-13 21:45:54 +00:00
Ross Thompson
0b06fa12ef
Merge branch 'testDivInterruptInterlock' into main
2022-01-13 11:21:48 -06:00
Ross Thompson
93cb24476f
Fixed interger divide so it can be interrupted.
2022-01-13 11:16:50 -06:00
Ross Thompson
4bcabd1a55
Removed unused inputs to hptw.
2022-01-13 11:04:48 -06:00
Ross Thompson
654a33bf92
Fixed bug in the lsu's write back data. If an AMO was uncached it would not be corrected executed because the write data to the bus would not include the amoalu.
2022-01-12 17:41:39 -06:00
Ross Thompson
861450c4d6
Fixed support to allow spills and no icache.
2022-01-12 17:25:16 -06:00
Ross Thompson
000d713cb5
Better solution to the integer divider interrupt interaction.
2022-01-12 14:22:18 -06:00
Ross Thompson
26fb09c868
Added additional fsm to ILA.
2022-01-12 14:17:16 -06:00
Ross Thompson
6eb2f37ce4
Possible fix for the TrapM DTLBMiss suppression.
2022-01-12 14:17:16 -06:00
Ross Thompson
6b483e621d
If a trap occurs concurrent with a I/DTLB miss the interlock fsm incorrectly goes into the states to handle the TLB miss.
...
This commit fixes this bug by keeping the interlock fsm in the T0_READY state on TrapM.
2022-01-12 14:17:16 -06:00
Ross Thompson
48c036a923
Oups. My hack for DivE interrupt prevention was wrong.
2022-01-12 14:17:16 -06:00
Ross Thompson
796316495d
Hack "fix" to prevent interrupt from occuring during an integer divide.
...
This is not the desired solution but will allow continued debuging of linux.
2022-01-12 14:17:16 -06:00
Ross Thompson
ecd3912900
Set rv32ic to not use icache.
2022-01-12 14:10:09 -06:00
Ross Thompson
2ed052f152
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-01-12 13:29:19 -06:00
Ross Thompson
87485f9f64
Improve wavefile by adding performance counters.
2022-01-12 10:53:29 -06:00
Kip Macsai-Goren
c99456d5e7
Fixed PMA regions, Added passing PMA tests to regression
2022-01-10 22:08:26 +00:00
David Harris
4cae11ad28
Merged coremark changes
2022-01-10 05:09:28 +00:00
David Harris
50c17f2a03
Removed unused coremark_bare
2022-01-10 05:05:55 +00:00
David Harris
467aac8463
Added riscvsingle. Removed unnecessary coremark config. Added compiler flags for Coremark.
2022-01-10 05:04:13 +00:00
Ross Thompson
55456e465c
Added icache access and icache miss to performance counters.
2022-01-09 22:56:56 -06:00
