David Harris
1aa1908994
Deleted vish_stacktrace
2021-05-17 18:39:01 -04:00
Thomas Fleming
a191978a97
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-05-14 07:40:08 -04:00
Thomas Fleming
1fc607b399
Remove busy-mmu and fix missing signal
2021-05-14 07:14:20 -04:00
Jarred Allen
dc41623754
Minor fixes in regression
2021-05-09 13:57:09 -04:00
Jarred Allen
788680fa4d
Fix bug in regression script
2021-05-06 12:56:57 -04:00
Jarred Allen
15da77fe15
Clean up regression script and document it
2021-05-04 18:58:59 -04:00
Thomas Fleming
d53afc8510
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-05-03 23:15:39 -04:00
Elizabeth Hedenberg
08bfaeffe3
coremark print statment
2021-05-03 19:35:08 -04:00
Elizabeth Hedenberg
81ed9b5d06
coremark directory changes
2021-05-03 19:35:06 -04:00
Ross Thompson
21c0ee0cf2
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-05-03 16:56:00 -05:00
Ross Thompson
ed4f2ecb24
fixed subtle typo in icache fsm. Was messing up hit spill hit.
...
I believe the mibench qsort benchmark runs after this icache fix.
2021-05-03 16:55:36 -05:00
Thomas Fleming
3f7061d557
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-05-03 17:38:13 -04:00
Jarred Allen
a21b84e2ad
Add lint to regression
2021-05-03 17:32:05 -04:00
Ross Thompson
0a44d4dd4e
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-05-03 14:53:54 -05:00
Ross Thompson
7185905f7b
Reduced icache to 1 port memory.
2021-05-03 14:47:49 -05:00
Thomas Fleming
94d734cca9
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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Conflicts:
wally-pipelined/src/ebu/ahblite.sv
2021-05-03 14:02:19 -04:00
Ross Thompson
12b978fec2
Eliminated extra register and fixed ports to icache.
...
Still need to support physical tag check and write in icache memory.
Still need to reduce to 1 port SRAM in icache.
I would like to refactor the icache code.
2021-05-03 12:04:54 -05:00
bbracker
1db608fbc6
small rv64 plic test bugfix
2021-05-03 10:06:44 -04:00
Ross Thompson
fdf4954a20
Added back in function name to wave.do
2021-05-03 09:04:48 -05:00
Noah Boorstin
c9fcd3405d
rollback regression to 400k instrs for busybear
2021-04-29 20:59:30 -04:00
Thomas Fleming
10c7260980
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-04-29 16:30:00 -04:00
Domenico Ottolia
99a927be47
Add medeleg tests
2021-04-29 15:02:36 -04:00
Jarred Allen
c6996ce39d
Remove signal which no longer exists from default waves, so sim-wally works
2021-04-29 14:41:10 -04:00
Thomas Fleming
d29ddddc3f
Remove unused waves from .do files
2021-04-29 02:19:46 -04:00
Thomas Fleming
6515c0b9ed
Add mmu waves (commented) to busybear
2021-04-28 20:01:05 -04:00
Ross Thompson
d191bc6cc1
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-04-26 14:28:09 -05:00
Ross Thompson
14a69c1d06
Added the ability to exclude branch predictor.
2021-04-26 14:27:42 -05:00
Noah Boorstin
24bbb674d3
linux: start using internal branch predictor signal
2021-04-26 14:34:38 -04:00
Noah Boorstin
9cbc769083
minor busybear fixes
2021-04-26 13:24:39 -04:00
Ross Thompson
44d28dbd1c
Icache integrated!
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Merge branch 'icache-almost-working' into main
2021-04-26 11:48:58 -05:00
bbracker
7947858481
it says I need to merge in order to pull
2021-04-26 07:46:24 -04:00
bbracker
8d77012995
progress on bus and lrsc
2021-04-26 07:43:16 -04:00
Ross Thompson
9e40fb072c
Merge branch 'tests' into icache-almost-working
2021-04-25 21:25:36 -05:00
bbracker
46a1616079
thomas fixed it before I did
2021-04-24 09:38:52 -04:00
bbracker
5687ab1c96
do script refactor
2021-04-24 09:32:09 -04:00
Ross Thompson
d7fea1ba3c
almost working icache.
2021-04-23 16:47:23 -05:00
Jarred Allen
9a88d83851
Remind people to run make allclean when a regression fails
2021-04-22 19:21:00 -04:00
Ross Thompson
c9bdaceddb
Fixed icache for 32 bit.
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Merge branch 'cache' into main
2021-04-22 16:45:29 -05:00
Ross Thompson
04eb302925
Yes. The hack to not repeat the d memory operation fixed this issue.
2021-04-22 15:22:56 -05:00
Jarred Allen
8baa2a350d
Add buildroot to regression test
2021-04-22 13:34:56 -04:00
Ross Thompson
7c8d2e9b78
Partially working icache.
...
The current issue is a StallF is required to halt the icache from getting an updated PCF. However
if the dmemory is the reason for a stall it is possible for the icache stall to hold the d memory request continuously causing d memory to repeatedly read from memory. This keeps StallF high and
the icache FSM is never allowed to complete.
2021-04-22 10:20:36 -05:00
Ross Thompson
50e893eec9
Fixed for the instruction spills.
2021-04-21 16:47:05 -05:00
Ross Thompson
269ea7997c
major progress.
...
It's running the icache is imperas tests now.
Compressed does not work yet.
2021-04-21 08:39:54 -05:00
Ross Thompson
a861a37b72
Why was the linter messed up?
...
There are a number of combo loops which need fixing outside the icache. They may be fixed in main.
We get to instruction address 50 now!
2021-04-20 22:06:12 -05:00
Ross Thompson
daa1ab9261
Progress on icache. Fixed some issues aligning the PC with instruction. Still broken.
2021-04-20 21:19:53 -05:00
Ross Thompson
649589ee2c
Broken icache. Design is done. Time to debug.
2021-04-20 19:55:49 -05:00
Jarred Allen
59b340dac9
Merge branch 'main' into cache
2021-04-19 00:05:23 -04:00
Noah Boorstin
5902637632
buildroot: sim is now running!
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yes it only gets through 5 instructions right now. Yes that's my fault.
2021-04-17 14:44:32 -04:00
Noah Boorstin
541fb22dc9
start to add buildroot testbench
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This still uses testbench-busybear.sv
I think it might be time to finally rename nearly 'busybear' thing to 'linux'
2021-04-16 23:27:29 -04:00
bbracker
195cead01c
working GPIO interrupt demo
2021-04-15 21:09:15 -04:00
