Ross Thompson 7c8d2e9b78 Partially working icache. ... The current issue is a StallF is required to halt the icache from getting an updated PCF. However if the dmemory is the reason for a stall it is possible for the icache stall to hold the d memory request continuously causing d memory to repeatedly read from memory. This keeps StallF high and the icache FSM is never allowed to complete.		2021-04-22 10:20:36 -05:00
..
wave-dos	Merge branch 'main' into cache	2021-04-19 00:05:23 -04:00
regression-wally.py	regression: use busybear batch instead	2021-03-25 15:34:10 -04:00
run_sim.sh	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-03-30 15:25:07 -04:00
sim-buildroot	start to add buildroot testbench	2021-04-16 23:27:29 -04:00
sim-buildroot-batch	start to add buildroot testbench	2021-04-16 23:27:29 -04:00
sim-busybear
sim-busybear-batch
sim-peripherals	Yee hoo first draft of PLIC plus self-checking tests	2021-04-04 06:40:53 -04:00
sim-wally
sim-wally-batch	Fixed issue with sim-wally-batch. Are people still using this script?	2021-03-17 11:17:52 -05:00
sim-wally-batch-muldiv	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-03-30 15:25:07 -04:00
sim-wally-batch-rv32ic	fixed sim-wally-32ic	2021-04-08 13:40:16 -04:00
sim-wally-rv32ic	fixed sim-wally-32ic	2021-04-08 13:40:16 -04:00
vish_stacktrace.vstf	Added some updates to divider - still not working all the time. Still a bug with signals within muldiv - specificaly MultDivE being modified during Execute stage. Seems to be triggered by ahblite signal.	2021-04-02 06:27:37 -05:00
wally-buildroot-batch.do	start to add buildroot testbench	2021-04-16 23:27:29 -04:00
wally-buildroot.do	buildroot: sim is now running!	2021-04-17 14:44:32 -04:00
wally-busybear-batch.do	busybear: clean up questa warnings	2021-03-31 14:02:15 -04:00
wally-busybear.do	busybear: clean up questa warnings	2021-03-31 14:02:15 -04:00
wally-coremark_bare.do	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-03-30 15:25:07 -04:00
wally-coremark.do	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-03-30 15:25:07 -04:00
wally-pipelined-batch-muldiv.do	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-03-30 15:25:07 -04:00
wally-pipelined-batch.do	Condense the parallel and non-parallel wally-pipelined-batch.do files into one	2021-03-16 18:15:13 -04:00
wally-pipelined-muldiv.do	Added some updates to divider - still not working all the time. Still a bug with signals within muldiv - specificaly MultDivE being modified during Execute stage. Seems to be triggered by ahblite signal.	2021-04-02 06:27:37 -05:00
wally-pipelined-ross.do	Converted branch predictor preloads to use system verilog rather than modelsim's load command.	2021-03-15 12:39:44 -05:00
wally-pipelined.do	Merge from branch 'main'	2021-04-08 17:19:34 -04:00
wally-privileged.do	Fix bugs with privileged tests	2021-03-25 14:06:05 -04:00
wave-all.do	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-03-30 15:25:07 -04:00
wave.do	Partially working icache.	2021-04-22 10:20:36 -05:00