Ross Thompson 12b978fec2 Eliminated extra register and fixed ports to icache. ... Still need to support physical tag check and write in icache memory. Still need to reduce to 1 port SRAM in icache. I would like to refactor the icache code.		2021-05-03 12:04:54 -05:00
..
wave-dos	Remove signal which no longer exists from default waves, so sim-wally works	2021-04-29 14:41:10 -04:00
regression-wally.py	rollback regression to 400k instrs for busybear	2021-04-29 20:59:30 -04:00
run_sim.sh	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-03-30 15:25:07 -04:00
sim-buildroot	start to add buildroot testbench	2021-04-16 23:27:29 -04:00
sim-buildroot-batch	start to add buildroot testbench	2021-04-16 23:27:29 -04:00
sim-busybear
sim-busybear-batch
sim-wally
sim-wally-batch	Fixed issue with sim-wally-batch. Are people still using this script?	2021-03-17 11:17:52 -05:00
sim-wally-batch-muldiv	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-03-30 15:25:07 -04:00
sim-wally-batch-rv32ic	fixed sim-wally-32ic	2021-04-08 13:40:16 -04:00
sim-wally-rv32ic	fixed sim-wally-32ic	2021-04-08 13:40:16 -04:00
vish_stacktrace.vstf	Added some updates to divider - still not working all the time. Still a bug with signals within muldiv - specificaly MultDivE being modified during Execute stage. Seems to be triggered by ahblite signal.	2021-04-02 06:27:37 -05:00
wally-buildroot-batch.do	do script refactor	2021-04-24 09:32:09 -04:00
wally-buildroot.do	do script refactor	2021-04-24 09:32:09 -04:00
wally-busybear-batch.do	do script refactor	2021-04-24 09:32:09 -04:00
wally-busybear.do	minor busybear fixes	2021-04-26 13:24:39 -04:00
wally-coremark_bare.do	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-03-30 15:25:07 -04:00
wally-coremark.do	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-03-30 15:25:07 -04:00
wally-pipelined-batch-muldiv.do	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-03-30 15:25:07 -04:00
wally-pipelined-batch.do	Condense the parallel and non-parallel wally-pipelined-batch.do files into one	2021-03-16 18:15:13 -04:00
wally-pipelined-muldiv.do	Added some updates to divider - still not working all the time. Still a bug with signals within muldiv - specificaly MultDivE being modified during Execute stage. Seems to be triggered by ahblite signal.	2021-04-02 06:27:37 -05:00
wally-pipelined-ross.do
wally-pipelined.do	do script refactor	2021-04-24 09:32:09 -04:00
wally-privileged.do	Add medeleg tests	2021-04-29 15:02:36 -04:00
wave-all.do	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-03-30 15:25:07 -04:00
wave.do	Eliminated extra register and fixed ports to icache.	2021-05-03 12:04:54 -05:00