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238 Commits

Author SHA1 Message Date
eroom1966
5f358d1af7 add changes for latest IDV file layout 2023-06-16 16:43:53 +01:00
Ross Thompson
d46500bfe0 Fixed the imperas testbench to work with parameters. 2023-06-16 08:59:52 -05:00
Ross Thompson
f3d35f914a Have the linux testbench working in the mean time. Before the consolidation. 2023-06-15 16:18:37 -05:00
Ross Thompson
4428babda9 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-06-15 15:38:38 -05:00
Ross Thompson
85567841eb Merge branch 'testbench-params2' 2023-06-15 15:31:13 -05:00
Ross Thompson
d2219023c3 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-06-15 14:57:23 -05:00
Ross Thompson
af046d4772 Major cleanup of testbench. 2023-06-15 14:57:05 -05:00
Ross Thompson
75b5c23edd Actually removed old `define configuration file for rv64gc. There were a lot of dangling problems. 2023-06-15 14:05:44 -05:00
Ross Thompson
b8a243827b Found a whole bunch of files still using the old `define configurations. 2023-06-15 13:09:07 -05:00
David Harris
45ee4c2f9f Added BMU instructions to instruction name decoder 2023-06-15 09:26:09 -07:00
Ross Thompson
301d54fea8 Significant refactoring of testbench. 2023-06-14 17:02:49 -05:00
Ross Thompson
4d2bb0ea83 Removed old configs from function name module. 2023-06-14 16:35:55 -05:00
Ross Thompson
8f09e17dc7 Found and fixed the source of the new testbench slow down. I accidentally increased the size of the signature buffer by 10x. 2023-06-14 14:11:25 -05:00
Ross Thompson
6330e8084c more testbench improvements. 2023-06-14 12:23:26 -05:00
Ross Thompson
6e42b9f865 Continued improvements to testbench. 2023-06-14 12:11:55 -05:00
Ross Thompson
10c6c08136 Resolved the duplicated check signature issue. 2023-06-14 11:50:12 -05:00
Ross Thompson
3a78d4ca73 Fixed another issue with the timing of memory resets in the new testbench. 2023-06-13 16:24:38 -05:00
Ross Thompson
af8ca85a5b Now have most of the regression tests running again. 2023-06-13 15:09:40 -05:00
Ross Thompson
836bc4a4f7 Cleaned up testbench more. 2023-06-13 14:05:17 -05:00
Ross Thompson
4bdecf8c6d Compacted memory resets. 2023-06-13 13:57:58 -05:00
Ross Thompson
91a22c3a8a More cleanup. 2023-06-13 13:54:07 -05:00
Ross Thompson
9869b26556 Fixed the multliple reads of the same preload memory file. 2023-06-13 13:52:02 -05:00
Ross Thompson
df62f3964c The testbench now at least runs the arch64i in rv64gc config. Still has several issues 
1. need to remove all dead code
2. seems to still be double reading memory files sometimes.
3. batch mode does not work.
 2023-06-13 13:18:46 -05:00
David Harris
004aeda362 Revert "Update for new layout of ImperasDV files" 2023-06-13 04:17:56 -07:00
Ross Thompson
fe72264de3 The new testbench is almost working except the shadow copy is not working. 2023-06-12 15:08:23 -05:00
Ross Thompson
9eeac21113 Progress towards new testbench. 2023-06-12 14:06:17 -05:00
Ross Thompson
3ef2031791 Created temporary wrapper for lint. 2023-06-12 11:49:51 -05:00
Ross Thompson
ee4352975c This parameterizes the testbench but does not use the verilator updates or the new testbench. 2023-06-12 11:00:30 -05:00
eroom1966
d61ed17730 Update for new layout of ImperasDV files 2023-06-12 09:29:07 +01:00
Ross Thompson
8d1dee5764 Removed comments around commented code for verilator. 2023-06-11 15:30:51 -05:00
Ross Thompson
e27dfb8ce0 Merge branch 'verilator' 2023-06-11 15:28:04 -05:00
James E. Stine
67d21ae3a6 Update testbench-fp thanks to Kevin's help - also fixed add which was broken due to config 2023-06-11 15:15:47 -05:00
David Harris
f68b9c224a Fixed WALLY-trap test case to use menvcfg 2023-06-09 15:24:26 -07:00
Ross Thompson
39c8f11191 Fixed the garbled output in embench transcript. 2023-06-08 10:43:46 -05:00
Ross Thompson
4ddbbd6948 Merge pull request #314 from davidharrishmc/dev 
Make and FP script improvements
 2023-06-06 12:38:26 -04:00
Ross Thompson
918464c236 Found the coremark performance issue. The testbench was continuously forcing the BTB to all zeros. Once fixed it resolved the performance problem. 2023-06-05 15:42:05 -05:00
Ross Thompson
1ceea51d8b Changes required to make verilator compile wally's testbench to c++. Not actually tested in simulation yet. 2023-05-31 16:51:00 -05:00
David Harris
65dd99af0c Support all testfloat tests with parameterized design 2023-05-31 06:30:21 -07:00
Ross Thompson
8648d0c25c Hacked it together, but I think testfloat is working. 2023-05-30 15:51:13 -05:00
Ross Thompson
04d0fd94f0 Merge branch 'param-lim-merge' 2023-05-26 16:25:35 -05:00
Ross Thompson
88cc473c68 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-05-24 13:00:50 -05:00
Ross Thompson
930fb67308 Trying to figure out why the parameterization slowed down modelsim so much. 2023-05-24 12:44:42 -05:00
Ross Thompson
2ddb8c7c78 Merge pull request #297 from davidharrishmc/dev 
Verilator testbench changes
 2023-05-22 13:29:54 -04:00
David Harris
163b05f1ce Removed force from branch predictor initialization 2023-05-22 09:57:41 -07:00
David Harris
84dac82def Initial testbench cleanup for Verilator 2023-05-22 09:51:46 -07:00
Ross Thompson
664231c0da Merge branch 'localhistory' 
Repair to wave file.
Created implementations of local history. Part of my Ph.D. research.
 2023-05-22 10:13:31 -05:00
David Harris
7b0d1a7883 Factored FMA tests out of the main 32/64 f/d tests to run in parallel and speed up sim 2023-05-16 11:37:01 -07:00
Ross Thompson
3a98fb8680 Baseline localhistory with speculative repair built. 2023-05-05 15:23:45 -05:00
Ross Thompson
8b0791b6b5 I think ahead pipelining is working for local history. 2023-05-03 12:52:32 -05:00
Ross Thompson
0904a9b97f Swapped the m and k parameters for local history predictor. 2023-05-02 10:52:41 -05:00
Kevin Wan
9ca738547e fixed tests.vh test lines 2023-04-28 07:47:59 -07:00
Kevin Wan
39c9cd5ee9 added tests for pmppriority module 2023-04-27 16:12:43 -07:00
Noah Limpert
4ec31de316 complete camline coverage on IFU and LSU 2023-04-27 14:26:10 -07:00
Noah Limpert
a0e71c26cb Add in a test that makes match 3 = 0 for all tlb lines 2023-04-20 14:50:06 -07:00
Noah Limpert
7ca44de126 Commiting changes to add coverage to ASID, Global, Megapage size checks. 2023-04-20 14:38:13 -07:00
David Harris
6e612a1693 Update tests.vh 
Missing comma from merge
 2023-04-19 06:23:05 -07:00
David Harris
4cbffd7972 Merge branch 'main' into coverage4 2023-04-19 06:16:07 -07:00
David Harris
b63dff098a Merge branch 'main' into main 2023-04-19 04:50:12 -07:00
David Harris
156a098884 Merge branch 'main' into main 2023-04-19 04:46:51 -07:00
Alec Vercruysse
b3a3af8ed3 add D$ test case to trigger a FlushStage while SetDirtyWay=1 
This hits some conditional coverage in each cacheway.
A cache store hit happens at the same time as a StoreAmoMisalignedFault.
 2023-04-19 01:34:01 -07:00
Alec Vercruysse
cd803bfa44 Cover CacheWay edge case: CacheDataMem we=1 while ce=0. 
This test basically triggers an i$ miss during a d$ (hit) store
operation. It requires some tricky timing (e.g. a flushD right
before the relevant store). I use a script to generate the test.
 2023-04-19 01:34:01 -07:00
Liam
9b72d6ac37 Update tests.vh 2023-04-18 23:15:47 -07:00
Kevin Wan
771124e265 Completely covers all PMPCFG_ARRAY_REGW cases 2023-04-18 21:50:48 -07:00
Kevin Wan
1bdae2285d PMPCFG_ARRAY_REGW cases 2023-04-18 18:43:50 -07:00
Kevin Thomas
db0ca8695a Add PR#252 test file to coverage 2023-04-18 17:57:56 -05:00
Limnanthes Serafini
2d9de7b58f Merge branch 'openhwgroup:main' into code_quality 2023-04-13 19:59:58 -07:00
Limnanthes Serafini
ff72cbc1b2 Finished up testbench reformatting 2023-04-13 19:18:26 -07:00
Limnanthes Serafini
b9c97c6a8c Further indents 2023-04-13 19:07:43 -07:00
Limnanthes Serafini
44356559bc testbench code visual improvements 2023-04-13 19:06:09 -07:00
David Harris
17ecb0103e Merge pull request #243 from Noah-G-L/main 
Pull Request to add tlbKP.S - Fill in cache lines
 2023-04-13 18:13:04 -07:00
Limnanthes Serafini
2e809a4e69 A couple indents->spaces 2023-04-13 17:00:41 -07:00
Noah Limpert
d1cb3ca013 git did not seem to add tests.vh, trying again 2023-04-13 16:59:10 -07:00
Limnanthes Serafini
95586abe09 Merge branch 'cachesim' of https://github.com/AlecVercruysse/cvw into cachesim 2023-04-13 16:54:16 -07:00
Limnanthes Serafini
7d274eae74 Fix of InvalDelayed warning 2023-04-13 16:53:36 -07:00
Ross Thompson
10be07857c Merge pull request #229 from davidharrishmc/dev 
Turned on SVADU_SUPPORTED in rv32/64gc wally-config and in imperas.ic…
 2023-04-12 12:21:03 -05:00
David Harris
e6cb928ab2 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-04-12 02:57:33 -07:00
David Harris
bedb3f95eb Swapped in svadu mmu tests 2023-04-12 02:06:52 -07:00
Limnanthes Serafini
65d29306ef Merge branch 'openhwgroup:main' into cachesim 2023-04-12 01:34:45 -07:00
James Stine
811004ef9f Update testbench-fp to run TestFloat for all FP operations 2023-04-11 22:16:20 -05:00
Limnanthes Serafini
a6545a0f47 Logger significantly improved. 2023-04-11 19:29:51 -07:00
Kevin Box
59e7c9371a Create new pmp tests 
configures all pmpcfg registers in each different address range.
 2023-04-09 16:29:57 -07:00
David Harris
b27199e276 Added vm64check tests to cover IMMU vm64 2023-04-07 21:14:52 -07:00
eroom1966
47999784d6 fix break to simulation testbench 2023-04-06 14:45:41 +01:00
Ross Thompson
7cdd12a40a Merge pull request #206 from AlecVercruysse/coverage2 
i$ coverage improvements
 2023-04-05 17:29:35 -05:00
Alec Vercruysse
8b6b96012d add ram1p1rwe for read-only cache ways (remove byte-enable) 
- increases coverage
 2023-04-05 11:48:18 -07:00
Limnanthes Serafini
9cbc2a8e4c Merge remote-tracking branch 'upstream/main' into cachesim 2023-04-05 09:53:05 -07:00
David Harris
7c71c21810 Merge pull request #201 from ross144/main 
Improved d/i cache loggers
 2023-04-05 06:40:14 -07:00
Limnanthes Serafini
49226a1eb2 Commenting, attribution for sim, minor log changes 2023-04-05 02:43:02 -07:00
Limnanthes Serafini
53cff56a97 Changed logging enables, debug mode in sim. 2023-04-04 23:49:35 -07:00
Limnanthes Serafini
6f7620e7c1 CacheSim edits, tests. I/D$ logging, Lim's version 2023-04-04 21:12:35 -07:00
Ross Thompson
02909b3c57 Fixed the d cache logger. 2023-04-04 14:19:19 -05:00
Ross Thompson
87e88a798f Improved d/i cache logger. 2023-04-04 13:38:32 -05:00
eroom1966
adafc8037d add support for Sstc 2023-04-04 17:20:00 +01:00
David Harris
4e2d80476e Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-04-03 06:13:16 -07:00
James Stine
e513c315c9 Update one bug in testfloat - still have to fix fpdiv but others should now all work 2023-04-02 18:16:23 -05:00
David Harris
c1ec1cb09c Added SSTC support to imperas.ic and wallyTracer. Fixes many of the privileged tests 2023-03-31 10:54:03 -07:00
Sydney Riley
4bd3121364 Manual merge in the coverage64gc 2023-03-29 15:25:27 -07:00
Sydney Riley
b0237eaa8b Starting IFU tests including c.fld compressed instruction 2023-03-29 15:15:47 -07:00
David Harris
115c042015 Turned off hpm counters 2023-03-28 21:28:56 -07:00
David Harris
3dc1c6673d Started adding fpu fctrl tests 2023-03-28 21:13:25 -07:00