Ross Thompson
b3849d8abb
Moved data path logic from icacheCntrl to icache.
2021-08-26 10:58:19 -05:00
Ross Thompson
c83f0a2e99
Removed unused logic in icache.
2021-08-26 10:49:54 -05:00
Ross Thompson
642efbb563
Converted the icache type from logic to state type.
2021-08-26 10:41:42 -05:00
Ross Thompson
b5d6c4fb46
Additional cleanup of ahblite.
2021-08-25 22:53:20 -05:00
Ross Thompson
bf312bb37c
Removed amo logic from ahblite. Removed many unused signals from ahblite.
2021-08-25 22:45:13 -05:00
Ross Thompson
939ff663a5
Forgot to include a few files in the last few commits.
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Also reorganized the dcache by read cpu path, write cpu path, and bus interface path.
Changed i/o names on subwordread to match signals in dcache.
2021-08-25 22:30:05 -05:00
Ross Thompson
d2b3b7345e
Moved dcache fsm to separate module.
2021-08-25 21:37:10 -05:00
Ross Thompson
7be0a73db1
Moved LRU and storage for the LRU into a single module. Also found a subtle bug with the update address used to write the cache's memory.
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This was correct for the LRU but incorrect for the data, tag, valid, and dirty storage.
2021-08-25 21:09:42 -05:00
Ross Thompson
b5eba44417
Replaced dcache generate ORing with or_rows.
2021-08-25 13:46:36 -05:00
Ross Thompson
83cc0266b2
Rename of DCacheMem to cacheway.
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simplified dcache names.
2021-08-25 13:33:15 -05:00
Ross Thompson
c48556836b
Removed generate around the dcache memories.
2021-08-25 13:27:26 -05:00
Ross Thompson
7139279e50
Moved more logic inside the dcache memory.
2021-08-25 13:17:07 -05:00
Ross Thompson
a99b5f648b
partial dcache reorg.
2021-08-25 12:42:05 -05:00
Ross Thompson
699053bab0
Updated linux test bench documenation and scripts.
2021-08-25 10:54:47 -05:00
David Harris
cb13e36d20
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-08-25 06:47:20 -04:00
David Harris
cf1e458ccf
simplified or_rows generation and renamed oneHotDecoder to onehotdecoder
2021-08-25 06:46:41 -04:00
Ross Thompson
b7972eafeb
Added function tracking to linux test bench.
2021-08-24 11:08:46 -05:00
Ross Thompson
bb3e94d68a
Modified the preformance counter's InstRet to include ECALL and EBREAK by changing the hazard logic so these instructions don't self flush the W stage.
2021-08-23 15:46:17 -05:00
Ross Thompson
97653e1aea
Wally previously was overcounting retired instructions when they were flushed.
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InstrValidM was used to control when the counter was updated. However this is
not suppress the counter when the instruction is flushed in the M stage.
2021-08-23 12:24:03 -05:00
Ross Thompson
f006655bdc
Renamed output of qemu trace.
2021-08-22 22:56:34 -05:00
Ross Thompson
b6e2710f5d
Confirmed David's changes to the interrupt code.
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When a timer interrupt occurs it should be routed to the machine interrupt
pending MTIP even if MIDELEG[5] = 1 when the current privilege mode is
Machine. This is true for all the interrupts. The interrupt should not be
masked even though it is delegated to a lower privilege. Since the CPU
is currently in machine mode the interrupt must be taken if MIE.
Additionally added a new qemu script which pipes together all the parsing and
post processing scripts to produce the singular all.txt trace without the
massivie intermediate files.
2021-08-22 21:36:31 -05:00
David Harris
696be3ff68
possible interrupt code
2021-08-22 17:02:40 -04:00
Ross Thompson
c0667f30bb
Fixed bug with coremark do file. When I moved the testbench to have a common set of files i forgot to remove the old path reference to function_radix.sv in wally-coremark_bare.do.
2021-08-19 10:33:11 -05:00
Ross Thompson
95f5ebaf30
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-08-17 16:06:54 -05:00
Ross Thompson
d3417e309b
Minor changes to dcache.
2021-08-17 15:22:10 -05:00
Katherine Parry
facd4062d0
all conversions go through the execute stage result mux
2021-08-16 13:06:09 -04:00
Ross Thompson
66ad510abf
Modified the hptw's simulation error message so that synthesis does not attempt to include this statement.
2021-08-16 10:02:29 -05:00
Ross Thompson
4c8ea89f15
Fixed syntax errors in some floating point modules. This came up in
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Xilinx synthesis.
2021-08-15 16:48:49 -05:00
Ross Thompson
4eca94268c
Added logic to linux test bench to not stop simulation on csr write faults.
2021-08-15 11:13:32 -05:00
Ross Thompson
15085448d7
Updated linux-wave.do to have cursors at the timer interrupt problem.
2021-08-13 17:29:37 -05:00
Ross Thompson
4f1f9d6e37
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-08-13 17:23:04 -05:00
Ross Thompson
4f3f26c5cb
Switched ExceptionM to dcache to be just exceptions.
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Added test bench logic to hold forces until the W stage is unstalled.
2021-08-13 15:53:50 -05:00
Ross Thompson
492b6f0ea4
Fixed bugs with CSR checking. The parsing algorithm was messing up the token order after the CSR token.
2021-08-13 14:53:43 -05:00
Ross Thompson
a1c26a16d6
Cleaned up the linux testbench by removing old code and signals.
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Added back in the csr checking logic.
Added code to force timer, external, and software interrupts by using the expected
values from qemu's (m/s)cause registers.
Still need to prevent wally's timer interrupt.
2021-08-13 14:39:05 -05:00
Katherine Parry
567260751a
move some FPU select muxs to execute stage
2021-08-13 14:41:22 -04:00
Ross Thompson
65490fb995
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-08-12 18:05:48 -05:00
Ross Thompson
272425c41f
Added documentation about how the dcache and ptw interact.
2021-08-12 18:05:36 -05:00
Ross Thompson
618cc18903
Optimized subwordread to reduce critical path from 8 muxes to 5 muxes + 1 AND gate.
2021-08-12 13:36:33 -05:00
Ross Thompson
3b327c949f
Minor cleanup of the linux test bench.
2021-08-12 11:14:55 -05:00
Abe
25d828eb28
Made a backup folder accessible to everyone for 3 portme directories that would not be preserved in the case of a clean coremark installation.
2021-08-12 05:23:04 -04:00
Ross Thompson
4dfe326761
Removed unused states from dcache fsm.
2021-08-11 17:06:09 -05:00
Ross Thompson
192392b524
Modified invalid plic reads to return 0 rather than deadbeaf.
2021-08-11 16:56:22 -05:00
Ross Thompson
d0afa397ba
Simplified Dcache by sharing the read data mux with the victim selection mux.
2021-08-11 16:55:55 -05:00
Ross Thompson
74e5b60819
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-08-10 13:36:29 -05:00
Ross Thompson
05a32508eb
Dcache and LSU clean up.
2021-08-10 13:36:21 -05:00
Katherine Parry
21555c392f
LZA added to FMA and attemting a merged FMA and adder in synthesis
2021-08-10 13:57:16 -04:00
Ross Thompson
467e24c05c
Fixed another bug with the atomic instrucitons implemention in the dcache.
2021-08-08 22:50:31 -05:00
Ross Thompson
20a04d8cee
Fixed another bug with AMO. If the CPU stalled as an AMO was finishing, the write to the
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cache's SRAM would occur. Then in the next cycle the SRAM would be reread while stalled
providing the new update dated rather than the correct older value.
2021-08-08 11:42:10 -05:00
Ross Thompson
25533bdc49
Fixed the AMO dcache bug. The subword write needs to occur before the AMO logic.
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Fixed logic for trace update in the M and W stages. The M stage should not update if there
is an instruction fault.
2021-08-08 00:28:18 -05:00
Ross Thompson
fda9985382
Finally past the CLINT issues.
2021-08-06 16:41:34 -05:00
