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Configurable RISC-V Processor
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SystemVerilog 33.8%
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Assembly 17.5%
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C 5.8%
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20a04d8cee
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Ross Thompson 20a04d8cee Fixed another bug with AMO. If the CPU stalled as an AMO was finishing, the write to the 
cache's SRAM would occur.  Then in the next cycle the SRAM would be reread while stalled
providing the new update dated rather than the correct older value.
2021-08-08 11:42:10 -05:00
riscv-coremark Updated location to find compiler for coremark 2021-07-16 19:13:18 -04:00
testsBP Added special tests for checking the accuracy of global and gshare branch 2021-06-04 11:01:54 -05:00
wally-pipelined Fixed another bug with AMO. If the CPU stalled as an AMO was finishing, the write to the 2021-08-08 11:42:10 -05:00
.gitattributes moved shared constants to a shared directory 2021-06-03 22:41:30 -04:00
.gitignore separated buildroot debugging from buildroot logging 2021-07-17 14:52:34 -04:00
.gitmodules Flow updated for 90nm 2021-07-01 13:32:42 -05:00
LICENSE Initial Checkin 2021-01-14 23:37:51 -05:00
README.md Initial commit 2021-01-14 20:16:47 -08:00

README.md

riscv-wally

Configurable RISC-V Processor