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Configurable RISC-V Processor
1,588 Commits 4 Branches 2 Tags 52 MiB
SystemVerilog 33.8%
Python 19.2%
Assembly 17.5%
Tcl 16.2%
C 5.8%
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192392b524
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Ross Thompson 192392b524 Modified invalid plic reads to return 0 rather than deadbeaf.
2021-08-11 16:56:22 -05:00
riscv-coremark
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wally-pipelined Modified invalid plic reads to return 0 rather than deadbeaf. 2021-08-11 16:56:22 -05:00
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.gitignore separated buildroot debugging from buildroot logging 2021-07-17 14:52:34 -04:00
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README.md

riscv-wally

Configurable RISC-V Processor