Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-01-24 13:34:28 +00:00
Code Issues Packages Projects Releases Wiki Activity
Configurable RISC-V Processor
1,622 Commits 4 Branches 2 Tags 52 MiB
SystemVerilog 33.8%
Python 19.2%
Assembly 17.5%
Tcl 16.2%
C 5.8%
Other 7.4%
7be0a73db1
Go to file
Ross Thompson 7be0a73db1 Moved LRU and storage for the LRU into a single module. Also found a subtle bug with the update address used to write the cache's memory. 
This was correct for the LRU but incorrect for the data, tag, valid, and dirty storage.
2021-08-25 21:09:42 -05:00
riscv-coremark Made a backup folder accessible to everyone for 3 portme directories that would not be preserved in the case of a clean coremark installation. 2021-08-12 05:23:04 -04:00
testsBP Added special tests for checking the accuracy of global and gshare branch 2021-06-04 11:01:54 -05:00
wally-pipelined Moved LRU and storage for the LRU into a single module. Also found a subtle bug with the update address used to write the cache's memory. 2021-08-25 21:09:42 -05:00
.gitattributes moved shared constants to a shared directory 2021-06-03 22:41:30 -04:00
.gitignore separated buildroot debugging from buildroot logging 2021-07-17 14:52:34 -04:00
.gitmodules Flow updated for 90nm 2021-07-01 13:32:42 -05:00
LICENSE Initial Checkin 2021-01-14 23:37:51 -05:00
README.md Initial commit 2021-01-14 20:16:47 -08:00

README.md

riscv-wally

Configurable RISC-V Processor