Kevin Kim
a5d1aaa846
fixed fsm bug in tb and typo in intdiv regression flow
2024-12-12 10:09:29 -08:00
Kevin Kim
8ce94388c4
Merge branch 'openhwgroup:main' into divremsqrtport
2024-08-29 16:05:15 -04:00
Rose Thompson
6ad2c2e7a6
Merge pull request #935 from davidharrishmc/dev
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Added lockstep support for RV32. Not all wally privileged tests pass…
2024-08-29 10:45:17 -07:00
David Harris
26f3c2a607
Added lockstep support for RV32. Not all wally privileged tests pass yet
2024-08-29 10:44:37 -07:00
Kevin Kim
99f72b627d
port works, just need to add extra derived configs for k=8
2024-08-28 13:12:39 -07:00
Kevin Kim
fda6305d1c
began porting over divremsqrt
2024-08-27 17:07:35 -07:00
Rose Thompson
113d71f1a0
More name updates.
2024-08-21 10:51:24 -07:00
Rose Thompson
f603d21826
Updated my name in multiple locations.
2024-08-21 10:50:39 -07:00
David Harris
be90457250
Merge pull request #862 from jordancarlin/verilator_fixes
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Remove Verilator hack
2024-08-08 20:50:50 -07:00
David Harris
d4a8377406
Merge pull request #862 from jordancarlin/verilator_fixes
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Remove Verilator hack
2024-08-08 20:50:50 -07:00
David Harris
77c2a86cef
Merge pull request #869 from jordancarlin/installation
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Installation and setup overhaul
2024-08-08 15:39:23 -07:00
David Harris
bc70f0b933
Merge pull request #869 from jordancarlin/installation
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Installation and setup overhaul
2024-08-08 15:39:23 -07:00
David Harris
010038ec32
Depricate conditional generation based on A_SUPPORTED, which is now computed from ZALRSC_SUPPORTED and ZAAMO_SUPPORTED
2024-08-08 05:27:35 -07:00
David Harris
fa98ae8c30
Depricate conditional generation based on A_SUPPORTED, which is now computed from ZALRSC_SUPPORTED and ZAAMO_SUPPORTED
2024-08-08 05:27:35 -07:00
Jordan Carlin
357175f1c8
Merge branch 'main' of https://github.com/openhwgroup/cvw into installation
2024-08-07 20:22:55 -07:00
Jordan Carlin
76eef03fe4
Merge branch 'main' of https://github.com/openhwgroup/cvw into installation
2024-08-07 20:22:55 -07:00
Huda-10xe
2405b6c1e2
Adding RVVI Functional Coverage Support
2024-08-07 14:31:16 +05:00
Huda-10xe
0303314f4e
Adding RVVI Functional Coverage Support
2024-08-07 14:31:16 +05:00
Jacob Pease
11ca2567b8
Merge branch 'main' of github.com:openhwgroup/cvw into spiboot
2024-08-06 17:09:39 -05:00
Jacob Pease
af2344d2d5
Merge branch 'main' of github.com:openhwgroup/cvw into spiboot
2024-08-06 17:09:39 -05:00
Jacob Pease
bd07a60c07
Updated wally source files for zsbl testing.
2024-08-02 15:33:57 -05:00
Jacob Pease
11a057b0b3
Updated wally source files for zsbl testing.
2024-08-02 15:33:57 -05:00
Jordan Carlin
2f1a101735
Merge branch 'main' of https://github.com/openhwgroup/cvw into installation
2024-07-25 21:21:57 -07:00
Jordan Carlin
42a9bbf28d
Merge branch 'main' of https://github.com/openhwgroup/cvw into installation
2024-07-25 21:21:57 -07:00
Jacob Pease
6fc10adc25
Added ability to split boot.memfile into boot.mem and data.mem.
2024-07-25 11:19:15 -05:00
Jacob Pease
336a413f31
Added ability to split boot.memfile into boot.mem and data.mem.
2024-07-25 11:19:15 -05:00
Rose Thompson
5a6e32576d
Fixed the reset bug in wallyTracer.
2024-07-24 13:32:46 -05:00
Rose Thompson
ce61429bdf
Fixed the reset bug in wallyTracer.
2024-07-24 13:32:46 -05:00
Rose Thompson
13db14db6b
Factored out the rvvi testbench code into rvvitbwrapper.
2024-07-24 13:10:57 -05:00
Rose Thompson
d0a5b278b7
Factored out the rvvi testbench code into rvvitbwrapper.
2024-07-24 13:10:57 -05:00
Rose Thompson
c11036358a
Converted fpga's rvvi from a config option to a testbench/fpga top level parameter and is envoked by passing --rvvi to wsim.
2024-07-24 12:47:50 -05:00
Rose Thompson
b1a711ae0f
Converted fpga's rvvi from a config option to a testbench/fpga top level parameter and is envoked by passing --rvvi to wsim.
2024-07-24 12:47:50 -05:00
Jordan Carlin
790f566eaa
Remove hardcoded /opt/riscv
2024-07-23 23:29:45 -07:00
Jordan Carlin
47452ddaaa
Remove hardcoded /opt/riscv
2024-07-23 23:29:45 -07:00
Rose Thompson
35efbd6a54
Changes are confirmed to work on the FPGA.
2024-07-23 17:39:38 -05:00
Rose Thompson
6c212ebf0e
Changes are confirmed to work on the FPGA.
2024-07-23 17:39:38 -05:00
Rose Thompson
02f108345a
Merge branch 'rvvi'
2024-07-22 12:01:01 -05:00
Rose Thompson
7223b15134
Merge branch 'rvvi'
2024-07-22 12:01:01 -05:00
David Harris
f5f8a6c50c
Disable misaligned accesses in imperas configuration and check misaligned support requires D$
2024-07-21 08:26:07 -07:00
David Harris
f30cc46ec5
Disable misaligned accesses in imperas configuration and check misaligned support requires D$
2024-07-21 08:26:07 -07:00
Rose Thompson
9471dcd296
Refactored the fpga and testbench so the RVVI can be synthesized cleanly and simulated without any major code changes.
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Adds three new configuration parameters to control enabling the RVVI packetizer and how much latency should exist between packets and the initial startup delay.
2024-07-19 17:08:47 -05:00
Jordan Carlin
5661dc4a03
Merge branch 'main' of https://github.com/openhwgroup/cvw into installation
2024-07-18 21:36:00 -07:00
Jordan Carlin
8853fd52bc
Merge branch 'main' of https://github.com/openhwgroup/cvw into installation
2024-07-18 21:36:00 -07:00
David Harris
29bd6a30ab
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2024-07-15 04:27:59 -07:00
David Harris
975c72c91d
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2024-07-15 04:27:59 -07:00
David Harris
459eaaef6a
Initial effort to make testbench_fp compatible with Verilator without breaking Questa
2024-07-14 20:08:33 -07:00
Rose Thompson
c53ea43ef9
Merge pull request #880 from davidharrishmc/dev
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wsim elf handling and RV64GCK lockstep support
2024-07-14 11:40:30 -05:00
Rose Thompson
276cb558f0
Merge pull request #880 from davidharrishmc/dev
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wsim elf handling and RV64GCK lockstep support
2024-07-14 11:40:30 -05:00
David Harris
26d4fbcc19
Switched ImperasDV to RV64GCK model to support crypto (issue #872 )
2024-07-13 21:42:14 -07:00
Rose Thompson
f83e6cf771
Fixed issue #874 .
2024-07-08 14:48:52 -05:00
