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cvw/.gitignore

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Add the regression logs and new regression byproducts to the gitignore
2021-02-02 15:43:41 +00:00
**/work*
**/wally_*.log
Add verilator support for wsim.
2024-04-12 03:02:20 +00:00
/**/obj_dir*
/**/gmon*
More testbench setup work - Copy bare-bones testbench from E85 - have testbench instantiate a wallypipelinedhart so we can simulate memory/peripherals easier - Create .gitignore for vsim files - Make PC reset a macro, change to 0x1000 to conform to the bootloader I don't know a good way to put the linux register trace file we're generating on git, since its both nontrivial to make and way to big to keep in a git repo for now it lives in /mnt/scratch/riscv_testbench/
2021-01-21 22:55:05 +00:00
add .nfs* files to gitignore
2021-02-28 20:48:01 +00:00
.nfs*
Add vscode and pycache folders to .gitignore
2021-03-25 06:37:50 +00:00
__pycache__/
.vscode/
gitignore the addins folder because it contains external repos
2021-10-19 20:32:26 +00:00
#External repos
Fixed .gitignore
2021-12-29 18:58:36 +00:00
addins/riscv-arch-test/Makefile.include
lsu cleanup down to 346 lines
2022-01-15 01:19:44 +00:00
addins/riscv-tests/target
Fixed floating Sqrt signal when floating point is disabled, causing REMU tohang during buildroot around 3.2M
2022-12-28 05:24:38 +00:00
addins/TestFloat-3e/build/Linux-x86_64-GCC/*
Ignore benchmark results
2023-11-18 01:02:32 +00:00
gitignore the addins folder because it contains external repos
2021-10-19 20:32:26 +00:00
More testbench setup work - Copy bare-bones testbench from E85 - have testbench instantiate a wallypipelinedhart so we can simulate memory/peripherals easier - Create .gitignore for vsim files - Make PC reset a macro, change to 0x1000 to conform to the bootloader I don't know a good way to put the linux register trace file we're generating on git, since its both nontrivial to make and way to big to keep in a git repo for now it lives in /mnt/scratch/riscv_testbench/
2021-01-21 22:55:05 +00:00
#vsim work files to ignore
transcript
vsim.wlf
Removed pipelined level of hierarchy
2023-02-02 22:14:11 +00:00
wlft*
Busybear test now processes first 100 instrs correctly! - changed test parser to recognize lw in addition to lw also, added temporary questa files (wlft*) to .gitignore
2021-01-28 06:16:39 +00:00
wlft*
Added debug option to disable the function radix if not needed. Function radix slows the simulation by 70 to 76 s (8.5%) for the rv64i tests.
2021-03-10 21:17:02 +00:00
/imperas-riscv-tests/FunctionRadix_32.addr
/imperas-riscv-tests/FunctionRadix_64.addr
gitignore FunctionRadix.addr
2021-03-25 04:13:46 +00:00
/imperas-riscv-tests/FunctionRadix.addr
Added debug option to disable the function radix if not needed. Function radix slows the simulation by 70 to 76 s (8.5%) for the rv64i tests.
2021-03-10 21:17:02 +00:00
/imperas-riscv-tests/ProgramMap.txt
script for running make and logging output
2021-05-18 02:12:18 +00:00
/imperas-riscv-tests/logs
Merge of main with the new icache and the branch predictor. I believe there is a bug in the icache with unaligned memory access. The second part of the access is incorrectly relying on the PCF being the address of the next two bytes of the instruction. However this is not always the case as the branch predictor can get the wrong target address. The icache needs to generate the +2 address internally.
2021-03-31 04:18:20 +00:00
*.o
*.d
Added files to repo
2021-12-05 04:25:33 +00:00
*.vstf
Merge of main with the new icache and the branch predictor. I believe there is a bug in the icache with unaligned memory access. The second part of the access is incorrectly relying on the PCF being the address of the next two bytes of the instruction. However this is not always the case as the branch predictor can get the wrong target address. The icache needs to generate the +2 address internally.
2021-03-31 04:18:20 +00:00
testsBP/*/*/*.elf*
testsBP/*/OBJ/*
testsBP/*/*.a
Updated configs to fix GPIO address to match FU540
2022-01-26 18:16:34 +00:00
tests/wally-riscv-arch-test/riscv-test-suite/*/I/*/*
arch bug fixes and testbench changes
2022-06-17 22:07:16 +00:00
tests/riscof/riscof_work/
added new work files to gitignore
2022-06-17 01:06:25 +00:00
tests/riscof/config32.ini
fixed wally rv32e tests, updated regression makefile to new testflow
2022-07-23 00:09:46 +00:00
tests/riscof/config32e.ini
added new work files to gitignore
2022-06-17 01:06:25 +00:00
tests/riscof/config64.ini
linux testgen refactor
2021-11-01 21:09:49 +00:00
tests/linux-testgen/linux-testvectors/*
!tests/linux-testgen/linux-testvectors/tvCopier.py
!tests/linux-testgen/linux-testvectors/tvLinker.sh
!tests/linux-testgen/linux-testvectors/tvUnlinker.sh
tests/linux-testgen/buildroot
tests/linux-testgen/buildroot-image-output
tests/linux-testgen/buildroot-config-src/main.config.old
tests/linux-testgen/buildroot-config-src/linux.config.old
tests/linux-testgen/buildroot-config-src/busybox.config.old
Add linux/buildroot to .gitignore to ignore the intermediate built for RISCV/buildroot
2024-03-08 20:58:08 +00:00
linux/buildroot
disassembleBootTrace works on first 50M lines of boot
2023-11-23 06:17:01 +00:00
linux/testvector-generation/boottrace.S
linux/testvector-generation/boottrace_disasm.log
Renamed regression to sim
2023-02-02 22:48:23 +00:00
sim/slack-notifier/slack-webhook-url.txt
Created Makefile to manage IP generation.
2021-11-30 00:32:51 +00:00
fpga/generator/IP
Added make clean to fpga IP generator.
2021-11-30 00:42:28 +00:00
fpga/generator/vivado.*
Updated .gitignore file to hide fpga outputs.
2021-12-14 00:30:10 +00:00
fpga/generator/.Xil/*
fpga/generator/WallyFPGA*
fpga/generator/reports/
fpga/generator/*.log
fpga/generator/*.jou
Fixed .gitignore
2021-12-29 18:58:36 +00:00
*.objdump*
*.signature.output
examples/asm/sumtest/sumtest
lsu cleanup down to 346 lines
2022-01-15 01:19:44 +00:00
examples/asm/example/example
Updated configs to fix GPIO address to match FU540
2022-01-26 18:16:34 +00:00
examples/C/sum/sum
Replaced || and && with | and &
2022-01-31 01:07:35 +00:00
examples/C/fir/fir
Created softfloat_demo showcasing how to do math with SoftFloat
2022-02-27 18:17:21 +00:00
examples/fp/softfloat_demo/softfloat_demo
Add files built from examples to gitignore
2024-04-08 19:14:32 +00:00
examples/fp/softfloat_demo/softfloat_demoDP
examples/fp/softfloat_demo/softfloat_demoQP
examples/fp/softfloat_demo/softfloat_demoSP
Enhanced printing intermediate results in fpcalc.c
2022-02-28 04:15:20 +00:00
examples/fp/fpcalc/fpcalc
Add files built from examples to gitignore
2024-04-08 19:14:32 +00:00
examples/fp/sqrttest/sqrttest
ignore example binaries
2023-05-30 06:24:48 +00:00
examples/C/inline/inline
Add files built from examples to gitignore
2024-04-08 19:14:32 +00:00
examples/C/mcmodel/mcmodel
ignore example binaries
2023-05-30 06:24:48 +00:00
examples/C/sum_mixed/sum_mixed
examples/asm/trap/trap
Tested assembly language file for the pause example
2023-10-24 17:45:41 +00:00
examples/asm/etc/pause
Removed pipelined level of hierarchy
2023-02-02 22:14:11 +00:00
src/fma/fma16_testgen
add trimmed-down virt devicetree to repo for QEMU
2022-02-08 11:11:44 +00:00
linux/devicetree/debug/*
rename dump-dts debug script
2022-02-10 00:10:09 +00:00
!linux/devicetree/debug/dump-dts.sh
revived checkpointing and hacked it up to generate a trace starting at the checkpoint
2022-02-25 23:51:40 +00:00
linux/testvector-generation/genCheckpoint.gdb
linux/testvector-generation/silencePipe
linux/testvector-generation/silencePipe.control
linux/testvector-generation/fixBinMem
greatly improve trace-generating checkpoint process with QEMU hack
2022-02-28 23:00:00 +00:00
linux/testvector-generation/qemu-serial
gitignore dtb's because we only care about dts's as being source files
2022-02-08 11:14:59 +00:00
*.dtb
Cleaned up synthesis flow.
2022-02-09 21:18:49 +00:00
synthDC/WORK
synthDC/alib-52
synthDC/*.log
synthDC/*.svf
synthDC/runs/
organizing synth scripts
2022-06-24 06:43:44 +00:00
synthDC/newRuns
organized ppa files into ppa directory
2022-07-05 22:28:25 +00:00
synthDC/ppa/PPAruns
synthDC/ppa/plots
Fixed config file writing for synthesis (#29) * Fixed writing config files for synth sweeps * cleaned up comments
2023-01-26 04:58:15 +00:00
synthDC/wallyplots/
stop tracking runArchive and ppa plots
2022-06-03 22:03:26 +00:00
synthDC/runArchive
Cleaned up synthesis flow.
2022-02-09 21:18:49 +00:00
synthDC/hdl
Renamed regression to sim
2023-02-02 22:48:23 +00:00
sim/power.saif
First version of iterelf running; removed directory support from wsim
2024-07-03 21:54:46 +00:00
tests/fp/vectors
Ignore intermediate files in synthesis sweeps
2022-04-27 13:12:04 +00:00
synthDC/Summary.csv
Added files to gitignore.
2022-12-19 00:53:37 +00:00
tests/custom/work
tests/custom/*/*/*.list
tests/custom/*/*/*.elf
tests/custom/*/*/*.map
tests/custom/*/*/*.memfile
tests/custom/crt0/*.a
More progress on debug.S, but it crashes in Spike
2023-02-04 17:59:22 +00:00
tests/custom/*/*.elf*
Renamed regression to sim
2023-02-02 22:48:23 +00:00
sim/sd_model.log
Removed SDC from repo due to copy right issue. Modified fpga build flow to reference it outside the repo.
2023-01-20 20:35:46 +00:00
fpga/src/sdc/*
fpga/src/sdc.tar.gz
Updated ignore to exclude copied files.
2023-01-21 01:45:17 +00:00
fpga/src/CopiedFiles_do_not_add_to_repo/*
Renamed regression to sim
2023-02-02 22:48:23 +00:00
sim/branch.log
Merge branch 'main' of https://github.com/openhwgroup/cvw This merges the branch predictor improvements into the main repo.
2023-01-29 21:24:20 +00:00
/fpga/generator/sim/imp-funcsim.v
/fpga/generator/sim/imp-timesim.sdf
/fpga/generator/sim/imp-timesim.v
/fpga/generator/sim/syn-funcsim.v
ignore external
2023-01-18 13:22:32 +00:00
external
Renamed regression to sim
2023-02-02 22:48:23 +00:00
sim/results
Ignore new tests from lab
2023-02-15 14:43:00 +00:00
tests/wally-riscv-arch-test/riscv-test-suite/rv*i_m/I/src/*.S
tests/wally-riscv-arch-test/riscv-test-suite/rv*i_m/I/Makefrag
Improved coverage reporting
2023-03-19 17:24:35 +00:00
sim/branch_BP_GSHARE10.log
sim/branch_BP_GSHARE16.log
Moved functional coverage files to sim/questa and to tests/riscvdv
2024-04-24 18:46:38 +00:00
sim/questa/imperas.log
Improved coverage reporting
2023-03-19 17:24:35 +00:00
sim/results-error/
sim/test1.rep
Moved functional coverage files to sim/questa and to tests/riscvdv
2024-04-24 18:46:38 +00:00
sim/questa/vsim.log
Makefile improvements
2023-03-22 18:17:17 +00:00
tests/coverage/*.elf
Git issues, repushing
2023-03-29 11:10:47 +00:00
*.elf.memfile
sim/*Cache.log
Ignore IF_vectors
2023-04-28 13:20:12 +00:00
sim/branch
tests/fp/combined_IF_vectors/IF_vectors/*.tv
Fpga does not correctly boot linux. I think the solution here is to revert out all substantive changes except for parameterization and then add them back in one at a time. This is necessary because the parameterization is not completed in one contiguous group of commits.
2023-06-22 17:55:49 +00:00
/sim/branch-march14.tar.gz
/sim/gshareforward-no-class
/sim/lint-wally_32
/sim/lint-wally_32e
/sim/local16.txt
/sim/localhistory_m6k10_results_april24.txt
/sim/log.log
/sim/obj_dir/Vtestbench.cpp
/sim/obj_dir/Vtestbench.h
/sim/obj_dir/Vtestbench.mk
/sim/obj_dir/Vtestbench__ConstPool_0.cpp
/sim/obj_dir/Vtestbench__Syms.cpp
/sim/obj_dir/Vtestbench__Syms.h
/sim/obj_dir/Vtestbench___024root.h
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__0.cpp
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__0__Slow.cpp
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__1.cpp
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__10.cpp
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__11.cpp
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__1__Slow.cpp
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__2.cpp
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__2__Slow.cpp
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__3.cpp
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__3__Slow.cpp
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__4.cpp
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__4__Slow.cpp
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__5.cpp
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__5__Slow.cpp
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__6.cpp
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__7.cpp
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__8.cpp
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__9.cpp
/sim/obj_dir/Vtestbench___024root__DepSet_hfc24d085__0.cpp
/sim/obj_dir/Vtestbench___024root__DepSet_hfc24d085__0__Slow.cpp
/sim/obj_dir/Vtestbench___024root__Slow.cpp
/sim/obj_dir/Vtestbench___024unit.h
/sim/obj_dir/Vtestbench___024unit__DepSet_hf87c9ffd__0__Slow.cpp
/sim/obj_dir/Vtestbench___024unit__Slow.cpp
/sim/obj_dir/Vtestbench__verFiles.dat
/sim/obj_dir/Vtestbench_classes.mk
/sim/obj_dir/Vtestbench_tlbcam__Pz1_T20_K34_S9.h
/sim/obj_dir/Vtestbench_tlbcam__Pz1_T20_K34_S9__DepSet_h34d4af8f__0.cpp
/sim/obj_dir/Vtestbench_tlbcam__Pz1_T20_K34_S9__DepSet_h34d4af8f__0__Slow.cpp
/sim/obj_dir/Vtestbench_tlbcam__Pz1_T20_K34_S9__DepSet_h845a114e__0.cpp
/sim/obj_dir/Vtestbench_tlbcam__Pz1_T20_K34_S9__DepSet_h845a114e__0__Slow.cpp
/sim/obj_dir/Vtestbench_tlbcam__Pz1_T20_K34_S9__DepSet_h845a114e__1.cpp
/sim/obj_dir/Vtestbench_tlbcam__Pz1_T20_K34_S9__Slow.cpp
/sim/obj_dir/Vtestbench_tlbram__Pz1_T20.h
/sim/obj_dir/Vtestbench_tlbram__Pz1_T20__DepSet_h3df7cb71__0.cpp
/sim/obj_dir/Vtestbench_tlbram__Pz1_T20__DepSet_hab70f5b0__0.cpp
/sim/obj_dir/Vtestbench_tlbram__Pz1_T20__DepSet_hab70f5b0__0__Slow.cpp
/sim/obj_dir/Vtestbench_tlbram__Pz1_T20__Slow.cpp
Cleanup. Linux makefile wally tracer. probably reduce some complexity here.
2023-11-13 20:04:43 +00:00
sim/bp-results/*.log
sim/branch*.log
/tests/custom/fpga-test-sdc/bin/fpga-test-sdc
Ignore benchmark results
2023-11-18 01:02:32 +00:00
benchmarks/embench/wally*.json
benchmarks/embench/run*
sim/cfi.log
Added files to ignore file.
2023-11-26 23:31:23 +00:00
sim/cfi/*
sim/branch/*
Progress on Verilator simulation. Full adder compiles and runs. Wally builds.
2023-12-31 17:53:13 +00:00
sim/obj_dir
examples/verilog/fulladder/obj_dir
Verilator fulladder example improvmeents
2024-04-29 05:08:00 +00:00
examples/verilog/fulladder/fulladder.vcd
Initial derivgen working
2024-01-29 19:22:34 +00:00
config/deriv
Remove buildroot and testvector to avoid duplicate files.
2024-04-15 17:30:14 +00:00
docs/docker/buildroot-config-src
docs/docker/testvector-generation
regression-wally refactoring to support mulitple simulators
2024-04-06 04:45:56 +00:00
sim/questa/cov
Fixed .gitignore
2024-07-15 12:46:35 +00:00
sim/covhtmlreport/
regression-wally refactoring to support mulitple simulators
2024-04-06 04:45:56 +00:00
sim/questa/logs
sim/questa/wkdir
Ignoring more sim files
2024-07-15 12:34:50 +00:00
sim/questa/ucdb
Ignore functional coverage outputs
2024-07-15 21:19:37 +00:00
sim/questa/fcov
sim/questa/fcov_logs
sim/questa/fcov_ucdb
regression-wally refactoring to support mulitple simulators
2024-04-06 04:45:56 +00:00
sim/verilator/logs
sim/verilator/wkdir
sim/vcs/logs
sim/vcs/wkdir
Ignoring more sim files
2024-07-15 12:34:50 +00:00
sim/vcs/ucdb
Ignore coremark_results
2024-04-08 12:57:50 +00:00
benchmarks/coremark/coremark_results.csv
Updated .gitignore for branch prediction results.
2024-04-11 15:31:27 +00:00
fpga/zsbl/OBJ/*
fpga/zsbl/bin/*
sim/*.svg
ignore VCS junk files
2024-04-22 02:49:55 +00:00
sim/vcs/csrc
sim/vcs/profileReport*
sim/vcs/program.out
sim/vcs/sim_out*
sim/vcs/simprofile_dir
sim/vcs/ucli.key
sim/vcs/verdi_config_file
Change all SUPPORTED type localparamters to one bit logic. Update configs for consistency.
2024-05-14 23:24:26 +00:00
sim/vcs/vcdplus.vpd
derived nobpred_rv32gc config for coremark test
2024-04-24 11:41:25 +00:00
sim/*/testbench.vcd
Moved functional coverage files to sim/questa and to tests/riscvdv
2024-04-24 18:46:38 +00:00
sim/questa/imperas.log
Name cleanups
2024-05-04 10:27:39 +00:00
sim/questa/functcov.log
sim/questa/functcov_logs/*
sim/questa/functcov_ucdbs/*
sim/questa/functcov
Moved functional coverage files to sim/questa and to tests/riscvdv
2024-04-24 18:46:38 +00:00
sim/questa/riscv.ucdb
sim/questa/riscv.ucdb.log
sim/questa/riscv.ucdb.summary.log
sim/questa/riscv.ucdb.testdetails.log
tests/riscvdv
Ignore VCS junk output
2024-04-30 15:59:32 +00:00
examples/verilog/fulladder/csrc/
examples/verilog/fulladder/profileReport.html
examples/verilog/fulladder/profileReport.json
examples/verilog/fulladder/profileReport.txt
examples/verilog/fulladder/profileReport/
examples/verilog/fulladder/simprofile_dir/
examples/verilog/fulladder/simv.daidir/
examples/verilog/fulladder/ucli.key
Ignore functcov tests
2024-05-03 18:44:55 +00:00
examples/verilog/fulladder/verdi_config_file
Added gfmul example
2024-05-16 02:29:42 +00:00
examples/crypto/gfmul/gfmul
Ignore functcov tests
2024-05-03 18:44:55 +00:00
tests/functcov
tests/functcov/*
tests/functcov/*/*
Name cleanups
2024-05-04 10:27:39 +00:00
sim/vcs/simprofile*
git ignore
2024-07-06 04:35:10 +00:00
sim/verilator/verilator.log
Refactored the fpga and testbench so the RVVI can be synthesized cleanly and simulated without any major code changes. Adds three new configuration parameters to control enabling the RVVI packetizer and how much latency should exist between packets and the initial startup delay.
2024-07-19 22:08:47 +00:00
/fpga/rvvidaemon/rvvidaemon
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