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add trimmed-down virt devicetree to repo for QEMU

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bbracker 2022-02-08 11:11:44 +00:00
parent 775e07d69a
commit b165fe3937
3 changed files with 83 additions and 0 deletions
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2
.gitignore vendored
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@ -53,3 +53,5 @@ examples/asm/example/example
examples/C/sum/sum
examples/C/fir/fir
synthDC/hdl/*.sv
linux/devicetree/debug/*
!linux/devicetree/debug/dumpdts.sh

6
linux/devicetree/debug/dumpdts.sh Executable file
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@ -0,0 +1,6 @@
#!/bin/bash
machine=virt
qemu-system-riscv64 -M $machine,dumpdtb=$machine.dtb -bios $RISCV/buildroot/output/images/fw_jump.elf
dtc -I dtb -O dts $machine.dtb > $machine.dts

75
linux/devicetree/virt-trimmed.dts Normal file
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@ -0,0 +1,75 @@
/dts-v1/;
/ {
#address-cells = <0x02>;
#size-cells = <0x02>;
compatible = "riscv-virtio-trimmed";
model = "riscv-virtio-trimmed,qemu";
chosen {
linux,initrd-end = <0x85c43a00>;
linux,initrd-start = <0x84200000>;
bootargs = "root=/dev/vda ro";
stdout-path = "/soc/uart@10000000";
};
memory@80000000 {
device_type = "memory";
reg = <0x00 0x80000000 0x00 0x8000000>;
};
cpus {
#address-cells = <0x01>;
#size-cells = <0x00>;
timebase-frequency = <0x989680>;
cpu@0 {
phandle = <0x01>;
device_type = "cpu";
reg = <0x00>;
status = "okay";
compatible = "riscv";
riscv,isa = "rv64imafdcsu";
mmu-type = "riscv,sv48";
interrupt-controller {
#interrupt-cells = <0x01>;
interrupt-controller;
compatible = "riscv,cpu-intc";
phandle = <0x02>;
};
};
};
soc {
#address-cells = <0x02>;
#size-cells = <0x02>;
compatible = "simple-bus";
ranges;
uart@10000000 {
interrupts = <0x0a>;
interrupt-parent = <0x03>;
clock-frequency = <0x384000>;
reg = <0x00 0x10000000 0x00 0x100>;
compatible = "ns16550a";
};
plic@c000000 {
phandle = <0x03>;
riscv,ndev = <0x35>;
reg = <0x00 0xc000000 0x00 0x210000>;
interrupts-extended = <0x02 0x0b 0x02 0x09>;
interrupt-controller;
compatible = "sifive,plic-1.0.0\0riscv,plic0";
#interrupt-cells = <0x01>;
#address-cells = <0x00>;
};
clint@2000000 {
interrupts-extended = <0x02 0x03 0x02 0x07>;
reg = <0x00 0x2000000 0x00 0x10000>;
compatible = "sifive,clint0\0riscv,clint0";
};
};
};