cvw/.gitignore

**/work*
**/wally_*.log

.nfs*

#vsim work files to ignore
transcript
vsim.wlf
wally-pipelined/wlft*
wlft*
Add the regression logs and new regression byproducts to the gitignore 2021-02-02 15:43:41 +00:00			`*/work`
			`*/wally_.log`
More testbench setup work - Copy bare-bones testbench from E85 - have testbench instantiate a wallypipelinedhart so we can simulate memory/peripherals easier - Create .gitignore for vsim files - Make PC reset a macro, change to 0x1000 to conform to the bootloader I don't know a good way to put the linux register trace file we're generating on git, since its both nontrivial to make and way to big to keep in a git repo for now it lives in /mnt/scratch/riscv_testbench/ 2021-01-21 22:55:05 +00:00
add .nfs* files to gitignore 2021-02-28 20:48:01 +00:00			`.nfs*`

More testbench setup work - Copy bare-bones testbench from E85 - have testbench instantiate a wallypipelinedhart so we can simulate memory/peripherals easier - Create .gitignore for vsim files - Make PC reset a macro, change to 0x1000 to conform to the bootloader I don't know a good way to put the linux register trace file we're generating on git, since its both nontrivial to make and way to big to keep in a git repo for now it lives in /mnt/scratch/riscv_testbench/ 2021-01-21 22:55:05 +00:00			`#vsim work files to ignore`
			`transcript`
			`vsim.wlf`
load instructions from file line by line 2021-01-22 19:11:17 +00:00			`wally-pipelined/wlft*`
Busybear test now processes first 100 instrs correctly! - changed test parser to recognize lw in addition to lw also, added temporary questa files (wlft*) to .gitignore 2021-01-28 06:16:39 +00:00			`wlft*`