cvw/pipelined/src
2022-12-23 17:01:34 -06:00
..
cache Revert to 98b824 2022-12-22 23:58:14 -08:00
ebu Success we've replaced TrapM with FlushD in the IFU. 2022-12-22 21:36:49 -06:00
fpu reworked negitive sticky bit handeling in fma 2022-12-23 17:01:34 -06:00
generic Memory cleanup 2022-12-20 11:22:26 -08:00
hazard Renamed IFU and LSU stalls. 2022-12-22 21:56:33 -06:00
ieu IFU mux for CSRWriteFenceM conditional on ZICSR/ZIFENCEI 2022-12-20 15:38:30 -08:00
ifu Renamed IFU and LSU stalls. 2022-12-22 21:56:33 -06:00
lsu Renamed IFU and LSU stalls. 2022-12-22 21:56:33 -06:00
mmu Renamed IFU and LSU stalls. 2022-12-22 21:56:33 -06:00
muldiv Use FlushE to reset integer divider FSM 2022-12-15 11:00:54 -08:00
ppa cleanup, plots for paper 2022-06-15 18:28:36 +00:00
privileged Moved InstrValidNotFLushed to csr including InstrValidM 2022-12-23 00:27:44 -08:00
uncore Fixed minor bug in PLIC. reading interrupt source 0 should not return x. it should provide produce 0. 2022-12-21 09:00:09 -06:00
wally Renamed IFU and LSU stalls. 2022-12-22 21:56:33 -06:00
sdc piplined directory cleanup 2022-01-07 12:43:50 +00:00